CN110911406B - Memory, forming method thereof and semiconductor device - Google Patents
Memory, forming method thereof and semiconductor device Download PDFInfo
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- CN110911406B CN110911406B CN201811075311.9A CN201811075311A CN110911406B CN 110911406 B CN110911406 B CN 110911406B CN 201811075311 A CN201811075311 A CN 201811075311A CN 110911406 B CN110911406 B CN 110911406B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 230000006870 function Effects 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000002360 preparation method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a memory, a forming method thereof and a semiconductor device. The method for forming the memory comprises forming sacrificial layer patterns on a substrate between adjacent bit line combination structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combination structures; node contacts are formed on the contact regions; removing the sacrificial layer pattern to form a second cavity; and forming an insulating sealing layer which is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity so as to define a plurality of isolation cavities between node contacts by using the insulating sealing layer and the adjacent bit line combined structure. Therefore, the preparation process is simple, and the gap in the formed isolation cavity structure is uniform, so that parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a memory, a method for forming the same, and a semiconductor device.
Background
The memory typically includes a storage capacitor for storing a charge representing stored information, and a storage transistor connected to the storage element. An active region, a drain region and a gate structure are formed in the memory transistor. The gate structure is connected to a word line for controlling current flow between the source and drain regions. The source region is used for forming a bit line combination structure contact region for connecting to the bit line combination structure, and the drain region is used for forming a storage node contact region for connecting to the storage capacitor. However, parasitic capacitance is inevitably generated between adjacent bit line combination structures, so that interference of the bit line combination structures is generated, and the performance of the memory is affected.
1-7 Illustrate a method of forming a memory, comprising:
As shown in fig. 1, a bit line combination structure 2 is formed on a substrate 1 with a space 3 between adjacent bit line combination structures 2; as shown in fig. 2, a first dielectric layer 4 is formed on the bit line combined structure 2; as shown in fig. 3, a second dielectric layer 5 is formed in the space 3 on the substrate 1, the second dielectric layer 5 filling the lower half of the space 3; as shown in fig. 4-5, a third dielectric layer 6 is formed to fill the space 3, and side walls 7 are formed by etching, wherein the side walls 7 are positioned on two sides of the upper half part of the space 3 and are not contacted, and a second cavity is formed; referring to fig. 6, the second dielectric layer at the lower half of the space 3 is etched from the second cavity, and removed to form a cavity 8; finally, a fourth dielectric layer 9 is formed to seal the cavity 8.
However, the above-described process is complicated in steps, complicated in process, increased in cost, and increased in risk of potential defects.
Disclosure of Invention
The invention aims to provide a memory, a forming method thereof and a semiconductor device, optimize a preparation process and better reduce parasitic capacitance.
According to a first aspect of the present invention, there is provided a method of forming a memory, comprising:
providing a front end structure, comprising a substrate and a plurality of bit line combined structures arranged on the substrate in a protruding manner;
Forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern is at least filled between adjacent bit line combined structures in a patterning way so as to define a plurality of contact areas on the substrate;
a plurality of node contacts are arranged in contact areas on the substrate, and the node contacts are accommodated in a plurality of first cavities formed by the bit line combination structure and the sacrificial layer patterns in a staggered manner and are electrically contacted with the substrate at the bottom layer;
Removing the sacrificial layer pattern to form a second cavity between the node contacts; and
And forming an insulating sealing layer on the front-end structure, wherein the insulating sealing layer is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by utilizing the insulating sealing layer and the adjacent bit line combined structure.
Optionally, for the method for forming a memory, the bit line combination structure includes: a work function layer, a conductive layer on the work function layer, and an insulating layer on the conductive layer and covering the conductive layer and the work function layer.
Optionally, for the method for forming a memory, the step of forming an insulating capping layer on the front-end structure includes: the insulating capping layer is deposited and partially fills the second cavity toward the substrate but not to a depth of the conductive layer.
Optionally, for the method for forming a memory, the step of forming an insulating capping layer on the front-end structure further includes: and thinning the insulating sealing cover layer until the node contact is exposed, so that the insulating sealing cover layer is formed at the pattern part at the upper part of the isolation cavity to seal the second cavity.
Optionally, for the method for forming a memory, the insulating layer includes a nitride layer.
Optionally, for the method for forming the memory, the aspect ratio of the isolation cavity is greater than 3.
Optionally, for the method for forming a memory, the sacrificial layer includes an oxide layer, and the insulating capping layer includes a nitride layer.
Optionally, for the method for forming the memory, a plasma enhanced chemical vapor deposition process is used to form the insulating capping layer.
According to a second aspect of the present invention, there is provided a memory comprising:
A substrate, a plurality of bit line combination structures positioned on the substrate, and a plurality of contact areas on the substrate are defined between adjacent bit line combination structures;
a plurality of node contacts, which are arranged in contact areas on the substrate and are electrically contacted with the substrate; and
And the insulating sealing layer is lapped on the top of the adjacent bit line combined structure, and the insulating sealing layer and the adjacent bit line combined structure define a plurality of isolation cavities between the node contacts.
Optionally, for the memory, the bit line combination structure includes: a work function layer, a conductive layer on the work function layer, and an insulating layer on the conductive layer and covering the conductive layer and the work function layer.
Optionally, for the memory, the insulating capping layer is formed on a pattern portion on an upper portion of the isolation cavity, but a bottom end of the insulating capping layer is not in contact with the conductive layer.
Optionally, for the memory, the aspect ratio of the isolation cavity is greater than 3.
According to a third aspect of the present invention, there is also provided a semiconductor device including the memory as described above.
The method for forming the memory comprises forming sacrificial layer patterns on a substrate between adjacent bit line combination structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combination structures; node contacts are formed on the contact regions; removing the sacrificial layer pattern to form a second cavity; and forming an insulating sealing layer which is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity so as to define a plurality of isolation cavities between node contacts by using the insulating sealing layer and the adjacent bit line combined structure. Therefore, the preparation process is simple, and the gap in the formed isolation cavity structure is uniform, so that parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Drawings
FIGS. 1-7 are schematic diagrams of a memory during formation;
FIG. 8 is a flowchart of a method for forming a memory according to a first embodiment of the invention;
FIG. 9 is a schematic diagram showing a front-end structure provided by a method for forming a memory according to a first embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of A-A' of FIG. 9;
FIG. 11 is a diagram illustrating a method for forming a sacrificial layer pattern in a memory according to a first embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view of A-A' of FIG. 11;
FIG. 13 is a schematic cross-sectional view of B-B' of FIG. 11;
FIG. 14 is a schematic diagram illustrating a method for forming a node contact in a memory according to a first embodiment of the present invention;
FIG. 15 is a schematic cross-sectional view of A-A' of FIG. 14;
FIG. 16 is a schematic cross-sectional view of B-B' of FIG. 14;
FIG. 17 is a diagram illustrating the removal of the sacrificial layer pattern in the method for forming a memory according to the first embodiment of the present invention;
FIG. 18 is a schematic cross-sectional view of A-A' of FIG. 17;
FIG. 19 is a schematic cross-sectional view of B-B' of FIG. 17;
FIG. 20 is a schematic diagram of depositing an insulating capping layer in a method for forming a memory according to a first embodiment of the invention;
FIG. 21 is a schematic cross-sectional view of A-A' of FIG. 20;
FIG. 22 is a schematic cross-sectional view of B-B' of FIG. 20;
FIG. 23 is a schematic diagram showing a planarization insulating capping layer in a method for forming a memory according to a first embodiment of the present invention;
FIG. 24 is a schematic cross-sectional view of A-A' of FIG. 23;
FIG. 25 is a schematic cross-sectional view of B-B' of FIG. 23.
Wherein, the reference numerals are as follows:
1. 10-a substrate;
101-a contact region;
102-a first cavity;
2. 20-bit line combination structure;
201—a work function layer;
202-a conductive layer;
203-an insulating layer;
3-interval;
30-node contact;
4-a first dielectric layer;
40-sacrificial layer patterns;
5-a second dielectric layer;
50-a second cavity;
6-a third dielectric layer;
60-insulating capping layer;
7-side walls;
8-cavity;
9-fourth dielectric layer.
Detailed Description
The memory and method of forming the same will now be described in greater detail with reference to the drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the beneficial results of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the following description, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, pad, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
The main idea of the present invention is to provide a method for forming a memory, as shown in fig. 8, mainly comprising:
Step S11, providing a front end structure, comprising a substrate and a plurality of bit line combined structures arranged on the substrate in a protruding manner;
Step S12, forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern is at least filled between adjacent bit line combined structures in a patterning way so as to define a plurality of contact areas on the substrate;
Step S13, a plurality of node contacts are arranged in contact areas on the substrate, and the node contacts are accommodated in a plurality of first cavities formed by the bit line combination structure and the sacrificial layer pattern in a staggered manner and are electrically contacted with the substrate at the bottom layer;
Step S14, removing the sacrificial layer pattern to form a second cavity between the node contacts; and
And S15, forming an insulating sealing layer on the front-end structure, wherein the insulating sealing layer is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity so as to define a plurality of isolation cavities between the node contacts by utilizing the insulating sealing layer and the adjacent bit line combined structure.
The preparation process is simple, and the gap in the formed isolation cavity structure is uniform, so that parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Specifically, referring to fig. 9 and 10, for step S11, a front-end structure is provided, which includes a substrate 10 and a plurality of bit line combined structures 20 protrusively disposed on the substrate 10.
For example, the substrate 10 may be a silicon substrate, such as a monocrystalline silicon substrate or the like. Active regions, word lines, etc. may also be formed in the substrate 10.
In one embodiment, as can be seen in fig. 10 and 11, for example, the bit line combination structure 20 includes a work function layer 201, a conductive layer 202 on the work function layer 201, and an insulating layer 203 on the conductive layer 202 and covering the conductive layer 202 and the work function layer 201.
According to practical requirements, a bottom insulating layer (not shown) may be further disposed in a portion of the area between the work function layer 201 and the substrate 10, so as to avoid the electrical connection between the non-bit line structure contact area in the substrate 10 and the formed bit line structure 20.
For example, the conductive layer 202 may be made of tungsten, or may be made of other materials, such as copper, gold, silver, etc.
The insulating layer 203 may be, for example, a nitride layer, for example, a silicon nitride material, or may be silicon oxide, silicon oxynitride, or the like, and in this embodiment, silicon nitride is used.
As shown in fig. 10, the bit line combined structure 20 is higher than the substrate 10, which is equivalent to forming a plurality of isolation barriers on the surface of the substrate 10. In the subsequent process of preparing the storage node contact, the isolation barrier can be fully utilized, and the boundary of the storage node contact is defined in a self-aligned manner.
Referring to fig. 11 to 13, for step S12, a sacrificial layer pattern 40 is formed on the substrate 10, and the sacrificial layer pattern 40 is at least filled between adjacent bit line structures 20 in a patterning manner to define a plurality of contact areas 101 on the substrate 10; the bit line assembly structure 20 and the sacrificial layer pattern 40 are staggered to form a plurality of first cavities 102.
For example, the material of the sacrificial layer pattern 40 may be an oxide layer, such as silicon oxide, or may be a carbon-rich dielectric layer, germanium, hydrocarbon polymer, or amorphous carbon. For example, a silicon oxide layer is selected here. It is understood that the material of the sacrificial layer pattern 40 may have other choices, which are not listed here.
The sacrificial layer pattern 40 may have various forms, for example, the sacrificial layer pattern 40 may be equal in height to the bit line assembly structure 20 in a plurality of blocks, or may be higher than the bit line assembly structure 20 and laterally connected in a stripe shape.
Next, referring to fig. 14 to 16, for step S13, a plurality of contact areas 101 of the node contacts 30 on the substrate 10 are provided, and the node contacts 30 are accommodated in a plurality of first cavities 102 formed by the bit line assembly structure 20 and the sacrificial layer pattern 40 in a staggered manner and electrically contact with the underlying substrate 10.
For example, it may be that the bit line assembly structure 20, the sacrificial layer 40 and the node contact 30 are top surface flush.
Referring to fig. 17 to 19, for step S14, the sacrificial layer pattern is removed to form a second cavity 50 between the node contacts 30.
The sacrificial layer pattern may be removed by a wet etching process.
For example, dilute hydrofluoric acid solution (DHF) may be selected.
Because the sacrificial layer pattern is designed in the invention, the second cavity 50 obtained after the removal has uniform dimensions.
As can be seen from fig. 18 and 19, the removal of the sacrificial layer pattern does not have an effect on the node contact 30. The sacrificial layer between adjacent node contacts 30 between adjacent bit line structures 20 becomes the second cavity 50.
The size range of the second cavity 50 can be set according to practical requirements.
Then, referring to fig. 20 to 25, for step S15, an insulating capping layer 60 is formed on the front-end structure, and the insulating capping layer 60 is overlapped on top of the adjacent bit line combined structure 20 and covers and seals the top opening of the second cavity 50, so as to define a plurality of isolation cavities between the node contacts 30 by using the insulating capping layer 60 and the adjacent bit line combined structure 20.
Specifically, the insulating capping layer 60 is formed, for example, the insulating capping layer 60 may be formed using a plasma enhanced chemical vapor deposition process.
The insulating capping layer 60 may be selected from the group consisting of nitride, oxide, oxynitride, and the like, for example, silicon nitride.
After the deposition process, the insulating capping layer 60 is deposited on the front-end structure, and the insulating capping layer 60 covers the bit line assembly structure 20 and also covers the node contact 30, and meanwhile, the insulating capping layer 60 partially fills the second cavity 50 toward the substrate 10, as shown in fig. 22, and the upper portion of the second cavity 50 is filled and blocked by the insulating capping layer 60, but the filling depth is less than that of the conductive layer 202, i.e., the bottom surface of the insulating capping layer 60 covering the top end of the second cavity 50 is far away from the substrate 10 than the top surface of the conductive layer 202.
In one embodiment, the insulating capping layer 60 covers the second cavity 50 (i.e., the isolation cavity) with an aspect ratio greater than 3.
After the deposition of the insulating capping layer 60 is completed, referring to fig. 23 to 25, the insulating capping layer 60 is thinned until the node contact 30 is exposed, so that the insulating capping layer 60 is formed on the pattern portion at the upper portion of the isolation cavity to close the second cavity 50.
For example, a planarization process is performed to thin the insulating capping layer 60, such as a Chemical Mechanical Polishing (CMP) process, and the insulating capping layer 60 is polished until the bit line assembly structure 20 and the node contact 30 are exposed.
Thus, in practice, the insulating cap 60 is located only at the top of the second cavity 50, and the insulating cap 60 can better overlap the bit line structure due to the insulating layer 203 of the bit line structure 20. In the case of a node contact 30, the insulating capping layer 60 also overlaps the plurality of node contacts 30.
The second cavity is obtained by using the sacrificial layer pattern, and the second cavity is not blocked before the sacrificial layer pattern is removed, namely the sacrificial layer pattern is removed in a simple process, and the removal effect is good. However, in the case shown in fig. 6, the removal of the sacrificial layer is affected by the presence of the sidewall 7, and the effect is poor. The second cavity obtained in the invention has good quality and is more conducive to improving parasitic capacitance.
Through the above process, a memory of the present invention can be obtained, comprising:
a substrate 10, a plurality of bit line combined structures 20 positioned on the substrate 10, and a plurality of contact areas 101 on the substrate 10 are defined between adjacent bit line combined structures 20;
a plurality of node contacts 30 disposed on the substrate 10 at contact areas 101 and electrically contacting the substrate 10; and
An insulating capping layer 60 is overlapped on top of the adjacent bit line assembly structures 20, the insulating capping layer 60 and the adjacent bit line assembly structures 20 defining a plurality of isolation cavities between the node contacts 30.
Thus, the parasitic capacitance between adjacent bit line structures 20, i.e., between conductive layers 202 of adjacent bit line structures 20, is calculated as c=εa/d, where ε is the dielectric constant, a is the relative area of conductors between adjacent bit line structures, and d is the spacing between adjacent bit line structures. It can be seen that the second cavity is between the adjacent bit line structures, and air is located therein, epsilon= 1.00059, and compared with other media such as silicon oxide, epsilon=3.9, the parasitic capacitance C is effectively improved.
The invention also provides a semiconductor device comprising a memory as described above.
The method for forming the memory comprises forming sacrificial layer patterns on a substrate between adjacent bit line combination structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combination structures; node contacts are formed on the contact regions; removing the sacrificial layer pattern to form a second cavity; and forming an insulating sealing layer which is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity so as to define a plurality of isolation cavities between node contacts by using the insulating sealing layer and the adjacent bit line combined structure. Therefore, the preparation process is simple, and the gap in the formed isolation cavity structure is uniform, so that parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (11)
1. A method of forming a memory, comprising:
providing a front end structure, comprising a substrate and a plurality of bit line combined structures arranged on the substrate in a protruding manner;
Forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern is at least filled between adjacent bit line combined structures in a patterning way so as to define a plurality of contact areas on the substrate;
a plurality of node contacts are arranged in contact areas on the substrate, and the node contacts are accommodated in a plurality of first cavities formed by the bit line combination structure and the sacrificial layer patterns in a staggered manner and are electrically contacted with the substrate at the bottom layer;
Removing the sacrificial layer pattern to form a second cavity between the node contacts; and
And forming an insulating sealing layer on the front-end structure, wherein the insulating sealing layer is lapped on the top of the adjacent bit line combined structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by utilizing the insulating sealing layer and the adjacent bit line combined structure.
2. The method of forming a memory of claim 1, wherein the bit line combination structure comprises: a work function layer, a conductive layer on the work function layer, and an insulating layer on the conductive layer and covering the conductive layer and the work function layer.
3. The method of forming a memory of claim 2, wherein the step of forming an insulating capping layer over the front-end structure comprises: the insulating capping layer is deposited and partially fills the second cavity toward the substrate but not to a depth of the conductive layer.
4. The method of forming a memory of claim 3, wherein the step of forming an insulating capping layer over the front-end structure further comprises: and thinning the insulating sealing cover layer until the node contact is exposed, so that the insulating sealing cover layer is formed at the pattern part at the upper part of the isolation cavity to seal the second cavity.
5. The method of forming a memory of claim 2, wherein the insulating layer comprises a nitride layer.
6. The method of claim 1, wherein the isolation cavity has an aspect ratio greater than 3.
7. The method of forming a memory of claim 1, wherein the sacrificial layer comprises an oxide layer and the insulating capping layer comprises a nitride layer.
8. The method of forming a memory of claim 1, wherein the insulating capping layer is formed using a plasma enhanced chemical vapor deposition process.
9. A memory, comprising:
A substrate, a plurality of bit line combination structures positioned on the substrate, and a plurality of contact areas on the substrate are defined between adjacent bit line combination structures;
a plurality of node contacts, which are arranged in contact areas on the substrate and are electrically contacted with the substrate; and
An insulating capping layer overlapping the top of adjacent bit line structures, the insulating capping layer and adjacent bit line structures defining a plurality of isolation cavities between the node contacts;
The bit line combination structure includes: a work function layer, a conductive layer on the work function layer, and an insulating layer on the conductive layer and covering the conductive layer and the work function layer;
the aspect ratio of the isolation cavity is greater than 3.
10. The memory of claim 9 wherein said insulating cap layer is formed in a pattern above said isolation cavity but not at a bottom end of said insulating cap layer to said conductive layer.
11. A semiconductor device comprising the memory according to claim 9 or 10.
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| CN201811075311.9A CN110911406B (en) | 2018-09-14 | 2018-09-14 | Memory, forming method thereof and semiconductor device |
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| CN201811075311.9A CN110911406B (en) | 2018-09-14 | 2018-09-14 | Memory, forming method thereof and semiconductor device |
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| CN110911406B true CN110911406B (en) | 2024-06-07 |
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| CN208819880U (en) * | 2018-09-14 | 2019-05-03 | 长鑫存储技术有限公司 | Memory and semiconductor devices |
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| KR20120121795A (en) * | 2011-04-27 | 2012-11-06 | 에스케이하이닉스 주식회사 | Method for manufacturing of semiconductor device having spacer with air gap |
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