KR20110013033A - Method for manufacturing semiconductor device with buried gate - Google Patents

Abstract

PURPOSE: A semiconductor device manufacturing method is provided to obtain the margin of a plug process enough by minimizing the loss of the gap fill insulation layer on the top of the burying gate during strip process. CONSTITUTION: A trench(27) is formed on a semiconductor substrate(21) through the etching using the hard mask film of multilayer. A buried gate(29A) filling the trench is formed. A gap fill film(30B) having the protrusion projected on the upper part of the buried gate is formed. A spacer(32) is formed on the sidewall of the protrusion.

Description

Method for manufacturing semiconductor device with buried gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a buried gate.

As micronization progresses in the semiconductor process, various device characteristics and process implementations are becoming difficult. In particular, the formation of the gate structure, the bit line structure, and the contact structure is showing a limit as it goes down to 40 nm or less. For example, even if the structure is formed, it is possible to secure a resistance characteristic, a refresh (refresh) or a low fail that can satisfy the device characteristics. And breakdown voltage (BV) characteristics are present. Accordingly, recently, a buried gate process, in which a gate is buried in an active region, has been introduced to reduce parasitic capacitance, increase process margin, and minimize the formation of a smallest cell transistor.

1A to 1C illustrate a method of manufacturing a semiconductor device having a buried gate according to the related art.

As shown in FIG. 1A, the device isolation layer 12 is formed on the semiconductor substrate 11 through a shadow trench isolation (STI) process. The semiconductor substrate 11 includes a semiconductor substrate in a cell region, and the peripheral circuit region is not shown.

Subsequently, after the pad oxide film 13 is formed, the pad nitride film 14 is formed on the pad oxide film 13.

Subsequently, the pad nitride layer 14 is etched using a buried trench mask (not shown), and the pad oxide layer 13 and the semiconductor substrate 11 are continuously etched to a predetermined depth to form the trench 15 in which the buried gate is buried. do.

As shown in FIG. 1B, after the gate insulating layer 16 is formed through a gate oxidation process, a buried gate 17 partially filling the trench 15 is formed. The buried gate 17 is formed by proceeding in order of deposition of a metal film, a chemical mechanical polishing (CMP) process, and an etchback.

Subsequently, an upper portion of the buried gate 17 is gap filled using a gap fill insulating film. At this time, the gap fill insulating film is thinly sealed with the nitride film 18 and then gap filled using the oxide film 19. Thereafter, the planarization process is performed.

As shown in Fig. 1C, the pad nitride film is removed. At this time, the pad nitride film is stripped using phosphoric acid. Therefore, the gap fill insulating film of the nitride film 18A and the oxide film 19A remains on the buried gate 17.

The oxide film used as the gap fill insulating film in the above prior art should maintain its shape even after the strip of pad nitride film ('19' in FIG. 1C). This is because the oxide film acts as a polishing stop film in the subsequent plug process.

However, in the prior art, the loss of the oxide film, which is a gap fill insulating film, occurs when the pad nitride film is removed due to the influence of phosphoric acid used in the nitride film strip (19A in Fig. 1C). The loss of the oxide film occurs more severely when using SOD (Spin On Dielectric).

As such, when the oxide film is lost, the shape of the gap fill insulating film on the upper portion of the buried gate is not maintained, so that the margin of the subsequent plug process is insufficient. In particular, when sidewall loss of the oxide film occurs, the profile of the plug is poor, and a short between neighboring plugs occurs.

In order to overcome this problem, a chemical mechanical polishing (CMP) process must be performed to form a buried gate while compensating for the gap fill insulating film lost by depositing a very thick pad nitride film.

However, there is a problem that the margin of the trench etching process in which the buried gate is buried depends on the height of the pad nitride layer.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the problems according to the prior art, and has an object of the present invention to provide a method for manufacturing a semiconductor device which can sufficiently secure the margin of the plug process by minimizing the loss of the gap fill insulating film on the buried gate. .

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a trench in a semiconductor substrate through etching using a multi-layer hard mask film; Forming a buried gate to partially fill the trench; Forming a gap fill layer having a gap portion filling the upper portion of the buried gate and having protrusions protruding from both side walls and an upper surface thereof; Forming spacers on sidewalls of the protrusions; Removing the residual hardmask film under the spacer to expose the surface of the substrate; And forming a plug on the semiconductor substrate between the protrusions, wherein the multilayer hard mask film is stacked in the order of the first hard mask nitride film, the hard mask oxide film, and the second hard mask nitride film. Nitride Oxide Nitride) structure characterized in that it is formed. The spacer may include an oxide film, and the gap fill film may include a nitride film.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a device isolation film defining an active region on the semiconductor substrate; Forming a trench in the active region through etching using a multilayer hard mask layer; Forming a buried gate to partially fill the trench; Forming a gap fill layer for gap filling an upper portion of the buried gate; Planarizing the gap fill layer to expose the hard mask layer; Protruding both sidewalls and the top surface of the gap fill layer through etching using a mask to open the active region; Forming spacers on both protruding side walls of the gap fill layer; Exposing a surface of the semiconductor substrate by removing a residual hard mask layer under the spacer; And forming a plug on the semiconductor substrate between the protrusions.

According to the present invention, since the nitride film is used as a gap fill insulating film for gapfilling the buried gate and a spacer is formed on the sidewall thereof, the loss of the gap fill insulating film can be minimized during the subsequent stripping process due to phosphoric acid.

In addition, the present invention has the effect of maintaining the profile of the plug intact by removing the hard mask oxide film and the pad oxide film to form an oxide well (well), and by forming a plug embedded in the oxide well.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2A to 2L are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

As shown in FIG. 2A, the device isolation layer 22 is formed on the semiconductor substrate 21 through a shadow trench isolation (STI) process. Here, the semiconductor substrate 21 may include a silicon substrate, and the cell region and the peripheral circuit region may be divided. The device isolation layer 22 may include an oxide layer, such as a high density plasma oxide layer (HDP oxide) or a spin on dielectric layer (Spin On Dielectric). Although not shown, an active region is defined in the semiconductor substrate 21 by the device isolation film 22.

Subsequently, after the pad oxide film 23 is formed, a hard mask film is formed on the pad oxide film 23. Here, the hard mask film includes a multilayer structure, and includes a stacked structure of a first hard mask film, a second hard mask film, and a third hard mask film. Preferably, the multi-layered hard mask layer may have a NON (Nitride Oxide Nitride) structure stacked in the order of the first hard mask nitride layer 24, the hard mask oxide layer 25, and the second hard mask nitride layer 26. The hard mask oxide film 25 includes a high density plasma oxide film (HDP oxide), BPSG, SOD and the like. In particular, the high density plasma oxide film is a very hard material having a greater hardness than other oxide films. The first and second hard mask nitride films 24 and 26 are formed in a furnace or by using chemical vapor deposition (CVD). The nitride film formed in the furnace is called a thermal nitride film, and the nitride film formed by chemical vapor deposition is called a CVD nitride film. The first and second hard mask nitride layers 24 and 26 may include silicon nitride layers.

The hard mask oxide layer 25 may be thicker than the first and second hard mask nitride layers 24 and 26.

In the multilayered hard mask film, the second hard mask nitride film 26 serves as a hard mask in a subsequent process, the hard mask oxide film 25 serves as a polishing stop film in a plug separation process, and the first hard mask nitride film ( 24) serves as an etch stop during the subsequent etching process.

Subsequently, a multi-layer hard mask film is etched using a buried trench mask (not shown), and the pad oxide film 23 and the semiconductor substrate 21 are subsequently etched to a predetermined depth to form a trench 27 in which the buried gate is buried. . At this time, the trench 27 is in the form of a line.

As described above, in the etching process of the semiconductor substrate 21 for forming the trench 27 in which the buried gate is buried, the second hard mask nitride layer 26 serving as an etching barrier serves as an etching barrier.

As shown in FIG. 2B, the gate insulating layer 28 is formed through a gate oxidation process. In this case, the gate insulating film 28 may include a silicon oxide film.

Next, the metal film 29 is deposited on the entire surface until the trench 27 is gapfilled. The metal layer 29 is a material used as a buried gate, and may include at least one selected from the group consisting of a tantalum nitride layer (TaN), a titanium nitride layer (TiN), and a tungsten layer (W). For example, the metal film 29 may be formed of a two-layer structure such as TiN / W or TaN / W, which uses TiN or TaN alone, or a tungsten film is laminated on a titanium nitride film and a tantalum nitride film.

Subsequently, a chemical mechanical polishing (CMP) process is performed. At this time, in the CMP process, the polishing is stopped in the second hard mask nitride film 26. As a result, the metal film 29 remains only in the trench 27, and the metal film is removed from the surface of the second hard mask nitride film 26.

As shown in FIG. 2C, a recess process is performed. At this time, the recess process uses an etch back process, which forms a buried gate 29A for filling a portion of the trench 27 by recessing the metal film to a predetermined depth.

The buried gate 29A described above has a structure in which the inside of the trench 27 is partially buried on the gate insulating film 28.

As shown in FIG. 2D, an upper portion of the buried gate 29A is gap filled using the gap fill insulating film 30. At this time, the gap fill insulating film 30 uses a nitride film. In order to sufficiently fill the top of the buried gate 29A, the processes of deposition, stripping and deposition may be repeated.

As shown in FIG. 2E, the gap fill insulating layer 30 is selectively separated through the CMP process. That is, the gap fill insulating film 30 is polished so as to be polished to the second hard mask nitride film 26 in the multilayer hard mask film. At this time, the CMP process is stopped in the hard mask oxide film 25.

As such, the slurry used to stop polishing in the hard mask oxide film 25 uses a slurry having a polishing selectivity of 10: 1 or more between the nitride film and the oxide film. Accordingly, only the second hard mask nitride film 26 and the gap fill insulating film 30 can be selectively polished.

By the above-described CMP process, the gap fill insulating film 30A remains only on the buried gate 29A.

As shown in FIG. 2F, a mask 31 for etching the hard mask oxide layer 25 in the cell region is formed. In this case, the mask 31 is formed in such a manner as to cover the upper portion of the device isolation film 22 by using a negative photosensitive film and open the remaining regions (active regions) except the device isolation film 22.

Subsequently, the hard mask oxide film 25 is etched using the mask 31. At this time, the etching of the hard mask oxide film 25 is stopped in the first hard mask nitride film 24. As described above, when the hard mask oxide film 25 is etched, the protrusion (reference numeral 'B') of the gap fill insulating film 30A is exposed.

As shown in FIG. 2G, the spacer 32 is formed on the sidewall of the protrusion of the gap fill insulating film 30A after the mask is removed. At this time, the spacer 32 is formed through dry cleaning (Dry CLN) after depositing a liner oxide film using a thermal oxide (Thermal oxide) such as TEOS on the front. Dry cleaning uses a non plasma type method, for example, using HF gas or NH ₃ gas. On the other hand, the dry cleaning of the plasma type is a cleaning method using a gas for dry etching the oxide film. When the dry cleaning of the plasma type is applied, the first hard mask nitride film 24 and the gap fill insulating film 30A may be lost. Therefore, dry cleaning is performed using a non-plasma type method.

As such, when the spacers 32 are formed through dry cleaning, the loss of the gap fill insulating layer 30A may be minimized.

The spacer 32 prevents the sidewall of the gap fill insulating film 30A from being lost when stripping the subsequent first hard mask nitride film 24. In particular, since the spacer 32 is a thermal oxide film such as TEOS, the spacer 32 has a selectivity to phosphoric acid and is not lost. On the other hand, the spin-on insulating film conventionally used as the gap fill insulating film has a problem that it is quickly lost by phosphoric acid because the film quality is not as dense as that of TEOS.

As shown in FIG. 2H, wet cleaning, that is, nitride strip 101 is performed to remove the first hard mask nitride layer. The nitride film strip 101 process uses phosphoric acid, and the upper portion of the gap fill insulating film may be partially lost during the nitride film strip process. As a result, the gap-fill insulating film 30B whose height is lowered remains.

Since the spacers 32 are formed on the sidewalls of the gap fill insulating film 30B during the nitride film strip 101 process, the sidewall loss of the gap fill insulating film 30B is suppressed.

As shown in FIG. 2I, the pad oxide film 23 is removed by dry cleaning to expose the surface of the semiconductor substrate 21. At this time, the dry cleaning is applied to the non-plasma type (Non plasma type) method, for example, proceeds using HF gas or NH ₃ gas.

As described above, when the pad oxide layer 23 and the first hard mask nitride layer 24 on the semiconductor substrate 21 are removed, dry cleaning or wet cleaning, not dry etching, is performed. Wet cleaning. Accordingly, the loss of the gap fill insulating film 30B can be minimized.

If the pad oxide film 23 is removed, oxide wells 102 are formed between the gap fill film 30B. Thus, when the oxide well 102 is formed, the profile of the subsequent plug can be maintained intact.

As shown in FIG. 2J, after the plug conductive film is deposited without a time delay, the plug separation process is performed. The plug conductive film includes a polysilicon film, and the plug separation process uses a CMP process. In the CMP process, a slurry having a polishing selectivity of 10: 1 or more is used between the polysilicon film and the oxide film.

A landing plug 33 embedded in the oxide well is formed through the plug separation process as described above.

As shown in FIG. 2K, after the sealing film is deposited, the peripheral circuit region open mask 36 may be processed. The sealing film is formed by stacking the sealing nitride film 34 and the sealing oxide film 35.

Subsequently, the sealing oxide film, the sealing nitride film and the gap fill insulating film in the peripheral circuit area are removed using the peripheral circuit area open mask 36. When the gap fill insulating layer is removed, the etching is stopped in the lower first hard mask nitride layer 24.

As shown in FIG. 2L, after the peripheral circuit region open mask 36 is stripped, the first hard mask nitride film of the peripheral circuit region is removed. The first hard mask nitride layer is removed by wet cleaning, and the first hard mask nitride layer 24 remains in the cell region.

Upon removal of the first hard mask nitride film, the cell region is protected by the sealing oxide film.

As described above, when the first hard mask nitride film is removed, the sealing nitride film 34 and the sealing oxide film 35 remain on the cell region while the buried gate 29A and the landing plug 33 are formed in the cell region. Only the pad oxide film 23 remains.

Although not shown, a process of forming a transistor in the peripheral circuit region is then performed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A to 1C illustrate a method of manufacturing a semiconductor device having a buried gate according to the prior art.

2A to 2L are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23 pad oxide film 24 first hard mask nitride film

25: hard mask oxide film 26: second hard mask nitride film

27 trench 28 gate insulating film

29A: buried gate 30A, 30B: gap fill insulating film

32: spacer

Claims (14)

Forming a trench in the semiconductor substrate through etching using a multilayer hard mask film; Forming a buried gate to partially fill the trench; Forming a gap fill layer having a gap portion filling the upper portion of the buried gate and having protrusions protruding from both side walls and an upper surface thereof; Forming spacers on sidewalls of the protrusions; Removing the residual hardmask film under the spacer to expose the surface of the substrate; And Forming a plug on the semiconductor substrate between the protrusions A semiconductor device manufacturing method comprising a. The method of claim 1, The multilayer hard mask film is A method of manufacturing a semiconductor device in which a first hard mask nitride film, a hard mask oxide film, and a second hard mask nitride film are stacked in this order to form a nitride oxide nitride (NON) structure. The method of claim 2, Forming a gap fill film having the protrusion, Forming an insulating film to be used as the gap fill layer on the entire surface to gap fill the upper portion of the buried gate Planarizing the insulating film to expose a hard mask oxide film among the multilayer hard mask films; And Removing the hard mask oxide layer to protrude the top surface and both side walls of the planarized insulating layer A semiconductor device manufacturing method comprising a. The method of claim 1, Forming the spacers, Depositing an insulating film on the entire surface including the protrusion; And Dry cleaning the insulating film to form the spacer in contact with the sidewall of the protrusion; A semiconductor device manufacturing method comprising a. The method of claim 4, wherein The dry cleaning is a semiconductor device manufacturing method using a non-plasma type (non-plasma type) gas. The method of claim 5, The non-plasma type gas is a semiconductor device manufacturing method using HF gas or NH ₃ gas. The method according to any one of claims 1 to 6 The spacer includes an oxide film, and the gap fill film comprises a nitride film. Forming an isolation layer defining an active region on the semiconductor substrate; Forming a trench in the active region through etching using a multilayer hard mask layer; Forming a buried gate to partially fill the trench; Forming a gap fill layer for gap filling an upper portion of the buried gate; Planarizing the gap fill layer to expose the hard mask layer; Protruding both sidewalls and the top surface of the gap fill layer through etching using a mask to open the active region; Forming spacers on both protruding side walls of the gap fill layer; Exposing a surface of the semiconductor substrate by removing a residual hard mask layer under the spacer; And Forming a plug on the semiconductor substrate between the protrusions A semiconductor device manufacturing method comprising a. The method of claim 8, And a mask for opening the active region by using a negative photosensitive film. The method of claim 8, The multilayer hard mask film is A method of manufacturing a semiconductor device in which a first hard mask nitride film, a hard mask oxide film, and a second hard mask nitride film are stacked in this order to form a nitride oxide nitride (NON) structure. The method of claim 8, Forming the spacers, Depositing an insulating film on the entire surface including the protrusion; And Dry cleaning the insulating film to form the spacer in contact with the sidewall of the protrusion; A semiconductor device manufacturing method comprising a. The method of claim 11, The dry cleaning is a semiconductor device manufacturing method using a non-plasma type (non-plasma type) gas. The method of claim 12, The non-plasma type gas is a semiconductor device manufacturing method using HF gas or NH ₃ gas. The method according to any one of claims 8 to 13 The spacer includes an oxide film, and the gap fill film comprises a nitride film.

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