KR20080089069A - Gate of semiconductor device and method for fabricating the same - Google Patents

Gate of semiconductor device and method for fabricating the same Download PDF

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KR20080089069A
KR20080089069A KR1020070032054A KR20070032054A KR20080089069A KR 20080089069 A KR20080089069 A KR 20080089069A KR 1020070032054 A KR1020070032054 A KR 1020070032054A KR 20070032054 A KR20070032054 A KR 20070032054A KR 20080089069 A KR20080089069 A KR 20080089069A
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film
layer
gate
conductive
opening
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김정수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A gate of a semiconductor device and a method for manufacturing the same are provided to obtain a more vertical gate profile by forming a lower layer of a gate after an upper layer of the gate is formed through a damascene method. A first conductive layer is formed. A dielectric having an opening is formed on the first conductive layer. A protective layer(29B) is formed on the dielectric along the opening. A second conductive layer(30B) is formed on the protective layer to gap-fill the opening. The second conductive layer and the protective layer are etched to gap-fill a lower region of the opening. A hard mask layer is formed to gap-fill the remaining region of the opening. The dielectric is removed. A part of the first conductive layer is etched by using the hard mask layer as an etch barrier. A capping layer(32) is formed on the whole surface including the first conductive layer whose part is etched. The capping layer and the remaining of the first conductive layer are etched.

Description

반도체소자의 게이트 및 그 제조 방법{GATE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}GATE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

도 1은 종래기술에 따른 텅스텐게이트 공정시 발생하는 네가티브슬로프현상을 나타낸 사진.1 is a photograph showing a negative slope phenomenon occurring during the tungsten gate process according to the prior art.

도 2는 본 발명의 실시예에 따른 반도체소자의 게이트 구조를 도시한 도면.2 illustrates a gate structure of a semiconductor device in accordance with an embodiment of the present invention.

도 3a 내지 도 3i는 본 발명의 실시예에 따른 게이트 제조 방법을 도시한 공정 단면도.3A to 3I are cross-sectional views illustrating a method of manufacturing a gate in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 실리콘기판 22 : 소자분리막21 silicon substrate 22 device isolation film

23 : 게이트절연막 24B: 폴리실리콘막패턴23: gate insulating film 24B: polysilicon film pattern

25 : 희생막 26 : 하드마스크막25: sacrificial film 26: hard mask film

29B : 텅스텐실리사이드막 30B : 텅스텐막29B: tungsten silicide film 30B: tungsten film

31 : 게이트하드마스크막 32 : 캡핑막31: gate hard mask film 32: capping film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 반도체소자의 게이트 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate of a semiconductor device.

폴리실리콘과 텅스텐실리사이드의 적층을 이용한 게이트 형성 공정은 텅스텐실리사이드 식각 및 이후 폴리실리콘 식각 과정에서 네가티브슬로프(Negative Slope) 현상이 발생하지는 않는다. 그러나, 소자의 고집적화가 진행되면서 게이트의 선폭이 감소하면서 저항이 증가하고 이에 따라 데이터 전달 속도가 감소하여 시간지연(Time Delay)을 유발하여 제품 특성에 영향을 주고 있다.In the gate forming process using a stack of polysilicon and tungsten silicide, a negative slope phenomenon does not occur during tungsten silicide etching and subsequent polysilicon etching. However, as the integration of devices increases, the line width of the gate decreases, the resistance increases, and accordingly, the data transfer rate decreases, causing a time delay to affect product characteristics.

이에 최근에는 폴리실리콘과 텅스텐의 적층구조(이하 '텅스텐게이트'라 약칭함)를 이용하여 저항을 개선하는 방향으로 기술개발이 이루어지고 있다. 그러나, 텅스텐 게이트 공정에서는 텅스텐 식각 및 폴리실리콘 식각시 텅스텐실리사이드와는 다르게 텅스텐의 유연한 물성때문에 네가티브슬로프 현상(식각단면이 네가티브로 기울어지는 현상)이 발생하여 텅스텐의 선폭이 감소하는 현상이 발생하고 있다. Recently, technology development has been made to improve resistance by using a laminated structure of polysilicon and tungsten (hereinafter abbreviated as 'tungsten gate'). However, in the tungsten gate process, unlike tungsten silicide in tungsten etching and polysilicon etching, a negative slope phenomenon (a negative slope of the etching section) occurs due to the flexible physical properties of tungsten, thereby reducing the tungsten line width. .

도 1은 종래기술에 따른 텅스텐게이트 공정시 발생하는 네가티브슬로프현상을 나타낸 사진이다.1 is a photograph showing a negative slope phenomenon occurring during the tungsten gate process according to the prior art.

도 1의 네가티브슬로프(도면부호 'N Slope') 현상은 텅스텐막이 과도하게 식각됨에 따라 발생되며, 텅스텐게이트의 저항 감소의 걸림돌이 되고 있다. The negative slope (N 'slope') phenomenon of FIG. 1 occurs as the tungsten film is excessively etched, which is an obstacle in reducing the resistance of the tungsten gate.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 텅 스텐게이트 공정시 네가티브슬로프 현상이 발생하는 것을 방지하여 저항을 감소시킬 수 있는 반도체소자의 게이트 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, to provide a gate and a method of manufacturing a semiconductor device that can reduce the resistance by preventing the negative slope phenomenon occurs during the tungsten gate process. There is this.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 게이트 제조 방법은 제1도전막을 형성하는 단계; 상기 제1도전막 상에 오프닝을 갖는 절연막을 형성하는 단계; 상기 오프닝을 따라 절연막 상에 보호막을 형성하는 단계; 상기 보호막 상에 상기 오프닝을 채우는 제2도전막을 형성하는 단계; 상기 오프닝의 하부 영역을 채우도록 상기 제2도전막과 보호막을 식각하는 단계; 상기 오프닝의 나머지영역을 채우는 하드마스크막을 형성하는 단계; 상기 절연막을 제거하는 단계; 상기 하드마스크막을 식각장벽으로 하여 상기 제1도전막을 일부 식각하는 단계; 상기 일부 식각된 제1도전막을 포함한 전면에 캡핑막을 형성하는 단계; 및 상기 캡핑막과 상기 제1도전막의 나머지를 식각하는 단계를 포함하는 것을 특징으로 한다.Method of manufacturing a gate of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a first conductive film; Forming an insulating film having an opening on the first conductive film; Forming a protective film on the insulating film along the opening; Forming a second conductive film filling the opening on the protective film; Etching the second conductive layer and the passivation layer to fill the lower region of the opening; Forming a hard mask film filling the remaining area of the opening; Removing the insulating film; Etching the first conductive layer partially by using the hard mask layer as an etch barrier; Forming a capping layer on the entire surface including the partially etched first conductive layer; And etching the remainder of the capping layer and the first conductive layer.

또한, 본 발명의 반도체소자의 게이트는 제1도전막; 상기 제1도전막 상의 금속실리사이드막; 상기 금속실리사이드막 상의 제2도전막; 상기 제2도전막 상의 게이트하드마스크막; 및 상기 제1도전막의 상부 측벽과 상기 게이트하드마스크막 및 금속실리사이드막의 측벽을 덮는 캡핑막을 포함하는 것을 특징으로 하며, 상기 금속실리사이드막은 상기 제2도전막의 바닥 및 양측벽을 덮는 형태인 것을 특징으로 한다.In addition, the gate of the semiconductor device of the present invention is a first conductive film; A metal silicide film on the first conductive film; A second conductive film on the metal silicide film; A gate hard mask layer on the second conductive layer; And a capping layer covering an upper sidewall of the first conductive layer and a sidewall of the gate hard mask layer and the metal silicide layer, wherein the metal silicide layer is formed to cover the bottom and both sidewalls of the second conductive layer. do.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2는 본 발명의 실시예에 따른 반도체소자의 게이트 구조를 도시한 도면이다.2 illustrates a gate structure of a semiconductor device in accordance with an embodiment of the present invention.

도 2를 참조하면, 실리콘기판(21)에 소자분리막(22)이 형성되고, 실리콘기판(21)의 선택된 표면 상에 게이트절연막(23)이 형성된다.Referring to FIG. 2, a device isolation film 22 is formed on a silicon substrate 21, and a gate insulating film 23 is formed on a selected surface of the silicon substrate 21.

그리고, 게이트절연막(23) 위에 폴리실리콘막패턴(24B), 텅스텐실리사이드막(29B), 텅스텐막(30B) 및 게이트하드마스크막(31)이 적층되고, 폴리실리콘막패턴(24B)의 상부와 텅스텐실리사이드막(29B) 및 게이트하드마스크막(31)의 측벽에 캡핑막(32)이 형성된다. 여기서, 텅스텐실리사이드막(29B)은 텅스텐막(30B)의 바닥 및 양측벽을 덮는 형태를 가지면서 폴리실리콘막 패턴(24B) 상에 형성된다. 그리고, 폴리실리콘막패턴(24B)의 하부는 측면이 외부에 노출되고, 상부는 캡핑막(32)에 의해 덮이는 구조가 된다.Then, the polysilicon film pattern 24B, the tungsten silicide film 29B, the tungsten film 30B, and the gate hard mask film 31 are stacked on the gate insulating film 23, and the upper portion of the polysilicon film pattern 24B is formed. The capping film 32 is formed on the sidewalls of the tungsten silicide film 29B and the gate hard mask film 31. Here, the tungsten silicide film 29B is formed on the polysilicon film pattern 24B while having a form covering the bottom and both side walls of the tungsten film 30B. The lower side of the polysilicon layer pattern 24B is exposed to the outside, and the upper side thereof is covered by the capping layer 32.

바람직하게, 게이트하드마스크막(31) 및 캡핑막(32)은 질화막이다. 그리고, 폴리실리콘막패턴(24B) 위에 잔류하는 텅스텐막(30B)과 텅스텐실리사이드막(29B)의 높이는 800∼1000Å이다. 그리고, 텅스텐실리사이드막(29)의 두께는 50Å 이하(5∼50Å)의 두께이다.Preferably, the gate hard mask film 31 and the capping film 32 are nitride films. Then, the heights of the tungsten film 30B and the tungsten silicide film 29B remaining on the polysilicon film pattern 24B are 800 to 1000 mW. The tungsten silicide film 29 has a thickness of 50 kPa or less (5-50 kPa).

전술한 바와 같이, 텅스텐막(30B)과 폴리실리콘막패턴(24B)을 포함하는 텅스텐 게이트 구조가 되며, 전체적인 게이트의 프로파일이 수직 프로파일을 갖는다.As described above, the tungsten gate structure includes the tungsten film 30B and the polysilicon film pattern 24B, and the overall gate profile has a vertical profile.

후술하겠지만, 도 2의 게이트 구조는 상감기법을 이용하여 형성하며, 이러한 상감기법에 의해 텅스텐막의 네가티브슬로프를 방지하여 수직한 프로파일을 얻을 수 있다. 특히, 텅스텐실리사이드막(29B)은 후속 폴리실리콘막 식각시 텅스텐막(30B)의 측벽을 보호하는 보호막 역할을 한다.As will be described later, the gate structure of FIG. 2 is formed using the damascene method, and by this damascene method, a negative slope of the tungsten film can be prevented to obtain a vertical profile. In particular, the tungsten silicide layer 29B serves as a protective layer to protect the sidewall of the tungsten layer 30B during subsequent polysilicon layer etching.

도 3a 내지 도 3i는 본 발명의 실시예에 따른 반도체소자의 게이트 제조 방법을 도시한 공정 단면도이다.3A to 3I are cross-sectional views illustrating a method of manufacturing a gate of a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 실리콘기판(21)에 소자분리막(22)을 형성하여 트랜지스터가 동작할 부분, 즉 활성영역을 형성한다. 이때, 소자분리막(22)은 STI(Shallow Trench Isolation) 공정을 이용하여 형성한다.As shown in FIG. 3A, the device isolation layer 22 is formed on the silicon substrate 21 to form a portion in which the transistor operates, that is, an active region. In this case, the device isolation layer 22 is formed using a shallow trench isolation (STI) process.

이어서, 게이트전극과 실리콘기판간 절연을 위한 게이트절연막(23)을 형성한다. 이때, 게이트절연막(23)은 산화(Oxidation) 공정을 통해 형성한 실리콘산화막이다.Subsequently, a gate insulating film 23 for insulating between the gate electrode and the silicon substrate is formed. In this case, the gate insulating film 23 is a silicon oxide film formed through an oxidation process.

이어서, 게이트절연막(23) 상에 폴리실리콘막(24)을 증착한 후 게이트패터닝을 위한 희생막(25)과 식각시 배리어역할을 하는 하드마스크막(26)을 증착한다. 이때, 희생막(25)은 산화막(Oxide)이며, 또한, 희생막(25) 위에 형성되는 하드마스크막(26)은 절연체 및 식각배리어 역할을 동시에 구현하기 위해 불순물이 도핑되지 않은 폴리실리콘막(Undoped polysilicon)을 사용한다. 바람직하게, 희생막(25)과 하드마스크막(26)으로 이루어진 절연막 구조는 후속 텅스텐막의 높이와 게이트보호구조인 게이트하드마스크막의 높이를 고려하여 2500Å∼3000Å 두께로 형성한다. Subsequently, a polysilicon layer 24 is deposited on the gate insulating layer 23, and then a hard mask layer 26 serving as a barrier during etching with the sacrificial layer 25 for gate patterning is deposited. In this case, the sacrificial layer 25 is an oxide, and the hard mask layer 26 formed on the sacrificial layer 25 is a polysilicon layer that is not doped with impurities in order to simultaneously serve as an insulator and an etching barrier. Undoped polysilicon) is used. Preferably, the insulating film structure composed of the sacrificial film 25 and the hard mask film 26 is formed to have a thickness of 2500 kV to 3000 kPa in consideration of the height of the subsequent tungsten film and the height of the gate hard mask film, which is a gate protection structure.

도 3b에 도시된 바와 같이, 게이트가 형성될 부분의 공간(Space) 확보를 위 해 포토레지스트패턴(27)을 형성한다.As shown in FIG. 3B, a photoresist pattern 27 is formed to secure a space of a portion where the gate is to be formed.

이어서, 포토레지스트패턴(27)을 식각장벽으로 하여 하드마스크막(26)과 희생막(25)을 식각한다. 이로써, 폴리실리콘막(24)의 표면을 오픈시키는 오프닝(28)이 형성된다. 이때, 오프닝(28)은 게이트가 형성될 공간으로서 라인(Line) 패턴이다.Subsequently, the hard mask layer 26 and the sacrificial layer 25 are etched using the photoresist pattern 27 as an etch barrier. Thereby, the opening 28 which opens the surface of the polysilicon film 24 is formed. In this case, the opening 28 is a line pattern where the gate is to be formed.

도 3c에 도시된 바와 같이, 포토레지스트패턴(27)을 제거한 후, 전면에 텅스텐실리사이드막(29)을 증착한다. 이때, 텅스텐실리사이드막(29)은 후속 폴리실리콘막의 1,2차 식각시 텅스텐막의 측벽이 식각되는 것을 방지하는 보호막 역할만 하도록 그 두께를 최소화 한다. 바람직하게, 텅스텐실리사이드막(29)은 50Å 이하(5∼50Å)의 두께로 증착한다.As shown in FIG. 3C, after removing the photoresist pattern 27, a tungsten silicide layer 29 is deposited on the entire surface. In this case, the tungsten silicide layer 29 minimizes the thickness of the tungsten silicide layer 29 to serve only as a protective layer to prevent sidewalls of the tungsten layer from being etched during the first and second etchings of the polysilicon layer. Preferably, the tungsten silicide film 29 is deposited to a thickness of 50 kPa or less (5 to 50 kPa).

이어서, 텅스텐실리사이드막(29) 상에 오프닝(28)을 채우도록 텅스텐막(30)을 증착한다.Next, a tungsten film 30 is deposited on the tungsten silicide film 29 to fill the opening 28.

도 3d에 도시된 바와 같이, 에치백(Etchback) 공정을 진행한다. 이때, 에치백공정은 텅스텐막(30)과 텅스텐실리사이드막(29)을 동시에 에치백하며, 이를 통해 오프닝(28)의 내부에만 텅스텐막(30A)과 텅스텐실리사이드막(29A)을 잔류시켜 이웃한 게이트간에 절연상태가 유지되도록 한다.As shown in FIG. 3D, an etchback process is performed. At this time, the etch back process etches back the tungsten film 30 and the tungsten silicide film 29 at the same time, thereby remaining the tungsten film 30A and the tungsten silicide film 29A only in the opening 28. Ensure insulation between gates.

이와 같은 에치백공정시 하드마스크막(26)이 식각정지막(Etch stopper) 역할을 한다.During the etch back process, the hard mask layer 26 serves as an etch stopper.

도 3e에 도시된 바와 같이, 습식식각, 바람직하게는 습식딥식각(Wet Dip Etch)을 진행하여 추가로 텅스텐막(30A)과 텅스텐실리사이드막(29A)을 식각한다. 이때, 폴리실리콘막(24) 위에 잔류하는 텅스텐막(30B)과 텅스텐실리사이드막(29B)의 높이는 800∼1000Å을 유지하도록 한다. 이로써 텅스텐막(30B)과 텅스텐실리사이드막(29B)이 오프닝(28)의 하부(Bottom) 영역을 채우는 형태가 된다.As shown in FIG. 3E, a wet etching, preferably wet dip etching, is further performed to etch the tungsten film 30A and the tungsten silicide film 29A. At this time, the heights of the tungsten film 30B and the tungsten silicide film 29B remaining on the polysilicon film 24 are maintained at 800 to 1000 mW. As a result, the tungsten film 30B and the tungsten silicide film 29B fill the bottom region of the opening 28.

도 3f에 도시된 바와 같이, 폴리실리콘막(24), 텅스텐실리사이드막(29B) 및 텅스텐막(30B)을 보호하기 위해 게이트하드마스크막(31)을 증착한다. 이때, 게이트하드마스크막(31)은 질화막이다.As shown in FIG. 3F, a gate hard mask film 31 is deposited to protect the polysilicon film 24, the tungsten silicide film 29B, and the tungsten film 30B. At this time, the gate hard mask film 31 is a nitride film.

이어서, 게이트하드마스크막(31)을 에치백하여 이웃한 게이트간의 분리를 실시한다. 이때, 텅스텐막 위의 게이트하드마스크막(31)은 희생막(25)의 두께에 따라 1500∼2000Å을 유지하게 된다. 그리고, 게이트하드마스크막(31)의 에치백시 하드마스크막(26)이 식각정지막 역할을 한다.Subsequently, the gate hard mask film 31 is etched back to separate the adjacent gates. At this time, the gate hard mask film 31 on the tungsten film is maintained at 1500 to 2000 GPa according to the thickness of the sacrificial film 25. The hard mask layer 26 at the time of etch back of the gate hard mask layer 31 serves as an etch stop layer.

이로써, 게이트하드마스크막(31)이 오프닝의 나머지 영역을 채운다.As a result, the gate hard mask film 31 fills the remaining area of the opening.

도 3g에 도시된 바와 같이, 희생막(25)을 제거한다. As shown in FIG. 3G, the sacrificial layer 25 is removed.

바람직하게, 희생막(25) 제거 공정은 습식딥아웃(Dip Out) 공정을 이용하며, 예를 들어 희생막(25)이 산화막이므로 HF 또는 BOE 용액을 이용한다. 이러한 습식딥아웃 공정시 하드마스크막(26)이 동시에 떨어져 나가 제거된다.Preferably, the sacrificial film 25 removal process uses a wet dip out process. For example, since the sacrificial film 25 is an oxide film, an HF or BOE solution is used. During the wet deep out process, the hard mask layer 26 is simultaneously removed and removed.

도 3h에 도시된 바와 같이, 게이트하드마스크막(31)을 식각장벽으로 하여 폴리실리콘막(24)을 1차로 일부 식각한다. 이로써, 요철형 폴리실리콘막패턴(24A)이 형성된다. 이러한 1차 식각시 텅스텐실리사이드막(29B)이 텅스텐막(30B)이 식각되는 것을 방지한다.As shown in FIG. 3H, the polysilicon film 24 is partially etched primarily using the gate hard mask film 31 as an etching barrier. As a result, the uneven polysilicon film pattern 24A is formed. During the first etching, the tungsten silicide layer 29B prevents the tungsten layer 30B from being etched.

도 3i에 도시된 바와 같이, 폴리실리콘막패턴(24A) 보호 및 텅스텐실리사이 드막(29B) 보호를 위한 캡핑막(32)을 증착한다. 이때, 캡핑막(32)은 질화막이다.As shown in FIG. 3I, a capping film 32 is deposited to protect the polysilicon film pattern 24A and the tungsten silicon film 29B. At this time, the capping film 32 is a nitride film.

이어서, 에치백을 통해 캡핑막(32)을 선택적으로 식각한 후, 남아있는 폴리실리콘막패턴(24A)을 2차 식각하고, 연속해서 게이트절연막(23)을 식각하여 텅스텐게이트 구조를 완성한다. 이때, 폴리실리콘막패턴(24A)의 2차 식각시 텅스텐막(30B)의 측벽에는 텅스텐실리사이드막(29B) 및 캡핑막(32)이 존재하므로, 텅스텐막(30B)의 과도 식각이 발생되는 것을 방지한다.Subsequently, after the capping layer 32 is selectively etched through the etch back, the remaining polysilicon layer pattern 24A is secondarily etched, and the gate insulation layer 23 is subsequently etched to complete the tungsten gate structure. At this time, since the tungsten silicide film 29B and the capping film 32 exist on the sidewalls of the tungsten film 30B during the secondary etching of the polysilicon film pattern 24A, the excessive etching of the tungsten film 30B occurs. prevent.

최종 게이트 구조를 살펴보면, 게이트절연막(23) 위에 폴리실리콘막패턴(24B), 텅스텐실리사이드막(29B), 텅스텐막(30B) 및 게이트하드마스크막(31)이 적층되고, 폴리실리콘막패턴(24B)의 상부와 텅스텐실리사이드막(29B) 및 게이트하드마스크막(31)의 측벽에 캡핑막(32)이 형성된다. 여기서, 텅스텐실리사이드막(29B)은 텅스텐막(30B)의 바닥 및 양측벽을 덮는 형태를 가지면서 폴리실리콘막 패턴(24B) 상에 형성된다. 그리고, 폴리실리콘막패턴(24B)의 하부는 측면이 외부에 노출되고, 상부는 캡핑막(32)에 의해 덮이는 구조가 된다. 그리고, 폴리실리콘막패턴(24B) 위에 잔류하는 텅스텐막(30B)과 텅스텐실리사이드막(29B)의 높이는 800∼1000Å이다.Looking at the final gate structure, a polysilicon film pattern 24B, a tungsten silicide film 29B, a tungsten film 30B, and a gate hard mask film 31 are stacked on the gate insulating film 23, and the polysilicon film pattern 24B is stacked. The capping film 32 is formed on the upper side of the () and on the sidewalls of the tungsten silicide film 29B and the gate hard mask film 31. Here, the tungsten silicide film 29B is formed on the polysilicon film pattern 24B while having a form covering the bottom and both side walls of the tungsten film 30B. The lower side of the polysilicon layer pattern 24B is exposed to the outside, and the upper side thereof is covered by the capping layer 32. Then, the heights of the tungsten film 30B and the tungsten silicide film 29B remaining on the polysilicon film pattern 24B are 800 to 1000 mW.

전술한 바에 따르면, 본 발명은 상감(Damascene) 기법을 이용하여 오프닝을 형성한 후, 이 오프닝 내부에 텅스텐실리사이드막(29B), 텅스텐막(30B) 및 게이트하드마스크막(32)을 채우므로써, 수직(Vertical) 프로파일의 게이트 구조를 형성할 수 있다. 이와 같이, 텅스텐막(30B)이 수직한 프로파일을 가지므로 저항 개선의 효 과가 있다.According to the above, the present invention forms an opening by using a damascene technique, and then fills the tungsten silicide film 29B, the tungsten film 30B, and the gate hard mask film 32 inside the opening. A gate structure of a vertical profile can be formed. As such, since the tungsten film 30B has a vertical profile, there is an effect of improving the resistance.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 게이트의 저항을 개선할 수 있고, 저항 개선을 통해 트랜지스터의 안정적인 특성을 확보 할 수 있는 효과가 있다.The present invention described above can improve the resistance of the gate, it is possible to secure the stable characteristics of the transistor through the improved resistance.

또한, 본 발명은 게이트의 상층부를 상감기법(Damascene)에 의해 형성한 후 하층부 형성을 진행하므로써 기존 게이트 형성 방법보다 수직(Vertical)한 게이트프로파일을 얻을 수 있는 효과가 있다.In addition, the present invention has the effect of obtaining a vertical gate profile than the conventional gate forming method by forming the upper layer portion of the gate by a damascene method and then forming the lower layer portion.

Claims (16)

제1도전막을 형성하는 단계;Forming a first conductive film; 상기 제1도전막 상에 오프닝을 갖는 절연막을 형성하는 단계;Forming an insulating film having an opening on the first conductive film; 상기 오프닝을 따라 절연막 상에 보호막을 형성하는 단계;Forming a protective film on the insulating film along the opening; 상기 보호막 상에 상기 오프닝을 채우는 제2도전막을 형성하는 단계;Forming a second conductive film filling the opening on the protective film; 상기 오프닝의 하부영역을 채우도록 상기 제2도전막과 보호막을 식각하는 단계;Etching the second conductive layer and the passivation layer to fill the lower region of the opening; 상기 오프닝의 나머지 영역을 채우는 하드마스크막을 형성하는 단계;Forming a hard mask film filling the remaining area of the opening; 상기 절연막을 제거하는 단계;Removing the insulating film; 상기 하드마스크막을 식각장벽으로 하여 상기 제1도전막을 일부 식각하는 단계;Etching the first conductive layer partially by using the hard mask layer as an etch barrier; 상기 일부 식각된 제1도전막을 포함한 전면에 캡핑막을 형성하는 단계; 및Forming a capping layer on the entire surface including the partially etched first conductive layer; And 상기 캡핑막과 상기 제1도전막의 나머지를 식각하는 단계Etching the rest of the capping layer and the first conductive layer 를 포함하는 반도체소자의 게이트 제조 방법.Gate manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 오프닝의 하부영역을 채우도록 상기 제2도전막과 보호막을 식각하는 단계는,Etching the second conductive film and the protective film to fill the lower region of the opening, 상기 절연막의 표면이 드러나도록 상기 제2도전막과 보호막을 동시에 1차 식각하는 단계; 및Simultaneously etching the second conductive film and the protective film simultaneously so that the surface of the insulating film is exposed; And 상기 오프닝의 하부 영역을 채우는 형태가 될때까지 상기 제2도전막과 보호막을 추가로 2차 식각하는 단계Further etching the second conductive layer and the protective layer until the second region is filled to fill the lower region of the opening. 를 포함하는 반도체소자의 게이트 제조 방법.Gate manufacturing method of a semiconductor device comprising a. 제2항에 있어서,The method of claim 2, 상기 1차 식각은 에치백(Etchback) 공정이고, 상기 2차 식각은 습식딥 식각(Wet dip etch)인 반도체소자의 게이트 제조 방법.The first etching is an etchback process, the second etching is a wet dip etch (Wet dip etch) method of manufacturing a gate of a semiconductor device. 제1항에 있어서,The method of claim 1, 상기 보호막은 텅스텐실리사이드막인 반도체소자의 게이트 제조 방법.And the protective film is a tungsten silicide film. 제4항에 있어서,The method of claim 4, wherein 상기 보호막은 5∼50Å의 두께로 형성하는 반도체소자의 게이트 제조 방법.The protective film is a gate device manufacturing method of a semiconductor device to form a thickness of 5 ~ 50Å. 제1항에 있어서,The method of claim 1, 상기 절연막은, 산화막과 폴리실리콘막의 순서로 적층된 구조인 반도체소자의 게이트 제조 방법.And the insulating film has a structure in which an oxide film and a polysilicon film are stacked in this order. 제6항에 있어서,The method of claim 6, 상기 폴리실리콘막은 불순물이 도핑되지 않은 폴리실리콘막인 반도체소자의 게이트 제조 방법.And the polysilicon film is a polysilicon film not doped with impurities. 제6항에 있어서,The method of claim 6, 상기 절연막은 2500∼3000Å 두께인 반도체소자의 게이트 제조 방법.The insulating film is a gate manufacturing method of a semiconductor device having a thickness of 2500 ~ 3000Å. 제1항에 있어서,The method of claim 1, 상기 하드마스크막과 캡핑막은 질화막인 반도체소자의 게이트 제조 방법.And the hard mask and capping layers are nitride films. 제1항에 있어서,The method of claim 1, 상기 제1도전막은 폴리실리콘막으로 형성하고, 상기 제2도전막은 텅스텐막으 로 형성하는 반도체소자의 게이트 제조 방법.And the first conductive film is formed of a polysilicon film, and the second conductive film is formed of a tungsten film. 제1도전막;A first conductive film; 상기 제1도전막 상의 금속실리사이드막;A metal silicide film on the first conductive film; 상기 금속실리사이드막 상의 제2도전막;A second conductive film on the metal silicide film; 상기 제2도전막 상의 게이트하드마스크막; 및A gate hard mask layer on the second conductive layer; And 상기 제1도전막의 상부 측벽과 상기 게이트하드마스크막 및 금속실리사이드막의 측벽을 덮는 캡핑막Capping layers covering upper sidewalls of the first conductive layer and sidewalls of the gate hard mask layer and the metal silicide layer 을 포함하는 반도체소자의 게이트.Gate of the semiconductor device comprising a. 제11항에 있어서,The method of claim 11, 상기 금속실리사이드막은 상기 제2도전막의 바닥 및 양측벽을 덮는 형태인 반도체소자의 게이트.The metal silicide layer has a gate covering the bottom and both side walls of the second conductive layer. 제11항에 있어서,The method of claim 11, 상기 금속실리사이드막은 텅스텐실리사이드막인 반도체소자의 게이트.The metal silicide film is a tungsten silicide film. 제11항에 있어서,The method of claim 11, 상기 금속실리사이드막은 5∼50Å의 두께인 반도체소자의 게이트.The metal silicide film is a gate of a semiconductor device having a thickness of 5 to 50 GPa. 제11항에 있어서,The method of claim 11, 상기 게이트하드마스크막과 캡핑막은 질화막인 반도체소자의 게이트.The gate hard mask layer and the capping layer are nitride films. 제11항에 있어서,The method of claim 11, 상기 제1도전막은 폴리실리콘막이고, 상기 제2도전막은 텅스텐막인 반도체소자의 게이트.Wherein the first conductive film is a polysilicon film, and the second conductive film is a tungsten film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111092014A (en) * 2018-10-24 2020-05-01 中电海康集团有限公司 Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111092014A (en) * 2018-10-24 2020-05-01 中电海康集团有限公司 Method for manufacturing semiconductor device

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