CN110911362A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN110911362A
CN110911362A CN201910147220.XA CN201910147220A CN110911362A CN 110911362 A CN110911362 A CN 110911362A CN 201910147220 A CN201910147220 A CN 201910147220A CN 110911362 A CN110911362 A CN 110911362A
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China
Prior art keywords
semiconductor device
paste
substrate
semiconductor
metal film
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Granted
Application number
CN201910147220.XA
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Chinese (zh)
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CN110911362B (en
Inventor
藤卷明子
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

Embodiments provide a semiconductor device in which an electronic component can dissipate heat. A semiconductor device according to one embodiment includes a substrate, a semiconductor component, and a heat conductor. The semiconductor component includes an interposer substrate, an electronic component mounted on a 1 st surface of the interposer substrate, a coating resin in contact with the 1 st surface and the electronic component and covering the 1 st surface and the electronic component, and a metal film in contact with the coating resin and covering the coating resin, and is mounted on the substrate. The heat conductor is attached to the metal film, connects the substrate and the metal film, and has a thermal conductivity higher than that of the coating resin.

Description

Semiconductor device with a plurality of semiconductor chips
[ related applications ]
This application has priority to applications based on japanese patent application No. 2018-173003 (application date: 2018, 9/14). The present application incorporates the entire contents of the base application by reference thereto.
Technical Field
Embodiments of the present invention relate to a semiconductor device.
Background
A semiconductor component is known in which an electronic component mounted on an interposer substrate is sealed with a sealing resin. The semiconductor component is mounted on the substrate via the terminal. The semiconductor parts conduct heat to the substrate via the terminals, thereby dissipating heat. However, the semiconductor component may not sufficiently dissipate heat from the terminal.
Disclosure of Invention
Embodiments provide a semiconductor device in which an electronic component can dissipate heat.
A semiconductor device according to one embodiment includes a substrate, a semiconductor component, and a heat conductor. The semiconductor component includes an interposer substrate, an electronic component mounted on a 1 st surface of the interposer substrate, a coating resin in contact with the 1 st surface and the electronic component and covering the 1 st surface and the electronic component, and a metal film in contact with the coating resin and covering the coating resin, and is mounted on the substrate. The heat conductor is attached to the metal film, connects the substrate and the metal film, and has a thermal conductivity higher than that of the coating resin.
Drawings
Fig. 1 is a cross-sectional view schematically showing a part of a semiconductor device according to embodiment 1.
Fig. 2 is an exploded perspective view schematically showing the semiconductor device according to embodiment 1.
Fig. 3 is an exemplary plan view schematically showing a part of the semiconductor device according to embodiment 1.
Fig. 4 is a cross-sectional view schematically showing a part of the semiconductor device according to embodiment 2.
Fig. 5 is a cross-sectional view schematically showing a part of the semiconductor device according to embodiment 3.
Fig. 6 is an exemplary plan view schematically showing a part of the semiconductor device according to embodiment 3.
Fig. 7 is an exemplary plan view schematically showing a part of a semiconductor device according to a modification of embodiment 3.
Fig. 8 is a cross-sectional view schematically showing a part of the semiconductor device according to embodiment 4.
Detailed Description
(embodiment 1)
Hereinafter, embodiment 1 will be described with reference to fig. 1 to 3. In the present specification, the constituent elements of the embodiments and the description of the elements may be described in various forms of expressions. The constituent elements and their descriptions are not limited by the expressions of the present specification. The constituent elements may be designated by names different from those in the present specification. In addition, the constituent elements may be described by expressions different from those of the present specification.
Fig. 1 is a cross-sectional view schematically showing a part of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 may also be referred to as an electronic apparatus or a semiconductor memory device. The semiconductor device 1 in this embodiment is a smartphone. The semiconductor device 1 may be, for example, a personal computer, a portable computer, a tablet, a mobile phone, a television receiver, a Hard Disk Drive (HDD), a Solid State Drive (SSD), a USB (Universal Serial Bus) Flash Drive, an SD (Secure Digital) card, an eMMC (registered trademark), a Universal Flash Storage (UFS), a memory card, another Storage device, a wearable device, a smart speaker, a home electric appliance, or another device including a semiconductor. As shown in fig. 1, the semiconductor device 1 includes a substrate 5, a semiconductor component 6, and a heat conductor 7.
The substrate 5 is, for example, a Printed Circuit Board (PCB). The substrate 5 has a surface 5 a. The surface 5a is a substantially flat surface facing the positive Z-axis direction (the direction indicated by the Z-axis arrow). A semiconductor component 6 is mounted on the front surface 5a of the substrate 5. Further, other devices such as a Central Processing Unit (CPU) for controlling the semiconductor device 1 may be mounted on the substrate 5.
The substrate 5 further includes a plurality of base materials 11, a plurality of conductor layers 12, a plurality of through holes 13, and two solder resists 14. That is, the substrate 5 is a multilayer board including a plurality of layers, but may be a single panel.
The base material 11 is an insulating layer provided inside the substrate 5. The conductor layer 12 is provided on the surface of the base material 11, and forms, for example, wiring, pads, and solid patterns (planes) in the substrate 5. The through-holes 13 are provided in the substrate 11 and connect the plurality of conductor layers 12. Solder resist 14 covers substrate 11 and conductor layer 12. A solder resist 14 forms at least a part of the surface 5a of the substrate 5, between the base material 11 and the semiconductor part 6.
The conductive layer 12 includes a power supply 16, a ground 17, a plurality of electrodes 18, and a plurality of ground pads 19. The ground pad 19 is an example of a conductor, and may be referred to as a pad or a pattern.
The power supply 16 includes, for example, a power supply layer having a solid pattern and a wiring connected to the power supply layer. The ground 17 is a conductor of ground potential. The ground 17 includes, for example, a ground layer having a solid pattern and a wiring connected to the ground layer.
The electrode 18 is provided on the conductor layer 12 covered with the solder resist 14 forming the surface 5 a. The electrodes 18 include a signal electrode 18A, a power supply electrode 18B, and a ground electrode 18C. The signal electrode 18A is used for transmission and reception of signals between the circuit provided on the substrate 5 and the semiconductor component 6. Thus, an electrical signal passes through the signal electrode 18A. The power supply electrode 18B is connected to the power supply 16. The ground electrode 18C is connected to the ground 17.
The electrodes 18 are arranged in a matrix (grid), for example. The ground electrode 18C is disposed outside the signal electrode 18A and the power supply electrode 18B. Further, the electrode connected to the ground 17 may be located further inside than the signal electrode 18A and the power supply electrode 18B.
The ground pad 19 is provided on the conductor layer 12 covered with the solder resist 14 forming the surface 5 a. The ground pad 19 is connected to the ground 17.
Fig. 2 is an exemplary perspective view schematically showing semiconductor device 1 according to embodiment 1 in an exploded manner. As shown in fig. 2, the ground pad 19 extends along the electrode 18, surrounding the electrode 18. The plurality of ground pads 19 are separated from each other. Therefore, the conductor layer 12 may have a wiring passing between the two ground pads 19.
As shown in fig. 1, a plurality of holes 14a are provided in the solder resist 14. The hole 14a exposes the electrode 18 and the ground pad 19. Thus, the electrode 18 and the ground pad 19 are provided on the surface 5a of the substrate 5.
The semiconductor component 6 in this embodiment is a Ball Grid Array (BGA) semiconductor package. The semiconductor component 6 may have another structure, and may be a semiconductor package of another specification such as Land Grid Array (LGA).
As shown in the drawings, in the present specification, X, Y and Z axes are defined. The X, Y and Z axes are orthogonal to each other. The X-axis is along the width of the semiconductor part 6. The Y-axis is along the length (depth) of the semiconductor part 6. The Z-axis is along the height (thickness) of the semiconductor part 6.
The semiconductor part 6 includes an interposer substrate 21, a controller chip 22, a plurality of memory chips 23, a plurality of bonding wires 24, a sealing resin 25, and a metal film 26. The controller chip 22 and the memory chip 23 are examples of electronic components. The sealing resin 25 is an example of a coating resin.
The interposer substrate 21 is, for example, a Printed Wiring Board (PWB). The interposer substrate 21 has a 1 st surface 21a, a 2 nd surface 21b, and an end surface 21 c. The 1 st surface 21a is a substantially flat surface facing the positive direction of the Z axis. The 2 nd surface 21b is a substantially flat surface located on the opposite side of the 1 st surface 21a and oriented in the negative direction of the Z axis (the opposite direction of the arrow of the Z axis). The 2 nd surface 21b and the surface 5a of the substrate 5 are opposed to each other. The end surface 21c is provided between the edge of the 1 st surface 21a and the edge of the 2 nd surface 21b, and faces in a direction intersecting the Z axis.
The interposer substrate 21 also has a plurality of terminals 31. The terminals 31 include pads 35 and solder balls 36, respectively. Solder balls 36 may also be referred to as bumps. The solder balls 36 are connected to the corresponding electrodes 18. The terminal 31 may be different from the pad 35 and the solder ball 36, for example, according to the specification of the semiconductor component 6. For example, when the semiconductor component 6 is an LGA, the terminal 31 includes the pad 35 and does not include the solder ball 36.
The terminal 31 is provided on the 2 nd surface 21 b. The terminals 31 include a signal terminal 31A, a power supply terminal 31B, and a ground terminal 31C. The signal terminal 31A is connected to the signal electrode 18A. The power supply terminal 31B is connected to the power supply electrode 18B. The ground terminal 31C is connected to the ground electrode 18C.
The terminals 31 are arranged in a matrix (grid), for example. The ground terminal 31C is disposed outside the signal terminal 31A and the power supply terminal 31B. The terminal 31 connected to the ground 17 via the electrode 18 may be located further inside than the signal terminal 31A and the power supply terminal 31B.
The controller Chip 22 is, for example, a System on a Chip (SoC). In addition, the controller chip 22 may also be other Integrated Circuits (ICs) or circuits.
The controller chip 22 is mounted on the 1 st surface 21a of the interposer substrate 21. For example, the controller chip 22 is adhered to the 1 st surface 21a by an adhesive layer 22 a. Further, the electrode of the controller chip 22 and the electrode provided on the 1 st surface 21a are connected by a bonding wire 24. Thereby, the controller chip 22 is electrically connected to the terminals 31 via the wires provided on the interposer substrate 21. The controller chip 22 may be mounted on the 1 st surface 21a by flip-chip mounting, for example.
The memory chip 23 is, for example, a NAND (Not AND) flash memory, AND stores information. The memory chip 23 may be another memory chip such as a NOR (Not Or) type flash memory.
The memory chip 23 is mounted on and stacked on the 1 st surface 21a of the interposer substrate 21. For example, the memory chip 23 is bonded to the 1 st surface 21a by an adhesive layer 23 a. Further, the electrodes of the memory chip 23 and the electrodes provided on the 1 st surface 21a are connected by bonding wires 24. Thus, the memory chip 23 is electrically connected to the controller chip 22 via the wiring provided on the interposer substrate 21. The memory chip 23 may be mounted on the 1 st surface 21a by flip-chip mounting, for example.
The adhesive layers 22a, 23a are Die Attach Films (DAF). The Die attach Film may also be referred to as a Die Bonding Film (Die Bonding Film). The adhesive layers 22a and 23a may be an adhesive, for example.
The controller chip 22 controls, for example, storage and readout of the memory chip 23. The controller chip 22 is not limited to controlling the memory chip 23, and may control other electronic components included in the semiconductor component 6.
In the present embodiment, the controller chip 22 and the memory chip 23 are mounted on the 1 st surface 21 a. However, the memory chip 23 may be stacked on the controller chip 22, for example.
The sealing resin 25 is made of, for example, a synthetic resin containing an epoxy resin mixed with an inorganic substance such as silica. The sealing resin 25 may be made of a material containing another synthetic resin.
The sealing resin 25 seals the 1 st surface 21a of the interposer substrate 21, the controller chip 22, the memory chip 23, and the bonding wires 24. Therefore, the sealing resin 25 is in contact with the 1 st surface 21a, the controller chip 22, the memory chip 23, and the bonding wires 24, and covers the 1 st surface 21a, the controller chip 22, the memory chip 23, and the bonding wires 24.
The controller chip 22, the memory chip 23, and the bonding wires 24 are embedded in a sealing resin 25. According to another expression, the controller chip 22, the memory chip 23, and the bonding wires 24 are housed in the sealing resin 25 and are located in the sealing resin 25.
The sealing resin 25 has an upper surface 25a and a side surface 25 b. The upper surface 25a is an outer surface of the substantially flat sealing resin 25 facing the positive direction of the Z axis. The side surface 25b is an outer surface of the sealing resin 25 extending from an edge of the upper surface 25a in the negative direction of the Z axis, and faces in a direction intersecting the Z axis. The side surface 25b is substantially connected to the end surface 21c of the interposer substrate 21.
The metal film 26 is in contact with the upper surface 25a and the side surface 25b of the sealing resin 25 and covers the sealing resin 25. In the present embodiment, the metal film 26 also covers the end face 21c of the interposer substrate 21. The metal film 26 is attached to the sealing resin 25 by sputtering, for example. The metal film 26 may be formed by other methods such as paste coating.
The metal film 26 has an upper surface 26a and a side surface 26 b. The upper surface 26a is an outer surface of the substantially flat metal film 26 facing the positive direction of the Z axis. The side surface 26b is an outer surface of the metal film 26 extending from an edge of the upper surface 26a in the negative direction of the Z axis, and faces in a direction substantially intersecting the Z axis.
The metal film 26 covers the controller chip 22 and the memory chip 23 with the sealing resin 25 interposed therebetween. The metal film 26 is an electromagnetic shield for shielding electromagnetic waves emitted from the controller chip 22 and the memory chip 23 or external electromagnetic waves.
The thermal conductor 7 connects the substrate 5 with the metal film 26 of the semiconductor component 6. The heat conductor 7 has electrical conductivity as a whole and higher thermal conductivity than the sealing resin 25. The thermal conductor 7 may have a higher thermal conductivity than the sealing resin 25 in the thermal path between the substrate 5 and the metal film 26. Therefore, the heat conductor 7 may also include a portion having lower thermal conductivity than the sealing resin 25. The heat conductor 7 may include an insulating portion. The heat conductor 7 includes a metal member 41, a 1 st paste 42, and a 2 nd paste 43.
As shown in fig. 2, metal member 41 is formed in a substantially quadrangular ring shape corresponding to ground pad 19 of substrate 5. The shape of the metal member 41 is not limited to this example, and may be, for example, a rod. The metal member 41 has higher thermal conductivity than the sealing resin 25.
Fig. 3 is an exemplary plan view schematically showing a part of the semiconductor device 1 according to embodiment 1. In fig. 3, the 1 st paste 42 and the 2 nd paste 43 are omitted for convenience. As shown in fig. 3, the metal member 41 surrounds the semiconductor component 6 and is spaced apart therefrom in a plan view toward the surface 5a of the substrate 5. In other words, the metal member 41 is separated from the semiconductor part 6 in a direction intersecting the Z-axis. The semiconductor component 6 may partially overlap the metal member 41 in a direction intersecting the Z axis.
As shown in fig. 1, the metal member 41 covers the ground pad 19. The metal member 41 is bonded to the ground pad 19 provided on the surface 5a by the 2 nd paste 43. Further, the metal member 41 may be further bonded to another portion of the surface 5a formed by the solder resist 14. In addition, the metal member 41 may be connected to the ground pad 19 by another method such as solder.
The 2 nd paste 43 is a so-called thermal conductive paste. The 2 nd paste 43 contains, for example, thermosetting synthetic resin and silver filler. Therefore, the 2 nd paste 43 has electrical conductivity and has higher thermal conductivity than the sealing resin 25. For example, the thermal conductivity of the No. 2 paste 43 is 50W/mK or more, but is not limited to this value. The 2 nd paste 43 may contain silicon instead of the silver filler, and thus may have insulating properties. The above material of the 2 nd paste 43 is an example, and is not limited to these examples.
The 2 nd paste 43 is cured in a state of being attached to the metal member 41 and the ground pad 19. Therefore, the 2 nd paste 43 fixes the metal member 41 to the ground pad 19. The No. 2 paste 43 may have fluidity without being hardened. The metal member 41 is thermally and electrically connected to the ground pad 19 by the 2 nd paste 43.
The 1 st paste 42 is a so-called thermal conductive paste as in the 2 nd paste 43. The 1 st paste 42 contains, for example, thermosetting synthetic resin and silver filler. Therefore, the 1 st paste 42 has electrical conductivity and has higher thermal conductivity than the sealing resin 25. For example, the thermal conductivity of the 1 st paste 42 is 50W/mK or more, but is not limited to this value. The 1 st paste 42 may have insulating properties by containing silicon instead of the silver filler. The material of the above-described 1 st paste 42 is an example, and is not limited to these examples.
The 1 st paste 42 is cured while adhering to the side surface 26b of the metal film 26 and the metal member 41. Therefore, the 1 st paste 42 thermally and electrically connects the metal film 26 to the metal member 41. The 1 st paste 42 may have fluidity without being hardened.
The 1 st paste 42 thermally and electrically connects the metal film 26 and the ground pad 19 of the substrate 5 via the metal member 41 and the 2 nd paste 43. Therefore, heat generated from the controller chip 22 and the memory chip 23 is conducted to the ground pad 19 via the sealing resin 25, the metal film 26, the 1 st paste 42, the metal member 41, and the 2 nd paste 43. The heat conducted to the ground pad 19 is released to a device such as a server or a personal computer on which the semiconductor device 1 is mounted, for example.
As shown in fig. 3, the 1 st paste 42 has a portion P closer to the controller chip 22 than to the memory chip 23. The controller chip 22 becomes a high temperature more easily than the memory chip 23. Heat generated from the controller chip 22 can be released through the nearby 1 st paste 42.
As shown in fig. 1, the metal film 26 is electrically connected to the ground 17 via the 1 st paste 42, the metal member 41, the 2 nd paste 43, and the ground pad 19. The metal film 26 can discharge the absorbed electromagnetic noise to the ground 17.
Hereinafter, a method of mounting the semiconductor component 6 and the heat conductor 7 will be partially exemplified. The method of mounting semiconductor component 6 and heat conductor 7 is not limited to the following method, and other methods may be used. First, the terminal 31 of the semiconductor component 6 is connected to the electrode 18 of the substrate 5. The solder balls 36 of the terminals 31 are connected to the electrodes 18 by, for example, reflow soldering.
Next, the 2 nd paste 43 is applied to the ground pad 19 by a dispenser. Further, the metal member 41 is placed on the 2 nd paste 43, and is bonded to the ground pad 19 by the 2 nd paste 43.
Next, the 1 st paste 42 is supplied between the metal member 41 and the metal film 26 by a dispenser. The 1 st paste 42 is attached to the metal member 41 and the metal film 26. Next, the 2 nd paste 43 and the 1 st paste 42 are thermally cured, whereby the semiconductor component 6 and the heat conductor 7 are mounted.
By adjusting the viscosity of the 1 st paste 42, the 1 st paste 42 is suppressed from entering the gap between the substrate 5 and the interposer substrate 21. However, the 1 st paste 42 may enter the gap between the substrate 5 and the interposer substrate 21.
As described above, the ground terminal 31C is disposed outside the signal terminal 31A and the power supply terminal 31B. Therefore, the ground terminal 31C is closer to the heat conductor 7 than the signal terminal 31A and the power supply terminal 31B.
The 1 st paste 42 that has entered the gap between the substrate 5 and the interposer substrate 21 is more likely to adhere to the ground terminal 31C than to adhere to the signal terminal 31A and the power supply terminal 31B. In this case, the metal film 26 and the metal member 41 are electrically connected to the ground terminal 31C and the ground 17 via the 1 st paste 42. However, the metal film 26 and the metal member 41 are typically electrically connected to the ground 17 via the ground pad 19. Therefore, the ground terminal 31C is suppressed from being short-circuited.
The plurality of ground terminals 31C are arranged along the end face 21C of the interposer substrate 21. Therefore, the ground terminal 31C blocks the 1 st paste 42, and the 1 st paste 42 is prevented from adhering to the signal terminal 31A and the power supply terminal 31B. The description above is typical for the 1 st paste 42, and the same applies to the 2 nd paste 43.
In the semiconductor device 1 according to embodiment 1 described above, the heat conductor 7 is attached to the metal film 26 of the semiconductor component 6, the substrate 5 is connected to the metal film 26, and the thermal conductivity is higher than that of the sealing resin 25. Thus, heat generated from the controller chip 22 and the memory chip 23 can be conducted to the substrate 5 through the sealing resin 25, the metal film 26, and the heat conductor 7. Therefore, the controller chip 22 and the memory chip 23 can dissipate heat further.
The substrate 5 has a ground pad 19 disposed on the surface 5 a. The heat conductor 7 connects the metal film 26 with the ground pad 19. Thus, heat generated from the controller chip 22 and the memory chip 23 can be efficiently conducted to the substrate 5 via the heat conductor 7, compared to a case where the heat conductor 7 connects another portion of the substrate 5 such as the solder resist 14 to the metal film 26. Therefore, the controller chip 22 and the memory chip 23 can efficiently dissipate heat.
The heat conductor 7 is conductive, and the ground pad 19 is connected to the ground 17. Thereby, the metal film 26 of the semiconductor component 6 is electrically connected to the ground 17 via the heat conductor 7. Therefore, the performance of the metal film 26 as an electromagnetic shield can be improved.
The ground terminal 31C is connected to the ground 17 via the ground electrode 18C and is located closer to the heat conductor 7 than the signal terminal 31A and the power supply terminal 31B. Therefore, even if the 1 st paste 42 of the thermal conductor 7 enters between the 2 nd surface 21B of the interposer substrate 21 and the surface 5a of the substrate 5, it is more likely to adhere to the ground terminal 31C than to the signal terminal 31A or the power supply terminal 31B. Therefore, the 1 st paste 42 is prevented from adhering to the signal terminal 31A or the power supply terminal 31B to cause short-circuiting.
The thermal conductor 7 includes the 1 st paste 42 attached to the metal film 26. Thereby, the heat conductor 7 can be easily provided by a device such as a dispenser, for example.
The thermal conductor 7 comprises a metal part 41 which is thermally and electrically connected to the ground pad 19. The 1 st paste 42 is attached to the metal member 41. That is, the metal film 26 of the semiconductor component 6 is connected to the ground pad 19 of the substrate 5 via the 1 st paste 42 and the metal member 41. In general, since the metal member 41 has a small thermal resistance and a large surface area as compared with a synthetic resin, it is possible to efficiently conduct heat generated from the controller chip 22 and the memory chip 23 to the substrate 5. Therefore, the controller chip 22 and the memory chip 23 can efficiently dissipate heat.
The metal member 41 surrounds the semiconductor component 6 in a plan view toward the surface 5 a. This increases the surface area of the metal member 41, and heat generated from the controller chip 22 and the memory chip 23 can be efficiently conducted to the substrate 5. Therefore, the controller chip 22 and the memory chip 23 can efficiently dissipate heat.
The 1 st paste 42 contains a thermosetting resin. Thus, the 1 st paste 42 is cured, thereby preventing the 1 st paste 42 from peeling off from the metal film 26. Further, the 1 st paste 42 may be cured simultaneously with curing of the underfill applied to other electronic components. Therefore, an increase in the number of working steps is suppressed, thereby suppressing an increase in the cost of the semiconductor device 1.
The heat conductor 7 includes a 2 nd paste 43, and the 2 nd paste 43 includes a thermosetting resin, is attached to the metal member 41 and the ground pad 19, has a higher thermal conductivity than the sealing resin 25, and has an electrical conductivity. The 1 st paste 42 and the 2 nd paste 43 are cured. Thereby, the metal member 41 and the ground pad 19 are electrically connected through the 2 nd paste 43. Furthermore, the 1 st paste 42 and the 2 nd paste 43 can be cured at the same time, so that an increase in the number of working steps can be suppressed, and an increase in the cost of the semiconductor device 1 can be suppressed. The 1 st paste 42 and the 2 nd paste 43 firmly fix the semiconductor component 6 to the substrate 5 like underfill. This suppresses damage to the connection portion between the terminal 31 and the electrode 18.
The thermal conductor 7 has a portion P closer to the controller chip 22 than to the memory chip 23. In general, the controller chip 22 becomes higher in temperature more easily than the memory chip 23. Therefore, the heat of the controller chip 22 can be conducted to the substrate 5 via the sealing resin 25, the metal film 26, and the heat conductor 7. Therefore, the controller chip 22 and the memory chip 23 can efficiently dissipate heat.
In embodiment 1 described above, the 1 st paste 42 and the 2 nd paste 43 connect the metal film 26 and the ground pad 19 via the metal member 41. However, the 1 st paste 42 or the 2 nd paste 43 may also directly connect the metal film 26 with the ground pad 19. This suppresses an increase in the number of work steps, and thus suppresses an increase in the cost of the semiconductor device 1.
In addition, in embodiment 1 above, the ground pad 19 connected to the heat conductor 7 is connected to the ground 17. However, the conductor (ground pad 19) connected to the heat conductor 7 may be a non-connection pad electrically disconnected from the conductor layer 12 forming a circuit on the substrate 5. In addition, if the heat conductor 7 is insulating, the conductor may be electrically connected to the signal electrode 18A or the power supply electrode 18B, for example.
(embodiment 2)
Hereinafter, embodiment 2 will be described with reference to fig. 4. In the following description of the embodiments, the components having the same functions as those of the components already described are denoted by the same reference numerals as those of the components already described, and the description thereof may be omitted. Note that the plurality of constituent elements denoted by the same reference numerals are not limited to all common functions and properties, and may have different functions and properties according to the respective embodiments.
Fig. 4 is a cross-sectional view schematically showing a part of the semiconductor device 1 according to embodiment 2. As shown in fig. 4, the semiconductor device 1 according to embodiment 2 includes an insulating underfill adhesive 51. The underfill 51 is interposed between the surface 5a of the substrate 5 and the 2 nd surface 21b of the interposer substrate 21.
The underfill 51 blocks a gap between the surface 5a of the substrate 5 and the 2 nd surface 21b of the interposer substrate 21. Thus, the underfill 51 is positioned between the terminal 31 and the heat conductor 7. In the present embodiment, the underfill 51 contacts the terminals 31 and covers the terminals 31. Further, the underfill 51 may also be separated from the terminal 31.
The underfill 51 is supplied between the substrate 5 and the interposer substrate 21 by a dispenser after the terminals 31 are connected to the electrodes 18, for example. Underfill 51 may also be thermally cured with, for example, first paste 42 and second paste 43.
In the semiconductor device 1 according to embodiment 2 described above, the insulating underfill 51 is interposed between the surface 5a of the substrate 5 and the 2 nd surface 21b of the interposer substrate 21 and between the terminal 31 and the heat conductor 7. This suppresses a short circuit caused by the adhesion of the conductive 1 st paste 42 to the terminal 31. Further, since the semiconductor component 6 is firmly fixed to the substrate 5 by the underfill 51, damage of the connection portion between the terminal 31 and the electrode 18 is suppressed.
(embodiment 3)
Hereinafter, embodiment 3 will be described with reference to fig. 5 to 7. Fig. 5 is a cross-sectional view schematically showing a part of the semiconductor device 1 according to embodiment 3. As shown in fig. 5, the semiconductor device 1 according to embodiment 3 is different from that according to embodiment 2 in that: includes a plurality of semiconductor components 6 mounted on a front surface 5a of a substrate 5. The semiconductor components 6 may be the same components or different components. As in embodiment 1, the semiconductor device 1 according to embodiment 3 may not include the underfill adhesive 51.
Fig. 6 is an exemplary plan view schematically showing a part of the semiconductor device 1 according to embodiment 3. As shown in fig. 6, metal member 41 includes frame portion 61 and intermediate portion 62. The frame portion 61 is formed in a substantially rectangular ring shape, and surrounds the plurality of semiconductor components 6 in a plan view facing the front surface 5a of the substrate 5. The intermediate portion 62 is located between two adjacent semiconductor components 6, and is connected to the frame portion 61.
The 1 st paste 42 is attached to the metal film 26, the frame portion 61, and the intermediate portion 62. Therefore, the 1 st paste 42 thermally and electrically connects the metal film 26 of the one semiconductor component 6, the metal film 26 of the other semiconductor component 6, and the ground pad 19.
In the semiconductor device 1 according to embodiment 3 described above, the metal member 41 surrounds the plurality of semiconductor components 6 in a plan view of the front surface 5 a. This increases the surface area of the metal member 41, and heat generated from the controller chip 22 and the memory chip 23 can be efficiently conducted to the substrate 5. Therefore, the controller chip 22 and the memory chip 23 can efficiently dissipate heat.
Fig. 7 is an exemplary plan view schematically showing a part of a semiconductor device 1 according to a modification of embodiment 3. As shown in fig. 7, metal member 41 has frame 61. However, the intermediate portion 62 is omitted. Two adjacent semiconductor components 6 are separated from each other with a gap therebetween.
In the modification of fig. 7, for example, the region on the front surface 5a of the substrate 5 where the semiconductor component 6 can be mounted is narrower than the example of fig. 6. Therefore, the intermediate portion 62 is omitted, and the distance between two adjacent semiconductor parts 6 is shorter than in the example of fig. 6.
In the modification of embodiment 3 described above, the frame portion 61 also surrounds the plurality of semiconductor components 6 in a plan view toward the front surface 5 a. Therefore, even if the gap between the plurality of semiconductor components 6 is small, the metal member 41 can be arranged along the plurality of semiconductor components 6. Therefore, even if the arrangement of the semiconductor components 6 in the substrate 5 is restricted, the 1 st paste 42 can be attached to the metal film 26 and the metal member 41.
(embodiment 4)
Hereinafter, embodiment 4 will be described with reference to fig. 8. Fig. 8 is a cross-sectional view schematically showing a part of the semiconductor device 1 according to embodiment 4. As shown in fig. 8, the semiconductor device 1 according to embodiment 4 is different from embodiment 3 in that: metal member 41, No. 2 paste 43, and ground pad 19 are not included. As in embodiment 1, the semiconductor device 1 according to embodiment 4 may not include the underfill adhesive 51, and may include a single semiconductor component 6.
In embodiment 4, the base material 11 has an exposed portion 11 a. Exposed portion 11a is a portion of base material 11 exposed on surface 5a of substrate 5 through hole 14a of solder resist 14. The surface roughness of exposed portion 11a of substrate 11 is coarser than the surface roughness of solder resist 14.
The 1 st paste 42 is attached to the side surface 26b of the metal film 26 and the exposed portion 11a exposed through the hole 14 a. Thus, the 1 st paste 42 connects the metal film 26 to the base material 11 of the substrate 5.
In the semiconductor device 1 according to embodiment 4 described above, the solder resist 14 is provided with the hole 14a for exposing the exposed portion 11a of the substrate 11. The 1 st paste 42 is attached to the exposed portion 11 a. Generally, the surface roughness of substrate 11 is coarser than the surface roughness of solder resist 14. This suppresses peeling of the 1 st paste 42 from the substrate 5.
In the above embodiments, the ground terminal 31C is located closer to the heat conductor 7 than the signal terminal 31A and the power supply terminal 31B. However, as a modification, the other terminals 31 may be located closer to the heat conductor 7 than the signal terminals 31A and the power supply terminals 31B. The electrode 18 connected to the terminal 31 is a non-connection pad electrically disconnected from the conductor layer 12 forming a circuit on the substrate 5. This suppresses short-circuiting caused by the adhesion of the 1 st paste 42 to the terminal 31. The terminal 31 and the electrode 18 reinforce the connection portion of the substrate 5 and the semiconductor element 6.
According to at least one embodiment described above, the heat conductor is attached to the metal film of the semiconductor component, connects the substrate and the metal film, and has a higher thermal conductivity than the coating resin. This allows heat generated by the electronic component to be conducted to the substrate via the coating resin, the metal film, and the heat conductor. Therefore, the electronic component can further dissipate heat.
Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other various ways, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.
[ description of symbols ]
1 semiconductor device
5 substrate
5a surface
6 semiconductor component
7 Heat conductor
11 base material
11a exposed part
14 solder resist
14a hole
16 power supply
17 is grounded
18 electrodes
18A signal electrode
18B power supply electrode
18C ground electrode
19 ground pad
21 interposer substrate
21a 1 st surface
21b No. 2
22 controller chip
23 memory chip
25 sealing resin
26 metal film
31 terminal
31A signal terminal
31B power supply terminal
31C grounding terminal
41 Metal part
42 st paste
43 ointment 2
51 underfill

Claims (16)

1. A semiconductor device includes:
a substrate;
a semiconductor component including an interposer substrate, an electronic component mounted on a 1 st surface of the interposer substrate, a coating resin in contact with the 1 st surface and the electronic component and covering the 1 st surface and the electronic component, and a metal film in contact with the coating resin and covering the coating resin, the semiconductor component being mounted on the substrate;
and
and a heat conductor attached to the metal film, connecting the substrate and the metal film, and having a thermal conductivity higher than that of the coating resin.
2. The semiconductor device according to claim 1, wherein the interposer substrate has a 2 nd surface located on an opposite side of the 1 st surface, and a terminal provided on the 2 nd surface,
the substrate has a surface facing the 2 nd surface, an electrode provided on the surface and connected to the terminal, and a conductor provided on the surface
The heat conductor connects the metal film and the conductor.
3. The semiconductor device according to claim 2, wherein the heat conductor is electrically conductive,
the substrate has a ground, an
The conductor is connected to the ground.
4. The semiconductor device according to claim 3, wherein the electrode has a signal electrode for passing an electric signal, a power supply electrode connected to a power supply, and a ground electrode connected to the ground, and
the terminal includes a signal terminal connected to the signal electrode, a power supply terminal connected to the power supply electrode, and a ground terminal connected to the ground electrode and closer to the heat conductor than the signal terminal and the power supply terminal.
5. The semiconductor device according to claim 3, wherein the heat conductor comprises a 1 st paste which has fluidity or is hardened, the 1 st paste being attached to the metal film, having higher thermal conductivity than the coating resin, and having electrical conductivity.
6. The semiconductor device according to claim 5, wherein the heat conductor has a metal member thermally connected and electrically connected to the conductor, and
the first paste 1 is attached to the metal film and the metal member.
7. The semiconductor device according to claim 6, wherein the metal member surrounds the semiconductor part in a plan view toward the surface.
8. The semiconductor device according to claim 6, further comprising a plurality of the semiconductor components, wherein
The metal member surrounds the plurality of semiconductor parts in a plan view toward the surface.
9. The semiconductor device according to claim 6, wherein the 1 st paste contains a thermosetting resin.
10. The semiconductor device according to claim 9, wherein the heat conductor comprises a cured 2 nd paste, the 2 nd paste comprises a thermosetting resin, adheres to the metal member and the conductor, has a higher thermal conductivity than the coating resin, and has an electrical conductivity, and
the 1 st paste hardens.
11. The semiconductor device according to claim 2, further comprising an insulating underfill interposed between the surface of the substrate and the 2 nd surface of the interposer substrate and positioned between the terminal and the heat conductor.
12. The semiconductor device according to claim 1, wherein the substrate comprises a base material, and a solder resist covering the base material and located between the base material and the semiconductor part,
the solder resist is provided with a hole exposing a part of the base material, and
the heat conductor is attached to a portion of the base material exposed through the hole.
13. The semiconductor device according to any one of claims 1 to 4 and 12, wherein the heat conductor comprises a paste having fluidity or being hardened, the paste being attached to the metal film and having higher thermal conductivity than the coating resin.
14. The semiconductor device according to claim 1, wherein the electronic part has a memory chip.
15. The semiconductor device according to claim 14, wherein the electronic part has a controller chip which controls the memory chip.
16. The semiconductor device according to claim 15, wherein the heat conductor has a portion closer to the controller chip than to the memory chip.
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