CN110890382A - 显示装置及其制造方法 - Google Patents

显示装置及其制造方法 Download PDF

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Publication number
CN110890382A
CN110890382A CN201910832800.2A CN201910832800A CN110890382A CN 110890382 A CN110890382 A CN 110890382A CN 201910832800 A CN201910832800 A CN 201910832800A CN 110890382 A CN110890382 A CN 110890382A
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switching
driving
layer
region
semiconductor material
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CN110890382B (zh
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朴晙皙
金兑相
文然建
朴根徹
林俊亨
全景辰
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

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Abstract

提供了一种显示装置及其制造方法。所述显示装置包括：基底，包括显示区域和非显示区域；栅极驱动器，在非显示区域中设置在基底上，并且包括生成栅极信号并将栅极信号输出到显示区域的多个级；开关晶体管和驱动晶体管，在显示区域中设置在基底上；以及发光二极管，连接到驱动晶体管，其中，多个级中的每个级可以包括多个晶体管，其中，驱动晶体管的沟道层包括第一氧化物半导体材料，包括在多个级中的每个级中的多个晶体管的沟道层包括第二氧化物半导体材料，其中，第一氧化物半导体材料与第二氧化物半导体材料不同，并且其中，第二氧化物半导体材料可以包括锡。

Description

显示装置及其制造方法
本申请要求于2018年9月4日在韩国知识产权局提交的第10-2018-0105501号韩国专利申请的优先权和权益，该韩国专利申请的公开内容通过引用被完全包含于此。
技术领域
本公开涉及一种显示装置及其制造方法。
背景技术
诸如发光显示装置的显示装置包括在其上显示图像的显示面板以及用于驱动显示面板的诸如栅极驱动器和数据驱动器的驱动器。驱动器在制造工艺中可以作为单独的芯片被提供并且电连接到显示面板。最近，已经开发了一种将栅极驱动器集成在显示面板中而不将栅极驱动器作为单独的芯片提供的技术。
随着显示装置的分辨率增加，包括在栅极驱动器中的多个级的晶体管的电阻和显示装置的开关晶体管的电阻也增大。因此，在高分辨率显示装置中，这样的晶体管可以形成为具有包括高迁移率的氧化物半导体材料的沟道层，以减小它们的尺寸。
然而，当将高迁移率的氧化物半导体材料应用到显示装置的驱动晶体管的沟道层时，可能达不到驱动晶体管的驱动范围。
在本背景技术部分中公开的上述信息仅用于增强对本公开的背景的理解，并且上述信息可以包含不构成本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供了一种显示装置，在显示装置中，栅极驱动器的晶体管的沟道层和驱动晶体管的沟道层包括不同的材料。
此外，本公开提供了一种通过单个掩模工艺形成包括不同材料的栅极驱动器的晶体管的沟道层和驱动晶体管的沟道层的方法。
本公开的示例性实施例提供了一种显示装置，所述显示装置包括：基底，包括显示区域和非显示区域；栅极驱动器，在非显示区域中设置在基底上，并且包括生成栅极信号并将栅极信号输出到显示区域的多个级；开关晶体管和驱动晶体管，在显示区域中设置在基底上；以及发光二极管，连接到驱动晶体管，其中，多个级中的每个级可以包括多个晶体管，驱动晶体管的沟道层包括第一氧化物半导体材料，包括在多个级中的每个级中的多个晶体管的沟道层包括第二氧化物半导体材料，其中，第一氧化物半导体材料与第二氧化物半导体材料不同，并且第二氧化物半导体材料可以包括锡。
开关晶体管的沟道层可以包括第二氧化物半导体材料。
包括在多个级中的每个级中的多个晶体管的沟道层以及驱动晶体管的沟道层可以设置在不同的层上。
开关晶体管的沟道层以及包括在多个级中的每个级中的多个晶体管的沟道层可以设置在同一层上。
包括在级中的晶体管中的每个晶体管和开关晶体管可以包括：开关半导体层，设置在基底上，并且包括开关源区、开关漏区和设置在开关源区与开关漏区之间的开关中间区；开关沟道层，设置在开关半导体层上；栅极绝缘膜，设置在开关沟道层上；开关栅电极，设置在栅极绝缘膜上并且与开关沟道层的至少一部分叠置；开关源电极，连接到开关源区；以及开关漏电极，连接到开关漏区，开关沟道层与开关半导体层的开关中间区的至少一部分叠置。
包括在多个级中的每个级中的多个晶体管的沟道层以及开关晶体管的沟道层中的每个可以包括开关沟道层。
驱动晶体管可以包括：驱动半导体层，设置在基底上，并且包括驱动源区、驱动漏区以及设置在驱动源区与驱动漏区之间的驱动中间区；栅极绝缘膜，设置在驱动中间区上；驱动栅电极，设置在栅极绝缘膜上并且与驱动中间区的至少一部分叠置；驱动源电极，连接到驱动源区；以及驱动漏电极，连接到驱动漏区。
驱动晶体管的沟道层可以包括驱动中间区。
开关中间区和驱动中间区可以包括相同的材料。
本公开的另一示例性实施例提供了一种制造显示装置的方法，其中，显示装置可以包括：基底，包括显示区域和非显示区域；栅极驱动器，在非显示区域中设置在基底上，并且包括生成栅极信号并将栅极信号输出到显示区域的多个级；开关晶体管和驱动晶体管，在显示区域中设置基底上；发光二极管，连接到驱动晶体管，其中，所述方法可以包括：在基底上顺序地形成第一半导体材料层和第二半导体材料层；通过蚀刻第一半导体材料层形成开关半导体层和驱动半导体层；通过蚀刻第二半导体材料层形成与开关半导体层的至少一部分叠置的开关沟道层；在基底、开关半导体层、驱动半导体层和开关沟道层上形成栅极绝缘膜材料层；在栅极绝缘膜材料层上形成与开关沟道层的至少一部分叠置的开关栅电极以及与驱动半导体层的至少一部分叠置的驱动栅电极；通过利用开关栅电极和驱动栅电极作为掩模对栅极绝缘膜材料层进行蚀刻来形成栅极绝缘膜；在开关半导体层、驱动半导体层、开关栅电极和驱动栅电极上形成层间绝缘膜；在层间绝缘膜上形成开关源电极、开关漏电极、驱动源电极和驱动漏电极；以及形成连接到驱动漏电极的发光二极管，其中，第一半导体材料层可以包括第一氧化物半导体材料，第二半导体材料层可以包括第二氧化物半导体材料，其中，第一氧化物半导体材料与第二氧化物半导体材料不同，并且其中，第二半导体材料层可以包括锡。
开关半导体层和驱动半导体层的形成以及开关沟道层的形成可以包括：在第二半导体材料层上形成第一光致抗蚀剂膜；通过利用第一掩模对第一光致抗蚀剂膜进行曝光和显影来形成第二光致抗蚀剂膜和第三光致抗蚀剂膜；通过第一蚀刻工艺对第一半导体材料层和第二半导体材料层进行蚀刻；通过将第二光致抗蚀剂膜和第三光致抗蚀剂膜灰化形成第四光致抗蚀剂膜；通过第二蚀刻工艺对第二半导体材料层进行蚀刻；以及去除第四光致抗蚀剂膜。
第一掩模可以包括光阻挡区、透射区和半透射区。
第一蚀刻工艺可以包括利用第二光致抗蚀剂膜和第三光致抗蚀剂膜作为掩模蚀刻第一半导体材料层和第二半导体材料层，可以通过蚀刻第一半导体材料层来形成开关半导体层和驱动半导体层。
在形成第四光致抗蚀剂膜的步骤中，可以去除第三光致抗蚀剂膜，并且可以去除第二光致抗蚀剂膜的一部分。
在第二蚀刻工艺中，可以利用第四光致抗蚀剂膜作为第二掩模来对第二半导体材料层进行蚀刻，以形成开关沟道层。
层间绝缘膜的形成可以包括执行热处理以使层间绝缘膜的氢扩散到开关半导体层和所述驱动半导体层中。
多个级中的每个级可以包括多个晶体管，包括在多个级中的每个级中的多个晶体管和开关晶体管可以具有相同的结构。
开关晶体管可以包括开关半导体层、开关沟道层、开关栅电极、开关源电极和开关漏电极，驱动晶体管可以包括驱动半导体层、驱动栅电极、驱动源电极和驱动漏电极。
开关晶体管的沟道层可以包括开关沟道层。
开关半导体层可以包括与开关沟道层的至少一部分叠置的开关中间区，驱动半导体层可以包括与驱动栅电极的至少一部分叠置的驱动中间区，驱动晶体管的沟道层可以包括驱动中间区。
根据本公开的示例性实施例，驱动器的晶体管的沟道层和驱动晶体管的沟道层可以彼此不同。
此外，根据本公开的示例性实施例，可以通过单个掩模工艺形成具有不同材料的驱动器的晶体管的沟道层和驱动晶体管的沟道层。
附图说明
图1示意性地示出了根据本公开的示例性实施例的显示装置。
图2示出了根据图1的显示装置的像素的等效电路图。
图3示出了包括在根据图1的显示装置中的晶体管的剖面的示例。
图4至图13示出了在根据本公开的示例性实施例的显示装置的制造工艺期间的显示装置的剖视图。
图14示出了根据本公开的示例性实施例的显示装置的像素的等效电路图。
具体实施方式
在下文中将参照其中示出了本公开的示例性实施例的附图来更充分地描述本公开。如本领域技术人员将认识到的，可以在不脱离本公开的精神或范围的情况下以各种不同的方式修改所描述的示例性实施例。
为了本公开的清楚描述，可以省略与描述无关的部分，并且在整个说明书中，同样的附图标记表示同样的元件。
此外，在附图中，为了易于描述，可以任意地示出每个元件的尺寸和厚度，并且本公开不必限于附图中所示的尺度和厚度。在附图中，为了清楚，可以夸大层、膜、面板、区等的厚度。在附图中，为了易于描述，可以格外夸大一些层和区域的厚度。
将理解的是，当诸如层、膜、区或基底的元件被称为“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在一个或更多个中间元件。相反，当元件被称为“直接在”另一元件“上”时，可以不存在中间元件。此外，在说明书中，词语“在……上”或“在……上方”意味着位于对象部分上或下方，并且不一定意味着基于重力方向位于对象部分的上侧或下侧上。
此外，除非明确地相反描述，否则词语“包括”及其诸如“包含”或“含有”的变体将被理解为暗示包括所述元件但不排除任何其它元件。
此外，在整个说明书中，短语“在平面上”或“在平面图中”意味着从顶部观看目标部，短语“在剖面上”或“在剖视图中”意味着观看通过从一侧垂直地切割目标部分所形成的剖面
图1示意性地示出了根据本公开的示例性实施例的显示装置。
参照图1，显示装置包括显示面板300、数据驱动器460、栅极驱动器500和信号控制器600。
显示面板300包括用于显示图像的显示区域DA和围绕显示区域DA的非显示区域NDA。可以从外部接收信号以显示图像的各种元件和布线形成在显示面板300(例如，基底)上。
用于显示图像的多个像素PX以及用于分别将信号施加到像素PX的多条栅极线G1至Gn和多条数据线D1至Dm设置在显示区域DA中。多条栅极线G1至Gn和多条数据线D1至Dm可以彼此绝缘并且在平面图中彼此交叉。此外，用于将驱动电压施加到像素PX的多条驱动电压线PL(例如，图2中所示的驱动电压线172)设置在显示区域DA中。
每个像素PX包括含有开关晶体管和驱动晶体管的至少两个晶体管、至少一个存储电容器以及发光元件(例如，发光二极管)，并且还可以包括至少一个补偿晶体管。后面将详细地描述像素PX。
用于将栅极信号施加到多条栅极线G1至Gn的栅极驱动器500设置在非显示区域NDA中。栅极驱动器500可以集成在非显示区域NDA中的基底上。显示区域DA中的多条数据线D1至Dm中的每条可以从数据驱动器460接收数据信号(即，施加到像素的数据电压)。在一个实施例中，数据驱动器460可以是安装在键合到显示面板300的柔性印刷电路板(FPCB)450上的集成电路(IC)芯片。
栅极驱动器500和数据驱动器460由信号控制器600控制。位于FPCB450外部的印刷电路板(PCB)400可以将信号从信号控制器600传输到数据驱动器460和栅极驱动器500。从信号控制器600提供给栅极驱动器500的信号可以通过设置在显示面板300中的驱动器控制信号线DCL传输到栅极驱动器500。通过驱动器控制信号线DCL从信号控制器600提供给栅极驱动器500的那些信号可以包括垂直起始信号和时钟信号以及用于提供特定电平的低电平的信号。可以从除了信号控制器600之外的外部装置(未示出)提供一些信号。
例如，驱动器控制信号线DCL可以连接到靠近栅极驱动器500设置的FPCB 450，并且可以在栅极驱动器500延伸的方向上延伸。例如，驱动器控制信号线DCL可以与非显示区域NDA中的栅极驱动器500平行地延伸。尽管驱动器控制信号线DCL被示出为单条线以简化图1的制图，但是驱动器控制信号线DCL可以包括与传输到栅极驱动器500的信号的类型对应的多条信号线，或可以包括更多或更少的信号线。驱动器控制信号线DCL的信号线可以与栅极驱动器500平行地设置在比栅极驱动器500距离显示区域DA更远的外部，但是本公开不限于此，并且驱动器控制信号线DCL的一些信号线可以通过栅极驱动器500来设置。
栅极驱动器500可以通过驱动器控制信号线DCL接收垂直起始信号、时钟信号和与栅极截止电压对应的低电压，以生成栅极信号(例如，栅极导通电压和栅极截止电压)，然后，将栅极信号施加到多条栅极线G1至Gn。栅极驱动器500可以包括用于生成和输出栅极信号的多个级ST1至STn。多个级ST1至STn可以连接到多条栅极线G1至Gn中的相应的栅极线，并且多个级ST1至STn可以分别将栅极信号顺序地输出到多条栅极线G1至Gn。然而，本公开不限于此，并且多个级ST1至STn中的一个级可以连接到多条栅极线G1至Gn中的两条栅极线。在这种情况下，每个级可以将栅极信号输出到两条栅极线。在其它实施例中，三条或更多条栅极线可以连接到一个级。
栅极驱动器500可以位于显示区域DA的左侧和/或右侧上，可选地,可以位于显示区域DA的上侧和/或下侧上。当两个栅极驱动器500分别设置在显示面板300的左侧和右侧上时，设置在显示面板300的左侧上的第一栅极驱动器500可以包括奇数级(ST1、ST3、……)并且设置在显示面板300的右侧上的第二栅极驱动器500可以包括偶数级(ST2、ST4、……)，或反之亦然。然而，在一些实施例中，即使两个栅极驱动器500分别设置在显示面板300的左侧和右侧上，两个栅极驱动器500中的每个也可以包括所有级ST1至STn。
多个级ST1至STn中的每个可以包括多个晶体管和至少一个存储电容器。包括在多个级ST1至STn中的每个晶体管的沟道层可以包括氧化物半导体。多个级ST1至STn中的每个可以是大体上矩形的，并且所有级ST1至STn可以具有基本相同的尺寸(面积)。换句话说，显示面板300中的设置有包括在各个级ST1至STn中的多个晶体管和存储电容器的区域的尺寸可以基本相同，并且各个级ST1至STn的区域可以是大体上矩形的。例如，多个级ST1至STn中的每个可以设置有基本相同的矩形区域。在图1中，多个级ST1至STn中的每个被示出为具有相同面积和形状的矩形块。
图2示出了根据图1的显示装置的像素的等效电路图。
参照图2，像素PX连接到多条信号线。
信号线包括用于传输栅极信号的栅极线121、用于传输数据信号的数据线171和用于传输驱动电压ELVDD的驱动电压线172。
栅极线121在基本水平的方向(或行方向)上延伸并且基本彼此平行，数据线171和驱动电压线172在基本竖直方向(或列方向)上延伸并且基本彼此平行。
像素PX包括开关晶体管Trs、驱动晶体管Trd、存储电容器Cst和发光二极管LD。
开关晶体管Trs具有控制端子、输入端子和输出端子，控制端子连接到栅极线121，输入端子连接到数据线171，输出端子连接到驱动晶体管Trd。开关晶体管Trs响应于施加到栅极线121的栅极信号将施加到数据线171的数据信号传输到驱动晶体管Trd。
驱动晶体管Trd也具有控制端子、输入端子和输出端子，控制端子连接到开关晶体管Trs的输出端子，输入端子连接到驱动电压线172，输出端子连接到发光二极管LD。驱动电流Id可以流过驱动晶体管Trd并且使发光二极管LD发光。驱动电流Id可以根据施加在驱动晶体管Trd的控制端子与输出端子之间的电压而变化。
根据一个实施例，开关晶体管Trs和驱动晶体管Trd的沟道层可以包括氧化物半导体。
存储电容器Cst可以连接在驱动晶体管Trd的控制端子与输入端子之间。存储电容器Cst充有与通过开关晶体管Trs施加到驱动晶体管Trd的控制端子的数据信号对应的电压，并且即使在开关晶体管Trs被截止之后也保持所充电压。
发光二极管LD包括连接到驱动晶体管Trd的输出端子的阳极和连接到共电压ELVSS的阴极。发光二极管LD可以根据流过驱动晶体管Trd的输出电流Id而发射具有不同强度的光以显示图像。
在不脱离本公开的范围的情况下，开关晶体管Trs、驱动晶体管Trd、存储电容器Cst和发光二极管LD的连接关系可以不同地被改变。
根据一个实施例，开关晶体管Trs和驱动晶体管Trd具有不同的结构。此外，开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管可以具有相同的结构。将参照图3来描述这样的开关晶体管和/或驱动晶体管的结构。
图3示出了包括在根据图1的显示装置中的晶体管的剖面的示例。
在图3中，“Trs”表示开关晶体管，“Stage Tr”表示包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管。“Trd”表示驱动晶体管。
参照图3，开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr包括开关半导体层120s、开关沟道层130、开关栅电极150s、开关漏电极175s和开关源电极173s。驱动晶体管Trd包括驱动半导体层120d、驱动栅电极150d、驱动漏电极175d和驱动源电极173d。
开关半导体层120s和驱动半导体层120d设置在基底110上。
基底110包括玻璃或塑料。
开关半导体层120s和驱动半导体层120d可以包括氧化物铟镓锌(IGZO)、氧化铟锌(IZO)、氧化铪铟锌(HIZO)和氧化铪锌(HZO)中的至少一种。
驱动半导体层120d包括驱动源区120sd、驱动漏区120dd和驱动中间区120cd。驱动中间区120cd设置在驱动源区120sd与驱动漏区120dd之间。根据一个实施例，驱动中间区120cd可以是未掺杂杂质的氧化物半导体，驱动源区120sd和驱动漏区120dd可以通过后面描述的层间绝缘膜160的氢被制成导体。层间绝缘膜160的氢可以扩散到氧化物半导体中，从而增大载流子的浓度。这里，驱动中间区120cd可以与驱动晶体管Trd的沟道层对应。
开关半导体层120s包括开关源区120ss、开关漏区120ds和开关中间区120cs。开关中间区120cs设置在开关源区120ss与开关漏区120ds之间。根据一个实施例，开关中间区120cs可以是未掺杂杂质的氧化物半导体，开关源区120ss和开关漏区120ds可以通过后面描述的层间绝缘膜160的氢被制成导体。层间绝缘膜160的氢可以扩散到氧化物半导体中，从而增大载流子的浓度。
开关沟道层130设置在开关半导体层120s上并且与开关中间区120cs的至少一部分叠置。在一个实施例中，开关沟道层130的宽度可以小于开关中间区120cs的宽度。在另一实施例中，开关沟道层130的宽度可以与开关中间区120cs的宽度基本相同。开关沟道层130可以是其中未掺杂有杂质的氧化物半导体，并且包括氧化铟锡镓锌(ITGZO)和氧化铟锡锌(ITZO)中的至少一种。开关沟道层130可以与开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层对应。
根据一个实施例，开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层以及驱动晶体管Trd的沟道层由不同的材料制成，并且可以在显示面板300上具有不同的结构和布置。
在一个实施例中，开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层包括含锡的氧化物半导体材料，驱动晶体管Trd的沟道层包括不含锡的氧化物半导体材料。由于材料组成不同，因此开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层的迁移率变得比驱动晶体管Trd的沟道层的迁移率高。
由于包括在多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层的增加的迁移率，因此可以减少包括在多个级ST1至STn中的每个中的晶体管Stage Tr的尺寸以及包括在多个级ST1至STn中的晶体管Stage Tr的数量。因此，可以减小栅极驱动器500的尺寸，从而也减小了非显示区域NDA的宽度。
随着开关晶体管Trs的沟道层的迁移率增加，可以减小施加到开关晶体管Trs的电压/电流的应力。
根据一个实施例，与包括在多个级ST1至STn中的每个中的晶体管Stage Tr的沟道层的迁移率相比，驱动晶体管Trd的沟道层的迁移率可以相对地减小。在这种情况下，可以扩大驱动晶体管Trd的驱动范围。这对于显示具有高分辨率的灰度可以是有利的。
在一些实施例中，开关晶体管Trs和包括在栅极驱动器500的级ST1至STn中的每个中的晶体管Stage Tr的沟道层可以设置在开关半导体层120s上并且与开关中间区120cs的至少一部分叠置。
缓冲层可以设置在基底110与开关半导体层120s之间以及基底110与驱动半导体层120d之间。缓冲层可以包括无机绝缘膜。缓冲层可以用于防止诸如杂质或湿气的不必要的组分渗透，并且同时使基底110的表面平坦。
栅极绝缘膜140可以在与开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr对应的区域中设置在开关沟道层130上，并且在与驱动晶体管Trd对应的区域中与驱动中间区120cd的至少一部分叠置。栅极绝缘膜140可以包括氧化硅(SiOx)和氮化硅(SiNx)中的至少一种。
驱动栅电极150d和开关栅电极150s可以设置在栅极绝缘膜140上。驱动栅电极150d可以与驱动中间区120cd的至少一部分叠置，并且开关栅电极150s可以与开关沟道层130的至少一部分叠置。
层间绝缘膜160可以设置在驱动源区120sd、驱动漏区120dd、开关源区120ss、开关漏区120ds、驱动栅电极150d和开关栅电极150s上。层间绝缘膜160可以包括氮氧化硅(SiOyNx)。在一些实施例中，层间绝缘膜160可以包括氧化硅(SiOx)和氮化硅(SiNx)。层间绝缘膜160在单位面积中具有比栅极绝缘膜140的氢量大的氢量或比栅极绝缘膜140的氢浓度高的氢浓度。
层间绝缘膜160包括第一接触孔161、第二接触孔162、第三接触孔163和第四接触孔164。第一接触孔161与驱动漏区120dd的至少一部分叠置，第二接触孔162与驱动源区120sd的至少一部分叠置。第三接触孔163与开关漏区120ds的至少一部分叠置，第四接触孔164与开关源区120ss的至少一部分叠置。
驱动漏电极175d、驱动源电极173d、开关漏电极175s和开关源电极173s设置在层间绝缘膜160上。驱动漏电极175d通过第一接触孔161连接到驱动漏区120dd。驱动源电极173d通过第二接触孔162连接到驱动源区120sd。开关漏电极175s通过第三接触孔163连接到开关漏区120ds。开关源电极173s通过第四接触孔164连接到开关源区120ss。
在下文中，将参照图4至图13以及图3来描述根据本公开的示例性实施例的显示装置的制造方法。
图4至图13示出了在根据本公开的示例性实施例的显示装置的制造工艺期间的显示装置的剖视图。
在图4至图13中，“Trs”表示开关晶体管，“Stage Tr”表示包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管。“Trd”表示驱动晶体管。
参照图4，在基底100上顺序地形成第一半导体材料层120a和第二半导体材料层130a。
第一半导体材料层120a可以包括氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化铪铟锌(HIZO)和氧化铪锌(HZO)中的至少一种。第二半导体材料层130a可以包括氧化铟锡镓锌(ITGZO)和氧化铟锡锌(ITZO)中的至少一种。
第一半导体材料层120a和第二半导体材料层130a在它们的材料组成上彼此不同。在一个实施例中，第一半导体材料层120a可以包括不含锡的氧化物半导体材料，第二半导体材料层130a可以包括含锡的氧化物半导体材料。
参照图5，在第二半导体材料层130a上形成第一光致抗蚀剂膜50，然后利用掩模200曝光第一光致抗蚀剂膜50。
掩模200包括透明基底210和光阻挡膜220。掩模200还包括光阻挡区A、透射区B和半透射区C。光阻挡区A与设置完全阻挡光的光阻挡膜220的区域对应。透射区B与不存在光阻挡膜220的区域对应，并且光透射过透射区B。半透射区C与间隔设置的多个光阻挡膜220的区域对应，并且透射过半透射区C的光的量小于透射过透射区B的光的量。透射区B可以仅设置在形成开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的区域中。在这种情况下，掩模200也可以称为半色调掩模或狭缝掩模。
参照图6，对第一光致抗蚀剂膜50的曝光部分进行显影，以形成第二光致抗蚀剂膜50s和第三光致抗蚀剂膜50d。第二光致抗蚀剂膜50s设置在形成开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的区域中，第三光致抗蚀剂膜50d设置形成驱动晶体管Trd的区域中。
第二光致抗蚀剂膜50s包括第一部分51和比第一部分51薄的第二部52分。第一部分51通过掩模200的透射区B曝光，第二部分52通过掩模200的半透射区C曝光。第三光致抗蚀剂膜50d的厚度可以与第二光致抗蚀剂膜50s的第二部分52的厚度相等。第三光致抗蚀剂膜50d通过掩模200的半透射区C曝光。
参照图7，执行第一蚀刻工艺以蚀刻第一半导体材料层120a和第二半导体材料层130a。通过蚀刻第一半导体材料层120a形成开关半导体层120s和驱动半导体层120d。开关半导体层120s设置在形成开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的区域中，驱动半导体层120d设置在形成驱动晶体管Trd的区域中。
利用第二光致抗蚀剂膜50s和第三光致抗蚀剂膜50d作为掩模来蚀刻第一半导体材料层120a和第二半导体材料层130a的第一蚀刻工艺可以包括湿蚀刻工艺。
参照图8，通过将第二光致抗蚀剂膜50s和第三光致抗蚀剂膜50d灰化来形成第四光致抗蚀剂膜55s。
当将第二光致抗蚀剂膜50s和第三光致抗蚀剂膜50d灰化时，可以去除第二光致抗蚀剂膜50s的第二部52和第三光致抗蚀剂膜50d，并且第二光致抗蚀剂膜50s的第一部51可以变薄，从而形成第四光致抗蚀剂膜55s。
参照图9，执行第二蚀刻工艺以形成开关沟道层130。开关沟道层130设置在形成开关晶体管Trs和包括在栅极驱动器500的多个级ST1至STn中的每个中的晶体管Stage Tr的区域中。
其中利用第四光致抗蚀剂膜55s作为掩模来蚀刻第二半导体材料层130a的第二蚀刻工艺可以包括干蚀刻工艺。在第二蚀刻工艺中，可以使用诸如SF6、CF4、CHF3、CHF5和C4F8的含有氟(F)的蚀刻气体。蚀刻气体对于含锡的第二半导体材料层130a和不含锡的第一半导体材料层120a具有蚀刻选择性。也就是说，由于含氟的蚀刻气体容易与锡反应，因此可以快速地执行第二半导体材料层130a的第二蚀刻工艺，并且可以蚀刻第二半导体材料层130a的除了第二半导体材料层130a的与第四光致抗蚀剂膜55s叠置的部分之外的部分。
因此，可以通过单个掩模工艺形成开关半导体层120s、驱动半导体层120d和开关沟道层130。因此，可以减少用于制造显示装置的掩模工艺的数量。
参照图10，在去除第四光致抗蚀剂膜55s之后，在基底110、开关半导体层120s、驱动半导体层120d和开关沟道层130上形成栅极绝缘膜材料层140a，然后在栅极绝缘膜材料层140a上形成开关栅电极150s和驱动栅电极150d。栅极绝缘膜材料层140a可以包括氧化硅(SiOx)和氮化硅(SiNx)中的至少一种。开关栅电极150s可以与开关沟道层130的至少一部分叠置，驱动栅电极150d可以与驱动半导体层120d的至少一部分叠置。
参照图11，利用开关栅电极150s和驱动栅电极150d作为掩模来蚀刻栅极绝缘膜材料层140a，以形成栅极绝缘膜140。
参照图12，在开关半导体层120s、驱动半导体层120d、开关栅电极150s和驱动栅电极150d上形成层间绝缘膜160。层间绝缘膜160可以包括氧氮化硅(SiOyNx)。在一些实施例中，层间绝缘膜160可以包括氧化硅(SiOx)和氮化硅(SiNx)。层间绝缘膜160可以在单位面积中具有比栅极绝缘膜140的氢量大的氢量或比栅极绝缘膜140的氢浓度高的氢浓度。
当形成层间绝缘膜160时，可以执行热处理工艺，并且在这种情况下，包括在层间绝缘膜160中的氢(H)可以扩散到开关半导体层120s和驱动半导体层120d中。开关半导体层120s的一部分的载流子浓度由于从层间绝缘膜160扩散的氢而增加，因此开关半导体层120s的扩散有氢的部分可以具有适当用作开关源区120ss和开关漏区120ds的导体的性质。此外，驱动半导体层120d的一部分的载流子浓度由于从层间绝缘膜160扩散的氢而增加，因此驱动半导体层120d的扩散有氢扩散的部分可以具有适合用作驱动源区120sd和驱动漏区120dd的导体的性质。
在完成热处理工艺之后，开关半导体层120s包括开关源区120ss、开关漏区120ds和开关中间区120cs，驱动半导体层120d包括驱动源区120sd、驱动漏区120dd和驱动中间区120cd。
参照图13，在层间绝缘膜160中形成第一接触孔161、第二接触孔162、第三接触孔163和第四接触孔164。第一接触孔161可以与驱动漏区120dd的至少一部分叠置，第二接触孔162可以与驱动源区120sd的至少一部分叠置。第三接触孔163可以与开关漏区120ds的至少一部分叠置，第四接触孔164可以与开关源区120ss的至少一部分叠置。
返回参照图3，在层间绝缘膜160上形成驱动漏电极175d、驱动源电极173d、开关漏电极175s和开关源电极173s。驱动漏电极175d通过第一接触孔161连接到驱动漏区120dd。驱动源电极173d通过第二接触孔162连接到驱动源区120sd。开关漏电极175s通过第三接触孔163连接到开关漏区120ds。开关源电极173s通过第四接触孔164连接到开关源区120ss。
此后，可以形成连接到驱动晶体管Trd的发光二极管LD(见图2)。
另一方面，在不脱离本公开的范围的情况下，可以以不同的方式形成像素的结构。
图14示出了根据本公开的示例性实施例的显示装置的像素的等效电路图。
参照图14，像素PX包括连接到多条信号线的多个晶体管。
晶体管包括驱动晶体管T1、开关晶体管T2、补偿晶体管T3、初始化晶体管T4、操作控制晶体管T5、发光控制晶体管T6和旁路晶体管T7。
信号线包括用于传输扫描信号Sn的栅极线121、用于将前一扫描信号Sn-1传递到初始化晶体管T4的前一栅极线122、用于将发光控制信号EM传输到操作控制晶体管T5和发光控制晶体管T6的发光控制线123、用于将旁路信号BP传输到旁路晶体管T7的旁路控制线128、与栅极线121交叉并且传输数据信号Dm的数据线171、传输驱动电压ELVDD并且形成为与数据线171基本平行的驱动电压线172以及用于传输使驱动晶体管T1初始化的初始化电压Vint的初始化电压线192。
像素PX还包括存储电容器Cst和发光二极管LD。
这里，驱动晶体管T1的结构可以与图3中所示的驱动晶体管Trd的结构相同。开关晶体管T2、补偿晶体管T3、初始化晶体管T4、操作控制晶体管T5、发光控制晶体管T6和旁路晶体管T7的结构可以与图3中所示的开关晶体管Trs的结构相同。
驱动晶体管T1的栅电极G1连接到存储电容器Cst的一端Cst1，驱动晶体管T1的源电极S1经由操作控制晶体管T5连接到驱动电压线172，驱动晶体管T1的漏电极D1经由发光控制晶体管T6电连接到发光二极管LD的阳极。驱动晶体管T1根据开关晶体管T2的开关操作接收数据信号Dm，并且将驱动电流Id供应给发光二极管LD。
开关晶体管T2的栅电极G2连接到栅极线121，开关晶体管T2的源电极S2连接到数据线171，开关晶体管T2的漏电极D2连接到驱动晶体管T1的源电极S1并且也经由操作控制晶体管T5连接到驱动电压线172。开关晶体管T2响应于通过栅极线121传输的扫描信号Sn而导通，以执行开关操作，从而将通过数据线171接收的数据信号Dm传输到驱动晶体管T1的源电极S1。
补偿晶体管T3的栅电极G3连接到栅极线121，补偿晶体管T3的源电极S3连接到驱动晶体管T1的漏电极D1，并且也经由发光控制晶体管T6连接到发光二极管LD的阳极，补偿晶体管T3的漏电极D3连接到初始化晶体管T4的漏电极D4、存储电容器Cst的一端Cst1和驱动晶体管T1的栅电极G1。补偿晶体管T3响应于通过栅极线121传输的扫描信号Sn而导通，以将驱动晶体管T1的栅电极G1和漏电极D1彼此连接，从而二极管连接驱动晶体管T1。
初始化晶体管T4的栅电极G4连接到前一栅极线122，初始化晶体管T4的源电极S4连接到初始化电压线192，初始化晶体管T4的漏电极D4连接到存储电容器Cst的一端Cst1、驱动晶体管T1的栅电极G1和补偿晶体管T3的漏电极D3。初始化晶体管T4响应于通过前一栅极线122接收的前一扫描信号Sn-1而导通，以将初始化电压Vint传输到驱动晶体管T1的栅电极G1，从而执行初始化操作以将驱动晶体管T1的栅电极G1的栅极电压初始化。
操作控制晶体管T5的栅电极G5连接到发光控制线123，操作控制晶体管T5的源电极S5连接到驱动电压线172，操作控制晶体管T5的漏电极D5连接到驱动晶体管T1的源电极S1和开关晶体管T2的漏电极D2。
发光控制晶体管T6的栅电极G6连接到发光控制线123，发光控制晶体管T6的源电极S6连接到驱动晶体管T1的漏电极D1和补偿晶体管T3的源电极S3,发光控制晶体管T6的漏电极D6电连接到发光二极管LD的阳极。操作控制晶体管T5和发光控制晶体管T6响应于通过发光控制线123接收的发光控制信号EM而同时导通，并且驱动电压ELVDD通过驱动晶体管T1的二极管连接被补偿，然后被传输到发光二极管LD。
旁路晶体管T7的栅电极G7连接到旁路控制线128，旁路晶体管T7的源电极S7连接到发光控制晶体管T6的漏电极D6和发光二极管LD的阳极，旁路晶体管T7的漏电极D7连接到初始化电压线192和初始化晶体管T4的源电极S4。在旁路晶体管T7截止的状态下，作为驱动电流Id的一部分的旁路电流Ibp流过旁路晶体管T7。
存储电容器Cst的另一端Cst2连接到驱动电压线172，发光二极管LD的阴极连接到用于传输共电压ELVSS的共电压线741。
虽然已经结合目前被认为是示例性实施例的内容描述了本公开，但是将理解的是，本公开不限于所公开的示例性实施例，而是相反地，本公开旨在覆盖包括在本公开的精神和范围内的各种修改和等同布置。
符号说明：
120a：第一半导体材料层
120d：驱动半导体层 120s：开关半导体层
121：栅极线
120cd：驱动中间区 120cs：开关中间区
120sd：驱动源区 120ss：开关源区
123：发光控制线
120dd：驱动漏区 120ds：开关漏区
130：开关沟道层
130a：第二半导体材料层
150d：驱动栅电极 150s：开关栅电极
171：数据线
175d：驱动漏电极 175s：开关漏电极
172：驱动电压线
173d：驱动源电极 173s：开关源电极
200：掩模

Claims (10)

1.一种显示装置，所述显示装置包括：
基底，包括显示区域和非显示区域；
栅极驱动器，在所述非显示区域中设置在所述基底上，并且包括生成栅极信号并将所述栅极信号输出到所述显示区域的多个级；
开关晶体管和驱动晶体管，在所述显示区域中设置在所述基底上；以及
发光二极管，连接到所述驱动晶体管，
其中，所述多个级中的每个级包括多个晶体管，
其中，所述驱动晶体管的沟道层包括第一氧化物半导体材料，包括在所述多个级中的每个级中的所述多个晶体管的沟道层包括第二氧化物半导体材料，
其中，所述第一氧化物半导体材料与所述第二氧化物半导体材料不同，并且
其中，所述第二氧化物半导体材料包括锡。
2.根据权利要求1所述的显示装置，其中，包括在所述多个级中的每个级中的所述多个晶体管的所述沟道层以及所述驱动晶体管的所述沟道层设置在不同的层上，并且
其中，所述开关晶体管的沟道层以及包括在所述多个级中的每个级中的所述多个晶体管的所述沟道层设置在同一层上。
3.根据权利要求2所述的显示装置，其中，包括在所述多个级中的每个级中的所述多个晶体管中的每个晶体管和所述开关晶体管包括：
开关半导体层，设置在所述基底上，并且包括开关源区、开关漏区和设置在所述开关源区与所述开关漏区之间的开关中间区；
开关沟道层，设置在所述开关半导体层上；
栅极绝缘膜，设置在所述开关沟道层上；
开关栅电极，设置在所述栅极绝缘膜上并且与所述开关沟道层的至少一部分叠置；
开关源电极，连接到所述开关源区；以及
开关漏电极，连接到所述开关漏区，
其中，所述开关沟道层与所述开关半导体层的所述开关中间区的至少一部分叠置，并且
其中，包括在所述多个级中的所述多个晶体管的所述沟道层和所述开关晶体管的所述沟道层中的每个包括所述开关沟道层。
4.根据权利要求3所述的显示装置，其中，所述驱动晶体管包括：
驱动半导体层，设置在所述基底上，并且包括驱动源区、驱动漏区和设置在所述驱动源区与所述驱动漏区之间的驱动中间区；
栅极绝缘膜，设置在所述驱动中间区上；
驱动栅电极，设置在所述栅极绝缘膜上并且与所述驱动中间区的至少一部分叠置；
驱动源电极，连接到所述驱动源区；以及
驱动漏电极，连接到所述驱动漏区，并且
其中，所述驱动晶体管的所述沟道层包括所述驱动中间区。
5.根据权利要求4所述的显示装置，其中，所述开关晶体管的所述沟道层包括所述第二氧化物半导体材料，并且
其中，所述开关中间区和所述驱动中间区包括相同的材料。
6.一种制造显示装置的方法，其中，所述显示装置包括：基底，包括显示区域和非显示区域；栅极驱动器，在所述非显示区域中设置在所述基底上，并且包括生成栅极信号并将所述栅极信号输出到所述显示区域的多个级；开关晶体管和驱动晶体管，在所述显示区域中设置在所述基底上；发光二极管，连接到所述驱动晶体管；
其中，所述方法包括：
在所述基底上顺序地形成第一半导体材料层和第二半导体材料层；
通过蚀刻所述第一半导体材料层形成开关半导体层和驱动半导体层；
通过蚀刻所述第二半导体材料层形成与所述开关半导体层的至少一部分叠置的开关沟道层；
在所述基底、所述开关半导体层、所述驱动半导体层和所述开关沟道层上形成栅极绝缘膜材料层；
在所述栅极绝缘膜材料层上形成与所述开关沟道层的至少一部分叠置的开关栅电极以及与所述驱动半导体层的至少一部分叠置的驱动栅电极；
通过利用所述开关栅电极和所述驱动栅电极作为掩模蚀刻所述栅极绝缘膜材料层来形成栅极绝缘膜；
在所述开关半导体层、所述驱动半导体层、所述开关栅电极和所述驱动栅电极上形成层间绝缘膜；
在所述层间绝缘膜上形成开关源电极、开关漏电极、驱动源电极和驱动漏电极；以及
形成连接到所述驱动漏电极的发光二极管，
其中，所述第一半导体材料层包括第一氧化物半导体材料，所述第二半导体材料层包括第二氧化物半导体材料，
其中，所述第一氧化物半导体材料与所述第二氧化物半导体材料不同，并且
其中，所述第二半导体材料层包括锡。
7.根据权利要求6的所述方法，其中，
所述形成所述开关半导体层和所述驱动半导体层的步骤以及所述形成所述开关沟道层的步骤包括：
在所述第二半导体材料层上形成第一光致抗蚀剂膜；
通过利用第一掩模对所述第一光致抗蚀剂膜进行曝光和显影来形成第二光致抗蚀剂膜和第三光致抗蚀剂膜；
通过第一蚀刻工艺对所述第一半导体材料层和所述第二半导体材料层进行蚀刻；
通过将所述第二光致抗蚀剂膜和所述第三光致抗蚀剂膜灰化来形成第四光致抗蚀剂膜；
通过第二蚀刻工艺对所述第二半导体材料层进行蚀刻；以及
去除所述第四光致抗蚀剂膜，并且
其中，所述第一掩模包括光阻挡区、透射区和半透射区。
8.根据权利要求7所述的方法，其中，所述第一蚀刻工艺包括利用所述第二光致抗蚀剂膜和所述第三光致抗蚀剂膜作为掩模来对所述第一半导体材料层和所述第二半导体材料层进行蚀刻，
其中，通过蚀刻所述第一半导体材料层来形成所述开关半导体层和所述驱动半导体层，并且
其中，在所述第二蚀刻工艺中，利用所述第四光致抗蚀剂膜作为第二掩模来对所述第二半导体材料层进行蚀刻，以形成所述开关沟道层。
9.根据权利要求8所述的方法，其中，在所述形成所述第四光致抗蚀剂膜的步骤中，去除所述第三光致抗蚀剂膜，并且去除所述第二光致抗蚀剂膜的一部分。
10.根据权利要求9所述的方法，其中，所述形成所述层间绝缘膜的步骤包括：
执行热处理以使所述层间绝缘膜的氢扩散到所述开关半导体层和所述驱动半导体层中。
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Publication number Priority date Publication date Assignee Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859710A (zh) * 2009-04-10 2010-10-13 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
CN104282259A (zh) * 2013-07-12 2015-01-14 三星显示有限公司 有机发光二极管显示器
CN105989804A (zh) * 2015-03-23 2016-10-05 三星显示有限公司 有机发光二极管显示器及其制造方法
CN107564949A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 氧化物tft、其制造方法、使用其的显示面板和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2172977A1 (en) 2008-10-03 2010-04-07 Semiconductor Energy Laboratory Co., Ltd. Display device
JP5806043B2 (ja) 2010-08-27 2015-11-10 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR102225594B1 (ko) 2013-09-12 2021-03-09 삼성디스플레이 주식회사 박막 트랜지스터 및 그 제조 방법
US9214508B2 (en) * 2014-02-24 2015-12-15 Lg Display Co., Ltd. Thin film transistor substrate with intermediate insulating layer and display using the same
US9490276B2 (en) * 2014-02-25 2016-11-08 Lg Display Co., Ltd. Display backplane and method of fabricating the same
KR102157689B1 (ko) 2014-06-27 2020-09-21 엘지디스플레이 주식회사 평판 표시장치용 박막 트랜지스터 어레이 기판
KR102640164B1 (ko) 2016-05-09 2024-02-23 삼성디스플레이 주식회사 박막 트랜지스터 표시판
KR102543639B1 (ko) * 2016-07-18 2023-06-15 삼성디스플레이 주식회사 표시 패널, 이의 제조 방법 및 이를 구비하는 표시 장치
KR20180013577A (ko) * 2016-07-29 2018-02-07 엘지디스플레이 주식회사 투명표시장치와 그의 제조방법
KR20180071538A (ko) * 2016-12-20 2018-06-28 엘지디스플레이 주식회사 표시 장치용 기판과 그를 포함하는 표시 장치
KR102376490B1 (ko) * 2017-03-29 2022-03-18 삼성디스플레이 주식회사 표시 장치
KR102565907B1 (ko) * 2017-12-27 2023-08-09 엘지디스플레이 주식회사 표시장치 및 전계발광 표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859710A (zh) * 2009-04-10 2010-10-13 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法
CN104282259A (zh) * 2013-07-12 2015-01-14 三星显示有限公司 有机发光二极管显示器
CN105989804A (zh) * 2015-03-23 2016-10-05 三星显示有限公司 有机发光二极管显示器及其制造方法
CN107564949A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 氧化物tft、其制造方法、使用其的显示面板和显示装置

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