CN110890341A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN110890341A CN110890341A CN201910115198.0A CN201910115198A CN110890341A CN 110890341 A CN110890341 A CN 110890341A CN 201910115198 A CN201910115198 A CN 201910115198A CN 110890341 A CN110890341 A CN 110890341A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000001681 protective effect Effects 0.000 claims description 13
- 239000010410 layer Substances 0.000 claims 2
- 239000011229 interlayer Substances 0.000 claims 1
- 230000015654 memory Effects 0.000 description 34
- 230000006870 function Effects 0.000 description 23
- 238000010586 diagram Methods 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
实施方式提供一种较好运行的半导体装置。实施方式的半导体装置具备:半导体衬底;多个第1焊垫电极,设置于半导体衬底;多条第1配线,与多个第1焊垫电极分别电气连接;第1电极,与多条第1配线共通连接;第2焊垫电极,设置于半导体衬底;及第1电阻部与第1保护元件,串联连接于第1电极与第2焊垫电极之间。
Description
[相关申请]
本申请享受以日本专利申请2018-168455号(申请日:2018年9月10日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置。
背景技术
高速运行的半导体装置受到期待。
发明内容
实施方式提供一种较好运行的半导体装置。
实施方式的半导体装置具备:半导体衬底;多个第1焊垫电极,设置于半导体衬底;多条第1配线,与多个第1焊垫电极分别电气连接;第1电极,与多条第1配线共通连接;第2焊垫电极,设置于半导体衬底;及第1电阻部与第1保护元件,串联连接于第1电极与第2焊垫电极之间。
附图说明
图1是第1实施方式的半导体装置的示意框图。
图2是该半导体装置的示意侧视图。
图3是该半导体装置的示意俯视图。
图4是第1实施方式的保护电路的电路示意图。
图5是比较例的保护电路的电路示意图。
图6是表示保护电路的信号的波形示意图。
图7是表示保护电路的信号的波形示意图。
图8是表示保护电路的信号的波形示意图。
图9是第1构成例的半导体装置的示意剖视图。
图10是该半导体装置的示意俯视图。
图11是第2构成例的半导体装置的示意剖视图。
图12是该半导体装置的示意俯视图。
图13是第3构成例的半导体装置的示意剖视图。
图14是该半导体装置的示意俯视图。
图15是第4构成例的半导体装置的示意剖视图。
图16是该半导体装置的示意俯视图。
图17是第5构成例的半导体装置的示意剖视图。
图18是该半导体装置的示意俯视图。
图19是第6构成例的半导体装置的示意剖视图。
图20是该半导体装置的示意俯视图。
图21是第7构成例的半导体装置的示意俯视图。
图22是第8构成例的半导体装置的示意俯视图。
图23是第2实施方式的半导体装置的示意俯视图。
图24是表示可变电阻元件VR的构成的示意图。
具体实施方式
接下来,参照附图,对实施方式的半导体装置详细地进行说明。此外,以下实施方式终归只不过是一个例子,而并非要限定本发明。
另外,在本说明书中,“上”或“下”等表达是以衬底为基准的。例如,在将与衬底的表面交叉的方向设定为第1方向的情况下,将沿着该第1方向离开衬底的方向称作“上”,将靠近衬底的方向称作“下”。另外,在关于某构成而提到下表面或下端部的情况下,意指该构成的衬底侧的面或端部,在提到上表面或上端部的情况下,意指该构成的与衬底为相反侧的面或端部。另外,在将与第1方向交叉的方向设定为第2方向的情况下,将与第2方向交叉的面称作“侧面”等。
[第1实施方式]
[整体构成]
图1是第1实施方式的半导体装置的功能示意框图。为了便于说明,图1中省略了一部分构成。
第1实施方式的半导体装置具备多个存储器芯片MC、及与这些存储器芯片MC进行数据(用户数据、地址数据、指令数据等)的收发的处理器芯片PC。存储器芯片MC分别具备多个焊垫电极P。存储器芯片MC经由这多个焊垫电极P与处理器芯片PC进行数据的收发。
存储器芯片MC具备存储单元阵列1、及控制该存储单元阵列1的周边电路。该周边电路具备列控制电路2、行控制电路3、电压产生电路4、状态机5、数据输入输出缓冲器6及指令接口7。
存储单元阵列1具备记录用户数据的多个存储单元、以及与多个存储单元连接的位线及字线。
列控制电路2经由位线将用户数据读出并发送至数据寄存器,或根据从数据寄存器接收到的用户数据向位线输送电压。
行控制电路3根据从地址寄存器接收到的地址数据向字线输送指定电压。
电压产生电路4将经由焊垫电极P供给来的电压降压或升压,然后输送至列控制电路2及行控制电路3。
状态机5对从指令寄存器接收到的指令数据依次进行解码,然后将内部控制信号发送至列控制电路2、行控制电路3及电压产生电路4。
数据输入输出缓冲器6经由多个焊垫电极P同时接收多比特数据,并将该数据输送至寄存器。另外,数据输入输出缓冲器6经由多个焊垫电极P同时输出寄存器内的多比特数据,并将该数据发送至处理器芯片PC。
指令接口7经由焊垫电极P接收外部控制信号,并根据该外部控制信号控制数据输入输出缓冲器6。
图2是表示本实施方式的半导体装置的构成例的示意侧视图。图3是表示该构成例的示意俯视图。为了便于说明,图2及图3中省略了一部分构成。
如图2所示,本实施方式的半导体装置具备安装衬底MS、积层于安装衬底MS的多个存储器芯片MC、及积层于存储器芯片MC的处理器芯片PC。这些构成是以使形成于上表面的焊垫电极P露出的方式在Y方向上错开而积层,并经由黏接剂等相互连接的。
如图3所示,安装衬底MS、多个存储器芯片MC及处理器芯片PC分别具备多个焊垫电极P。设置于安装衬底MS、多个存储器芯片MC及处理器芯片PC的多个焊垫电极P分别经由接合线B相互连接。
[保护电路]
在存储器芯片MC中蓄存的电荷量与测试装置等中蓄存的电荷量的差较大的情况下,会发生静电放电(ESD:Electro-Static Discharge),而导致焊垫电极P上流通大电流。静电放电包括例如带电器件模型(CDM:Charged Device Model)、机器模型(MM:MachineModel)、人体模型(HBM:Human Body Model)等。
本实施方式的半导体装置具备保护电路,以免这样的静电放电对半导体装置的内部电路(图1的存储单元阵列1等)造成损伤。
图4是表示本实施方式的保护电路的构成的电路示意图。图4中省略了一部分构成。
本实施方式的保护电路具备多个焊垫电极PIO、与这多个焊垫电极PIO分别连接的多条配线W1、与这多条配线W1共通连接的共通电极E1、与该共通电极E1连接的电阻部R1、经由配线W2与电阻部R1连接的保护元件D1、及与该保护元件D1连接的焊垫电极PVSS。另外,该保护电路具备与多个焊垫电极PIO分别连接的多条配线W3、与这多条配线W3共通连接的共通电极E2、与该共通电极E2连接的电阻部R2、经由配线W4与电阻部R2连接的保护元件D2、及与该保护元件D2连接的焊垫电极PVCCQ。
焊垫电极PIO是用于数据收发的焊垫电极P。焊垫电极PIO分别与数据输入输出缓冲器6内的反相器61连接。焊垫电极PVSS、PVCCQ是用于电压供给的焊垫电极P。对焊垫电极PVSS供给电压VSS(例如,0.0V左右)。对焊垫电极PVCCQ供给大于电压VSS的电压VCCQ(例如,1.8V左右)。
多条配线W1的阻抗大体一致。另外,多条配线W2的阻抗也大体一致。例如,在多条配线W1的阻抗的2位有效数字一致的情况下,这些阻抗充分地大体一致。此外,图中的R0是以示意的方式表示与多个焊垫电极PIO连接的各配线具有内部电阻。
保护元件D1、D2例如为二极管等非线性元件。保护元件D1是以电流从焊垫电极PVSS流向焊垫电极PIO的方向为整流方向。保护元件D2是以电流从焊垫电极PIO流向焊垫电极PVCCQ的方向为整流方向。
接下来,继续参照图4,对保护电路的动作进行说明。
在利用存储器芯片MC进行数据的收发时,对多个焊垫电极PIO供给与数据“0”对应的电压、或与数据“1”对应的电压。该电压例如设定于电压VSS以上电压VCCQ以下的范围内。由此,数据输入输出缓冲器6内的反相器61受到驱动,数据的输入得以进行。
此外,这时,对保护元件D1、D2基本上施加反向电压。因此,保护元件D1、D2中不流通电流。另外,配线W1、W3中的阻抗相较于焊垫电极PIO与反相器61之间的配线中的阻抗来说大得多。
在发生了所述静电释放的情况下,保护元件D1、D2中流通电流。另外,由于该电流,电阻部R1、R2断线。由此,共通电极E1、E2与保护元件D1、D2电气分离。
[比较例]
图5是表示比较例的保护电路的构成的电路示意图。图5中省略了一部分构成。
比较例的保护电路具备多个焊垫电极PIO、与这多个焊垫电极PIO分别连接的多个电阻部R1、与这多个电阻部R1分别连接的多个保护元件D1、及与这多个保护元件D1连接的多个焊垫电极PVSS。另外,该保护电路具备与多个焊垫电极PIO分别连接的多个电阻部R2、与这多个电阻部R2分别连接的多个保护元件D2、及与这多个保护元件D2分别连接的多个焊垫电极PVCCQ。
在这种结构中,发生了所述静电释放的情况下,一个或多个电阻部R1、R2断线,与之对应的焊垫电极PIO与保护元件D1、D2电气分离。
[第1实施方式的效果]
图6~图8是表示多个焊垫电极PIO的信号波形的波形示意图。横轴表示时间t,纵轴表示电压V的大小。此外,图6~图8中表示出了向多个焊垫电极PIO全部输入数据“0”或“1”的例子。
图6表示在第1实施方式或比较例的半导体装置中,电阻部R1、R2未断线的情况下的信号波形。如图6所示,若在时刻t1向焊垫电极PIO输入信号,则多个焊垫电极PIO的电压出现峰值的时刻与由时刻t2~t3所表示的期间T1一致。在该期间T1,利用数据输入输出缓冲器6进行数据的获取。
图7表示在比较例的半导体装置中,多个电阻部R1、R2中的任一者断线的情况下的信号波形。信号s1、s2是与未断线的电阻部R1、R2连接的焊垫电极PIO的信号。信号s3是与断线的电阻部R1、R2连接的焊垫电极PIO的信号。
在图示的例子中,信号s1、s2在期间T1内达到最大值。因此,与信号s1、s2对应的数据被正常获取。
另一方面,由于与信号s3对应的焊垫电极PIO和保护元件D1、D2电气分离,所以比起与信号s1、s2对应的焊垫电极,其保护元件D1、D2这一部分的静电电容变少(参照图5)。因此,信号s3达到峰值的时刻会与信号s1、s2达到峰值的期间T1不一致。这种情况下,与信号s3对应的数据会不被正常获取。
图8表示在第1实施方式的保护电路中,电阻部R1、R2中的任一者断线的情况下的信号波形。
在第1实施方式的保护电路中,若电阻部R1、R2断线,则共通电极E1、E2与保护元件D1、D2电气分离(参照图4)。这里,共通电极E1、E2与多个焊垫电极PIO共通连接。因此,在共通电极E1、E2与保护元件D1、D2电气分离的情况下,这多个焊垫电极PIO的静电电容大体一样地变化。从而,若调整数据获取开始的时刻t2′及数据获取结束的时刻t3′而在期间T1内获取数据,则能够正常获取所有信号的数据。由此,能够提供较好运行的半导体装置。
[构成例]
本实施方式的半导体装置可以通过各种态样来实现。以下,参照图9~图22,对本实施方式的半导体装置的构成例进行说明。
[第1构成例]
图9是用来说明第1构成例的示意剖视图。此外,图9是说明用示意附图,与实际的结构不一致。图9中省略了一部分构成。
第1构成例的半导体装置具备半导体衬底100、设置于半导体衬底100上的存储单元阵列1、及配设于半导体衬底100上方的配线层110、120、130、140。
存储单元阵列1具备沿着Z方向配设的多条字线WL、贯通多条字线WL沿着Z方向延伸的多个存储器结构MP、设置于存储器结构MP上方的位线BL、及将存储器结构MP与位线BL电气连接的接点部件C1、C2。字线WL例如为氮化钛(TiN)及钨(W)的积层膜。存储器结构MP例如为包含氧化硅(SiO2)、氮化硅(Si3N4)、氧化硅及多晶硅(Si)的积层膜的大体圆柱状的结构。
半导体衬底100具备工作区域101及氧化硅(SiO2)等绝缘区域102。工作区域101是含有磷(P)或硼(B)等杂质的区域,作为N型半导体或P型半导体发挥作用。另外,在半导体衬底100上,设置有栅极绝缘膜103及栅极电极104。栅极绝缘膜103为氧化硅等绝缘膜。栅极电极104例如包含含有磷(P)等杂质的多晶硅、氮化钛(TiN)及钨(W)等的积层膜。
在半导体衬底100上,设置有包含工作区域101、栅极绝缘膜103及栅极电极104的电场效应型晶体管等多个元件。这些元件作为发挥周边电路作用的CMOS(ComplimentaryMetal Oxide Semiconductor,互补金氧半导体)电路的一部分发挥作用。此外,图9中例示出了保护元件D1。保护元件D1是具备工作区域101的一部分、栅极绝缘膜103及栅极电极104的电场效应型晶体管。该晶体管的栅极电极104与漏极区域电气连接,其作为双端子非线性元件发挥作用。
配线层110、120、130、140分别包含多个配线部件111、121、131、141。另外,在这些配线部件111、121、131、141的下表面,连接有沿着Z方向延伸的接点部件112、122、132、142。接点部件112的下端与工作区域101或栅极电极104连接。接点部件122、132、142的下端与配线部件111、121、131的上表面连接。此外,配线层110、120内的各构成例如包含氮化钛及钨的积层膜等。另外,配线层130内的各构成例如包含氮化钛及铜(Cu)的积层膜等。另外,配线层130内的各构成例如包含氮化钛及铝(Al)的积层膜等。
此外,在图示的例子中,配线层140内的配线部件141a作为焊垫电极PIO、配线W1、共通电极E1、电阻部R1及配线W2的一部分发挥作用。另外,配线部件141a经由多个配线部件111、121、131及多个接点部件112、122、132、142与保护元件D1的源极区域(工作区域101)连接。设置于配线部件141a与工作区域101之间的这些构成作为配线W2的一部分发挥作用。
图10是表示半导体装置的构成例的示意俯视图。在图示的例子中,配线层140具备所述配线部件141a、作为焊垫电极PVSS发挥作用的配线部件141b、及作为焊垫电极PVCCQ发挥作用的配线部件141c。
配线部件141a作为多个焊垫电极PIO、与这多个焊垫电极PIO连接的多条配线W1、与这多条配线W1共通连接的共通电极E1、与该共通电极E1连接的电阻部R1、及与该电阻部R1连接的配线W2的一部分发挥作用。另外,配线部件141a作为与多个焊垫电极PIO连接的多条配线W3、与这多条配线W3共通连接的共通电极E2、与该共通电极E2连接的电阻部R2、及与该电阻部R2连接的配线W4的一部分发挥作用。
此外,在以下说明中,有时会将配线部件或接点部件中作为配线W1等发挥作用的部分简称作“配线W1”等。
配线W1的配线宽度及配线长度全部大体一致。也就是说,与多个焊垫电极PIO中距离共通电极E1最远的那一个连接的配线W11包含1个沿着Y方向延伸的直线部分W11Y、1个沿着X方向延伸的直线部分W11X、及1个将延伸方向不同的直线部分W11Y、W11X连接的连接部分W11C。另一方面,与多个焊垫电极PIO中距离共通电极E1最近的那一个连接的配线W12包含3个直线部分W12Y、3个直线部分W12X、及5个连接部分W12C。这里,例如,在将配线W11的配线长度设定为第1配线长度,将配线W12的配线长度设定为第2配线长度的情况下,第1配线长度与第2配线长度大体一致。此外,第1配线长度例如为配线W11中包含的直线部分W11Y的Y方向的长度与直线部分W11X的X方向的长度的和。另外,第2配线长度例如为配线W12中包含的3个直线部分W12Y各自的Y方向的长度与3个直线部分W12X各自的X方向的长度的总和。另外,例如,在直线部分的合计长度的2位有效数字一致的情况下,这些配线长度充分地大体一致。多条配线W3是与多条配线W1大体同样地构成。由此,能够使高速信号传输中的配线W1的特性阻抗在所有焊垫电极PIO中都一致。
电阻部R1具备与共通电极E1连接的第1部分R11、与第1部分R11连接的第2部分R12、及与第2部分R12连接的第3部分R13。第2部分R12的配线宽度小于第1部分R11的配线宽度及第3部分R13的配线宽度。此外,第3部分R13经由配线W2与保护元件D1连接。电阻部R2与电阻部R1大体同样地构成,且经由配线W4与保护元件D2连接。
这里,在第1构成例中,多个焊垫电极PIO、焊垫电极PVSS及焊垫电极PVCCQ沿着X方向排成一列。这里,如参照图2所说明的那样,多个存储器芯片MC是以使形成于上表面的焊垫电极P露出的方式在Y方向上错开而积层。因此,在多个焊垫电极PIO、焊垫电极PVSS及焊垫电极PVCCQ排成一列的情况下,能够使多个存储器芯片MC在Y方向上不错开得较大而积层。
[其他构成例]
第1构成例终归只不过是一种例示,具体的构成可以适当变更。
例如,在第1构成例中,仅配线层140内的配线部件141a作为配线W1、W3发挥作用。然而,也可以为其他配线层110、120、130内的构成作为配线W1、W3的一部分发挥作用。
例如,图11及图12中表示出了配线层130内的配线部件131d、配线层140内的配线部件141d、及与它们连接的多个接点部件作为配线W1、W3发挥作用的例子。另外,图13及图14中表示出了配线层120内的配线部件121e、配线层130内的配线部件131e、配线层140内的配线部件141d、及与它们连接的多个接点部件作为配线W1、W3发挥作用的例子。另外,图15及图16中表示出了配线层110内的配线部件111f、配线层120内的配线部件121f、配线层130内的配线部件131e、配线层140内的配线部件141d、及与它们连接的多个接点部件作为配线W1、W3发挥作用的例子。
另外,在以上构成例中,配线W1、W3具备大体相同的结构,由相同配线层中包含的配线部件等构成。然而,作为配线W1、W3发挥作用的配线部件等也可以由不同配线层中包含的配线部件等构成。
例如,图17及图18中表示出了配线层140内的配线部件141g作为焊垫电极PIO、配线W3、共通电极E2、电阻部R2及配线W4的一部分发挥作用,配线层130内的配线部件131g作为配线W1、共通电极E1、电阻部R1及配线W2的一部分发挥作用的例子。此外,配线部件141g与配线部件131g在XY平面上具有大体相同的形状。根据这种构成,能够使焊垫电极PIO、PVSS、PVCCQ接近存储器芯片MC的Y方向的端部。因此,能够使存储器芯片MC在Y方向上不错开得较大而积层(参照图2)。另外,能够削减保护电路的面积。
另外,在以上构成例中,是配线层110、120、130、140内的配线部件作为电阻部R1、R2发挥作用,但也可以不是配线部件而是接点部件作为电阻部R1、R2发挥作用。
例如,图19中表示出了接点部件132a作为电阻部R1发挥作用的例子。在图19的例子中,配线部件141h经由多个接点部件142a与配线部件131h连接。配线部件141h的一部分、多个接点部件142a及配线部件131h作为共通电极E1的一部分发挥作用。另外,在图19的例子中,配线部件131h经由1个接点部件132a与配线部件121h连接。接点部件132a作为电阻部R1发挥作用。另外,在图19的例子中,配线部件121h经由多个接点部件122a与配线部件111h连接,配线部件111h经由多个接点部件112a与保护元件D1(工作区域101)连接。这些配线部件121h、111h及接点部件122a、112a作为配线W2发挥作用。根据这种构成,就像图20所例示的那样,无需在配线部件141h设置电阻部R1、R2及配线W2、W4,因此能够削减保护电路的面积。
另外,在以上构成例中,配线层140内的作为焊垫电极PIO发挥作用的部分是沿着X方向排成一列。然而,作为焊垫电极发挥作用的部分也可以排成两列或两列以上的多列,或者呈所述图案以外的图案排列。
例如,图21中表示出了多个焊垫电极PIO沿着圆c1以相等间隔排列的例子。在圆c1的中心位置,配置共通电极E1,将它们连接的配线W1呈放射状延伸。此外,图中的点p1表示各焊垫电极PIO的中心点。
另外,在以上构成例中,作为配线W1、W2发挥作用的配线部件的配线宽度及配线长度大体相同,因此配线W1、W2的阻抗大体相同。然而,例如也可以使作为配线W1、W2发挥作用的配线部件的配线宽度与配线长度的比大体相同,由此使配线W1、W2的阻抗大体相同。
例如,图22中表示出了所具有的配线宽度像与距离共通电极E1、E2较远的焊垫电极PIO连接的配线W1那样大的例子。
[第2实施方式]
接下来,参照图23及图24,对第2实施方式的半导体装置进行说明。
第2实施方式的半导体装置基本上是与第1实施方式的半导体装置同样地构成。但是,在第2实施方式中,多个焊垫电极PIO与共通电极E1、E2之间设置有可变电阻元件VR。
也就是说,在第1实施方式中,是利用配线层110、120、130、140内的构成的配线电阻等,使配线W1、W2的阻抗大体相同。然而,在第2实施方式中,是通过调整可变电阻元件VR的阻抗,使焊垫电极PIO与共通电极E1、E2之间的阻抗大体相同。
图24是表示可变电阻元件VR的构成例的示意图。可变电阻元件VR具备输入端子n1、与输入端子n1连接的配线部件150、与配线部件150连接的多个晶体管Tr1~Tr5、及与多个晶体管Tr1~Tr5共通连接的输出端子n2。
配线部件150具备沿着Y方向配设且沿着X方向延伸的多个直线部分151、及与它们连接的连接部分152。多个直线部分151经由多个连接部分152串联连接。此外,配线部件150也可以为设置于配线层110、120、130、140内的配线部件中的一个。另外,也可以将多个栅极电极104中的一部分用作配线部件150。
晶体管Tr1经由1个直线部分151与输入端子n1连接。晶体管Tr2经由2个直线部分151与输入端子n1连接。以下,同样地,晶体管Tr3~Tr5经由3~5个直线部分151与输入端子n1连接。
[其他实施方式]
第1及第2实施方式是作为例子而提出的,具体的构成等可以适当变更。
例如,在第1实施方式中,如图1等所例示的那样,作为半导体装置的内部电路,例示的是存储单元阵列1。然而,内部电路也可以为例如运算处理电路等存储单元阵列以外的构成。另外,存储单元阵列的构成也可以适当变更。例如,第1实施方式的存储单元阵列1具备三维型NAND闪速存储器。然而,存储单元阵列也可以具备例如二维型NAND闪速存储器,或可以具备NOR闪速存储器。另外,存储单元阵列也可以具备DRAM(Dynamic Random AccessMemory,动态随机存取存储器)、ReRAM(Resistive Random Access Memory,电阻式随机存取存储器)、MRAM(Magnetoresistive Random Access Memory,磁阻式随机存取存储器)、PCRAM(Phase Change Random Access Memory,相变随机存取存储器)等闪速存储器以外的存储器。
另外,在第1实施方式中,如图2及图3所例示的那样,是通过接合线B进行各芯片间的连接。然而,各芯片间的连接也可以通过例如所谓的硅贯通电极(TSV:Through SiliconVia)等来进行。
另外,在第1实施方式中,如图4所例示的那样,共通电极E1与配线W2之间设置有电阻部R1,配线W2与焊垫电极PVSS之间设置有保护元件D1。另外,共通电极E2与配线W4之间设置有电阻部R2,配线W4与焊垫电极PVCCQ之间设置有保护元件D2。然而,也可以为共通电极E1与配线W2之间设置有保护元件D1,配线W2与焊垫电极PVSS之间设置有电阻部R1。同样地,也可以为共通电极E2与配线W4之间设置有保护元件D2,配线W4与焊垫电极PVCCQ之间设置有电阻部R2。
Claims (10)
1.一种半导体装置,其具备:
半导体衬底;
多个第1焊垫电极,设置于所述半导体衬底;
多条第1配线,与所述多个第1焊垫电极分别电气连接;
第1电极,与所述多条第1配线共通连接;
第2焊垫电极,设置于所述半导体衬底;及
第1电阻部与第1保护元件,串联连接于所述第1电极与所述第2焊垫电极之间。
2.根据权利要求1所述的半导体装置,其具备:
多条第2配线,与所述多个第1焊垫电极分别电气连接;
第2电极,与所述多条第2配线共通连接;
第3焊垫电极,设置于所述半导体衬底;及
第2电阻部与第2保护元件,串联连接于所述第2电极与所述第3焊垫电极之间。
3.根据权利要求2所述的半导体装置,其中
所述多条第1配线各者的阻抗、或所述多条第2配线各者的阻抗中,至少某一种阻抗大体一致。
4.根据权利要求2所述的半导体装置,其
具备一个或多个配线层,且
所述一个或多个配线层包含作为所述多个第1焊垫电极、所述多条第1配线、所述第1电极、所述多条第2配线、所述第2电极、所述第2焊垫电极、所述第3焊垫电极、所述第1电阻部、所述第2电阻部、所述第1保护元件及所述第2保护元件中的至少一者发挥作用的配线部件及接点部件中的至少一者。
5.根据权利要求2所述的半导体装置,其
具备含有工作区域的半导体衬底,且
所述第1保护元件具有所述半导体衬底的工作区域的一部分、设置于所述工作区域的一部分的第1绝缘膜、及设置于所述第1绝缘膜的第1下部电极,
所述第2保护元件具有所述半导体衬底的工作区域的一部分、设置于所述工作区域的一部分的第2绝缘膜、及设置于所述第2绝缘膜的第2下部电极。
6.根据权利要求2所述的半导体装置,其中
所述多个第1焊垫电极、所述第2焊垫电极及所述第3焊垫电极沿着第1方向排列,且
所述多条第1配线中的至少一者具有:多个第1延伸部,沿着所述第1方向延伸;及多个第2延伸部,沿着与所述第1方向交叉且位于所述半导体衬底的面内的第2方向延伸;
所述多条第2配线中的至少一者具有:多个第3延伸部,沿着所述第1方向延伸;及多个第4延伸部,沿着与所述第1方向交叉且位于所述半导体衬底的面内的第2方向延伸。
7.根据权利要求2所述的半导体装置,其中
所述第1电阻部具有:
第1部分,与所述第1电极连接;
第2部分,与所述第1部分连接;及
第3部分,与所述第2部分连接;且
所述第2部分的配线宽度小于所述第1部分及所述第3部分的配线宽度,
所述第2电阻部具有:
第4部分,与所述第2电极连接;
第5部分,与所述第4部分连接;及
第6部分,与所述第5部分连接;且
所述第5部分的配线宽度小于所述第4部分及所述第6部分的配线宽度。
8.根据权利要求2所述的半导体装置,其中
所述多条第1配线及所述多条第2配线具有:层间配线部,沿着所述半导体衬底的厚度方向延伸;及层内配线部,沿着与所述半导体衬底的表面呈水平的方向延伸。
9.根据权利要求2所述的半导体装置,其
具备与所述多个第1焊垫电极及所述多条第1配线分别连接的多个第1可变电阻元件,且
所述第1可变电阻元件具有:
第1端子;
第1配线部件,与所述第1端子连接;
多个第1晶体管,与所述第1配线部件连接;及
第2端子,与所述多个第1晶体管共通连接;
所述半导体装置还具备与所述多个第1焊垫电极及所述多条第2配线分别连接的多个第2可变电阻元件,且
所述第2可变电阻元件具有:
第3端子;
第2配线部件,与所述第3端子连接;
多个第2晶体管,与所述第2配线部件连接;及
第3端子,与所述多个第2晶体管共通连接。
10.根据权利要求2所述的半导体装置,其具备:
安装衬底,设置有多个电极端子,且积层有多片所述半导体衬底;及
接合配线,将所述多个电极端子与多片所述半导体衬底中的至少一片的所述第1焊垫电极、所述第2焊垫电极及所述第3焊垫电极连接。
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