CN110875280A - Chip full-shielding process method - Google Patents
Chip full-shielding process method Download PDFInfo
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- CN110875280A CN110875280A CN201811023293.XA CN201811023293A CN110875280A CN 110875280 A CN110875280 A CN 110875280A CN 201811023293 A CN201811023293 A CN 201811023293A CN 110875280 A CN110875280 A CN 110875280A
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 230000008569 process Effects 0.000 title claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 238000009713 electroplating Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention provides a chip full-shielding process method, which comprises the following steps: slotting on a core plate of an organic substrate, and metalizing the side wall of the slot; embedding the front surface of the chip into the groove towards the bottom of the groove, and pressing a dielectric layer in the groove to embed the chip in the dielectric layer; forming a blind hole or a blind groove on the dielectric layer on the front surface of the chip to expose the chip pin of the chip, and cleaning the dielectric on the chip pin; carrying out metal electroplating on chip pins; and (4) solder resist green oil is prepared on the part of the front surface of the chip, which is required to be soldered with the BGA solder balls, and the BGA solder balls are soldered after the solder resist green oil is prepared. The invention solves the packaging and shielding problem of the radio frequency microwave system or the chip, and solves the problem of electromagnetic interference between chips in the system and between packages, so that the system or a single chip is packaged to form a fully-shielded packaging structure.
Description
Technical Field
The invention relates to the field of chips, in particular to a chip full-shielding process method.
Background
With the requirements for higher integration level of electronic system miniaturization and the failure of moore's law, System Integrated Package (SiP) becomes an important package structure and form with its advantages of high integration, high performance, continuation of moore's law in the third dimension, etc.
However, in the prior art, when a plurality of chips are integrated into a single package to form a complete system, the problem of complex electromagnetic compatibility exists between different chips in a radio frequency module system or between the chips and external packages.
Disclosure of Invention
Based on the problems, the invention provides a chip full-shielding process method, which solves the packaging and shielding problems of a radio frequency microwave system or chips, solves the electromagnetic interference between the chips in the system and between the packages, and leads the system or a single chip to be packaged to form a full-shielding packaging structure.
The invention provides a chip full-shielding process method, which comprises the following steps:
slotting on a core plate of an organic substrate, and metalizing the side wall of the slot;
embedding the front surface of the chip into the groove towards the bottom of the groove, and pressing a dielectric layer in the groove to embed the chip in the dielectric layer;
forming a blind hole or a blind groove on the dielectric layer on the front surface of the chip to expose the chip pin of the chip, and cleaning the dielectric on the chip pin;
carrying out metal electroplating on chip pins;
and (4) solder resist green oil is prepared on the part of the front surface of the chip, which is required to be soldered with the BGA solder balls, and the BGA solder balls are soldered after the solder resist green oil is prepared.
In addition, the back surface of the chip is provided with a back gold, a blind hole or a blind groove is formed in the dielectric layer on the back surface of the chip, and the side wall of the groove is connected with the back gold on the back surface through the blind hole or the blind groove.
Further, the thickness of the chip is the same as the thickness of the chip.
In addition, when the core plate of the organic substrate is grooved, laser is adopted for grooving.
In addition, the trench is electroless plated or sputtered with a seed layer prior to metallization of the sidewalls of the trench.
In addition, the step of laminating the dielectric layer in the groove to embed the chip in the dielectric layer comprises the following steps: and pouring the medium into the gap completely to enable the chip to be completely embedded.
In addition, solder resist green oil was formed on both the front and back surfaces of the chip.
Through adopting above-mentioned technical scheme, have following beneficial effect:
the invention solves the packaging and shielding problem of the radio frequency microwave system or the chip, and solves the problem of electromagnetic interference between chips in the system and between packages, so that the system or a single chip is packaged to form a fully-shielded packaging structure.
Drawings
FIG. 1 is a flow chart of a chip full-shielding process method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a single chip fully-shielded package structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a system full shield fan-out package configuration according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a fully shielded system according to an embodiment of the present invention;
FIG. 5 is a process flow diagram provided by one embodiment of the present invention;
fig. 6 is a schematic diagram of a system full-shielding structure composed of chips with gold backs according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below with reference to specific embodiments and the attached drawings. It is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention be limited only by the appended claims.
Referring to fig. 1, the invention provides a chip full-shielding process method, which comprises the following steps:
step S001, slotting a core plate of the organic substrate, and metalizing the side wall of the slot;
s002, embedding the front surface of the chip into the groove towards the bottom of the groove, and laminating the dielectric layer in the groove to embed the chip into the dielectric layer;
step S003, a blind hole or a blind groove is formed in the dielectric layer on the front surface of the chip to expose the chip pin of the chip, and the dielectric on the chip pin is cleaned;
step S004, carrying out metal electroplating on the chip pin;
and step S005, solder resist green oil is manufactured on the part of the front surface of the chip, which is required to be soldered with the BGA solder ball, and the BGA solder ball is soldered after manufacture.
In the prior art, shielding is realized by adopting a mode of carrying out metalized through holes around a chip, the distribution of the through holes in the scheme has a great relationship with the frequency of the chip, in addition, the scheme can increase the packaging size of a system, and full shielding is difficult to realize. Patent No. CN106816431A provides a shielding structure with metallization on the top surface of the package, and the shielding structure cannot achieve the shielding effect on the side surface of the package.
In step S001, a groove is formed in a core plate of an organic substrate, the side wall of the groove is metalized, and shielding of the side surface of a chip is realized by metalizing the side wall of the groove;
in step S002, the front surface of the chip is embedded into the groove toward the bottom of the groove, and the dielectric layer is laminated in the groove to embed the chip in the dielectric layer; through carrying out dielectric layer pressfitting in the groove and making the chip bury in the dielectric layer, make the chip totally wrapped up, with the chip embedding in the base plate, the effect of dielectric layer does: the insulating layer is used for manufacturing circuits and avoiding short circuit between the circuits; the glue body in the dielectric layer can be used for filling the gap between the chip and the chip groove in the pressing process, so that the chip is completely embedded into the dielectric layer. Optionally, the dielectric layer is a resin. In the specific operation, the chip is placed in the chip groove, and then the dielectric layers are attached to the two sides.
In step S003, a blind hole or a blind groove is formed in the dielectric layer on the front surface of the chip to expose the chip pin of the chip, and the dielectric on the chip pin is removed; the interaction between the chip and the outside is realized through chip pins distributed on the surface of the chip, and as the chip is embedded into the dielectric layer, the medium on the chip pins needs to be cleaned up by opening blind holes or blind grooves through laser, then metal electroplating is carried out on the medium, and the like, and the chip pins are led out to the surface through opening the blind holes or the blind grooves, so that the communication between the chip and the outside is realized. The blind holes or blind grooves also have the function of protecting the interconnection between the side wall metal of the grooves and external circuits, wherein the cut-off layers of the blind holes or blind grooves are on the metal layers on the surfaces of the chip and the core plate.
In step S004, metal plating is performed on the chip pin;
in step S005, solder resist green oil is formed on the portion of the front surface of the chip to which the BGA solder ball is to be soldered, and the BGA solder ball is soldered after the formation.
The solder resist green oil preparation process comprises the following steps: and vacuum lamination is carried out by using dry film type green oil or solder mask layer manufacturing is carried out by using ink type green oil and a screen printing process, and then exposure development and curing are carried out to finish the solder mask green oil manufacturing.
When the BGA welding ball is welded, firstly, tin paste or soldering flux is printed on a chip manager, then the BGA welding ball is placed on a welding pad, and finally, reflow soldering is carried out to form the BGA welding ball.
The solder resist green oil can prevent solder of the BGA solder balls from overflowing, and can help to form good solder balls when the BGA solder balls are planted as a barrier layer, so that the solder balls cannot collapse.
Referring to fig. 2, fig. 2 is a schematic diagram of a single chip package shield, which includes: side wall metal 1, chip 2, BGA solder balls 3, blind holes 4 and core board 5.
Referring to fig. 3 and 4, fig. 3 is a schematic diagram of a system full-shielding fan-out type packaging structure, and by adopting the chip full-shielding structure provided by the invention, the problem of electromagnetic interference between multiple chips and between packages is realized by a multi-chip system.
Referring to fig. 5, fig. 5 shows a process flow of the chip full-shielding process method.
The invention solves the packaging and shielding problem of the radio frequency microwave system or the chip, and solves the problem of electromagnetic interference between chips in the system and between packages, so that the system or a single chip is packaged to form a fully-shielded packaging structure. The invention realizes a chip full-shielding structure by utilizing the metallization in the chip groove, realizes the full-wrapping shielding of the chip by utilizing the metal embedded in the side wall of the chip groove body and the front grounding welding ball, effectively solves the electromagnetic interference between chips and between packages in a system, and improves the system performance. The invention realizes the full-shielding packaging structure by combining the mature substrate process, and has the characteristics of good shielding performance, low process cost, simple process method, suitability for large-scale production and the like.
Referring to fig. 6, in one embodiment, the back surface of the chip has a back gold, a blind via or a blind via is formed in a dielectric layer on the back surface of the chip, and the side wall of the slot and the back gold on the back surface are interconnected through the blind via or the blind via, so that the grounding metal on the side wall of the slot, the grounding metal on the back surface of the chip, and the grounding solder ball on the front surface of the chip provide an omnidirectional shielding grounding metal, and the packaged chips are wrapped in the shielding metal to form a fully-shielded package structure between system chips and between packages.
Optionally, chemically plating seeds after removing medium slag in the blind holes, and then electroplating the blind holes, thereby realizing interconnection; and then, manufacturing metal layer circuits on the back and the front. Optionally, laser drilling is performed on the blind holes at corresponding positions by using a laser drilling machine, chemical copper plating is performed after removing glue residues in the blind holes, and the circuit layer can be manufactured by adopting two modes of pattern electroplating or full-plate electroplating.
In one of the embodiments, the thickness of the chip is the same as the thickness of the chip. Structurally and technologically, the thickness of the core board is the same as that of the chip, so that the core board can protect the embedded chip, and technically, the position precision of the embedded chip after lamination can be better ensured in the lamination process.
In one embodiment, when the grooves are formed on the core plate of the organic substrate, the grooves are formed by using laser. With the continuous improvement of the integration level of the chip and the smaller and smaller line width, the laser is required to be adopted for slotting with precise size. The size of the slot is larger than that of the chip and is used for embedding the chip, and the core plate is used as a support of the whole packaging body and can also determine the accurate position of the embedded chip.
In one embodiment, the trench is electroless plated or sputtered with a seed layer prior to metallization of the sidewalls of the trench. The electroplating process can be performed by chemically plating or sputtering a seed layer onto the bath.
In one embodiment, the step of laminating the dielectric layer in the groove to embed the chip in the dielectric layer comprises: and pouring the medium into the gap completely to enable the chip to be completely embedded. The chip is completely embedded by filling all gaps with a dielectric.
In one embodiment, solder resist green oil is applied to both the front and back sides of the chip.
Solder resist green oil is used to block solder from collapsing around the pad when other devices are soldered.
The foregoing is considered as illustrative only of the principles and preferred embodiments of the invention. It should be noted that, for those skilled in the art, several other modifications can be made on the basis of the principle of the present invention, and the protection scope of the present invention should be regarded.
Claims (7)
1. A chip full-shielding process method is characterized by comprising the following steps:
slotting on a core plate of an organic substrate, and metalizing the side wall of the slot;
embedding the front surface of the chip into the groove towards the bottom of the groove, and pressing a dielectric layer in the groove to embed the chip in the dielectric layer;
forming a blind hole or a blind groove on the dielectric layer on the front surface of the chip to expose the chip pin of the chip, and cleaning the dielectric on the chip pin;
carrying out metal electroplating on chip pins;
and (4) solder resist green oil is prepared on the part of the front surface of the chip, which is required to be soldered with the BGA solder balls, and the BGA solder balls are soldered after the solder resist green oil is prepared.
2. The chip full-shielding process method according to claim 1,
the back surface of the chip is provided with a back gold, a blind hole or a blind groove is formed in a dielectric layer on the back surface of the chip, and the side wall of the groove is connected with the back gold on the back surface through the blind hole or the blind groove.
3. The chip full-shielding process method according to claim 1,
the thickness of the chip is the same as the thickness of the chip.
4. The chip full-shielding process method according to claim 1,
when the core plate of the organic substrate is grooved, laser is adopted for grooving.
5. The chip full-shielding process method according to claim 1,
the trench is electroless plated or sputtered with a seed layer prior to metallization of the sidewalls of the trench.
6. The chip full-shielding process method according to claim 1,
the step of pressing the dielectric layer in the groove to embed the chip in the dielectric layer comprises the following steps: and pouring the medium into the gap completely to enable the chip to be completely embedded.
7. The chip full-shielding process method according to any one of claims 1 to 6,
and (4) solder resist green oil is manufactured on the front surface and the back surface of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811023293.XA CN110875280A (en) | 2018-09-03 | 2018-09-03 | Chip full-shielding process method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811023293.XA CN110875280A (en) | 2018-09-03 | 2018-09-03 | Chip full-shielding process method |
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| Publication Number | Publication Date |
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| CN110875280A true CN110875280A (en) | 2020-03-10 |
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| CN201811023293.XA Pending CN110875280A (en) | 2018-09-03 | 2018-09-03 | Chip full-shielding process method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117153824A (en) * | 2023-09-21 | 2023-12-01 | 上海韬润半导体有限公司 | Embedded packaging structure, embedded packaging method and packaging substrate |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367269A (en) * | 2013-07-15 | 2013-10-23 | 香港应用科技研究院有限公司 | Separation mixed substrate for radio frequency application |
| CN103716992A (en) * | 2012-10-02 | 2014-04-09 | 钰桥半导体股份有限公司 | Wiring board with embedded device, built-in stopper and electromagnetic shielding |
| CN105161474A (en) * | 2015-07-08 | 2015-12-16 | 华进半导体封装先导技术研发中心有限公司 | Fan-out packaging structure and production technology thereof |
| TWI630690B (en) * | 2016-04-25 | 2018-07-21 | 三星電機股份有限公司 | Fan-out semiconductor package |
| CN208722873U (en) * | 2018-09-03 | 2019-04-09 | 北京万应科技有限公司 | The full frame shield structure of chip and full-shield package system |
-
2018
- 2018-09-03 CN CN201811023293.XA patent/CN110875280A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103716992A (en) * | 2012-10-02 | 2014-04-09 | 钰桥半导体股份有限公司 | Wiring board with embedded device, built-in stopper and electromagnetic shielding |
| CN103367269A (en) * | 2013-07-15 | 2013-10-23 | 香港应用科技研究院有限公司 | Separation mixed substrate for radio frequency application |
| CN105161474A (en) * | 2015-07-08 | 2015-12-16 | 华进半导体封装先导技术研发中心有限公司 | Fan-out packaging structure and production technology thereof |
| TWI630690B (en) * | 2016-04-25 | 2018-07-21 | 三星電機股份有限公司 | Fan-out semiconductor package |
| CN208722873U (en) * | 2018-09-03 | 2019-04-09 | 北京万应科技有限公司 | The full frame shield structure of chip and full-shield package system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117153824A (en) * | 2023-09-21 | 2023-12-01 | 上海韬润半导体有限公司 | Embedded packaging structure, embedded packaging method and packaging substrate |
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