CN103716992A - Wiring board with embedded device, built-in stopper and electromagnetic shielding - Google Patents

Wiring board with embedded device, built-in stopper and electromagnetic shielding Download PDF

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Publication number
CN103716992A
CN103716992A CN201310468443.9A CN201310468443A CN103716992A CN 103716992 A CN103716992 A CN 103716992A CN 201310468443 A CN201310468443 A CN 201310468443A CN 103716992 A CN103716992 A CN 103716992A
Authority
CN
China
Prior art keywords
semiconductor element
layer
keeper
layer circuit
screening cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310468443.9A
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Chinese (zh)
Inventor
林文强
王家忠
陈振重
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/043,933 external-priority patent/US20140061877A1/en
Application filed by Yuqiao Semiconductor Co Ltd filed Critical Yuqiao Semiconductor Co Ltd
Publication of CN103716992A publication Critical patent/CN103716992A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

The invention discloses a wiring board with embedded device, built-in stopper and electromagnetic shielding. The wiring board includes a stopper, a semiconductor device, a stiffener with shielding sidewalls, a first build-up circuitry and a second build-up circuitry with a shielding lid. The first and second build-up circuitries cover the semiconductor device, the stopper and the stiffener in the opposite vertical directions. The shielding sidewalls and the shielding lid are electrically connected to at least one ground contact pad of the semiconductor device by the first build-up circuitry and can respectively serve as effective horizontal and vertical electromagnetic shields for the semiconductor device within the aperture of the stiffener.

Description

The wiring board with embedded element, built-in keeper and electromagnetic barrier
Technical field
The present invention relates to a kind of wiring board with embedded element, built-in keeper and electromagnetic barrier, a kind of wiring board with screening cover and shielding sidewall particularly, wherein screening cover and shielding sidewall can be respectively as the vertical and horizontal barrier of embedded element.
Background technology
Semiconductor element is vulnerable to electromagnetic interference (EMI) or other inner members disturb, such as the electric capacity when high frequency mode operates, induction, conduction coupling etc.When semiconductor chip is for microminiaturized and when closely arranging each other, the seriousness of these bad interference may significantly rise.In order to reduce electromagnetic interference, in some semiconductor element and module, may need barrier.
The people's such as Bolognia United States Patent (USP) 8,102,032, the people's such as Pagaila United States Patent (USP) 8,105,872, the people's such as Fuentes U.S. Patent number 8,093,691, the people's such as Chi United States Patent (USP) 8,314,486 and United States Patent (USP) 8,349,658 have disclosed the whole bag of tricks for semiconductor element barrier, comprise metal can, linear network (wire fences) or spherical net (ball fences).Above-mentioned all methods are all designed for the element being for example assembled in, on substrate and shielding material (metal can, metal film, wire or spherical net), shielding material is all outside form of adding, it needs exceptional space, thereby increases the size of semiconductor packages and additionally expend.
The people's such as Ito United States Patent (USP) 7,929,313, United States Patent (USP) 7,957,154 and U.S. Patent number 8,168,893 have disclosed conductive blind hole that a kind of use is arranged in resin bed to form the method for electromagnetic barrier layer, and this electromagnetic barrier layer is around for holding the sunk part of embedded semiconductor element.This kind of structure guarantees that the excellence of embedded element in little space electrically shields, but the degree of depth of conductive blind hole need to be as the thickness of semiconductor element, thus be subject to the restriction of high aspect ratio when boring and coating hole, and only can hold some ultra-thin elements.In addition, because the sunk part as chip put area is to form, because alignment is poor, cause semiconductor element dislocation after conductive blind hole metallization, and then make the method productive rate when a large amount of manufacture extremely low.
Summary of the invention
The present invention develops in view of above situation, and its object is to provide a kind of can be fixed on embedded element the wiring board of one precalculated position and barrier electromagnetic interference.Accordingly, wiring board provided by the present invention comprises a screening cover, semiconductor element, positioning piece, has a reinforced layer, the one first increasing layer circuit of a through hole of shielding sidewall and optionally comprise that one second increases a layer circuit.In addition, the present invention also provides another kind of wiring board, and it comprises semiconductor element, positioning piece, has the one second increasing layer circuit that a reinforced layer of a through hole of shielding sidewall, one first increases layer circuit, has a screening cover.
In a preferred embodiment, this keeper is as the configuration guiding element of this semiconductor element, this keeper is near the peripheral edge of this semiconductor element, and in this semi-conductive peripheral edge of side surface direction lateral alignment, and extend laterally over this semi-conductive peripheral edge in side surface direction.This semiconductor element and this keeper extend into this through hole of this reinforced layer, and this shielding sidewall of this through hole is in side surface direction side direction, to cover the peripheral edge of this semiconductor element, and this screening cover is to cover this semiconductor element in this second vertical direction.This shielding sidewall and this screening cover are electrically connected the ground connection contact pad of at least one this semiconductor element, and can be respectively as the level of this semiconductor element and vertical barrier.This first increasing layer circuit and this second increasing layer circuit cover this semiconductor element, this keeper and this reinforced layer respectively at this first vertical direction and this second vertical direction.
This semiconductor element comprises an active surface and contrary with this active surface one non-active on this active surface, having a plurality of contact pads.This active surface of this semiconductor element faces this first vertical direction, and this screening cover dorsad, and this non-active face of this semiconductor element faces this second vertical direction, and towards this screening cover.This semiconductor element can be fixed in via adhesive agent on this first or second increasing layer circuit, or is arranged on this screening cover.
This keeper can be prepared from by metal, photosensitive plastic material or non-photosensitivity material.For instance, this keeper substantially can be prepared by copper, aluminium, nickel, iron, tin or its alloy, and this keeper also can be prepared by epoxy resin or polyimides.
This reinforced layer comprises a through hole, and this through hole has the sidewall of conduction, and can use adhesive agent and be fixed on this screening cover or this first increases on an insulating barrier of layer circuit or this second insulating barrier.This reinforced layer may extend to the peripheral edge of this wiring board, and provides mechanical support to suppress bending or the warpage of this wiring board.This reinforced layer can be single layer structure or the sandwich construction with embedded individual layer wire or multi-layer conductor leads, for example, can be multilayer circuit board.This reinforced layer can be comprised of nonmetallic materials, as multiple inorganic or organic insulating material, comprises pottery, aluminium oxide (Al 2o 3), aluminium nitride (AlN), silicon nitride (SiN), silicon (Si), glass, stacked epoxy resin, polyimides or copper clad laminate.In the process of plating, in the through hole of non-metal reinforced layer, can form metallized sidewall, so that the electromagnetic shielding of the horizontal direction of this semiconductor element that is positioned at this through hole to be provided.In addition, this of this reinforced layer first and second surface can be metallized via plating program, thereby, this reinforced layer comprise a conductive layer in this first and second surface, be electrically connected and be adjacent to this shielding sidewall.This reinforced layer also can be made by metal, as copper (Cu), aluminium (Al), stainless steel etc.For effective horizontal effectiveness is provided, this shielding sidewall is preferably the side surface that intactly covers this semiconductor element, to reduce the electromagnetic interference of horizontal direction.In addition, this shielding sidewall can be electrically connected via this first increasing layer circuit the contact pad of at least one ground connection.For instance, this shielding sidewall can be electrically connected to this first increasing layer circuit via the conductive blind hole of this first increasing layer circuit, and the conductive layer on this first surface of this first increasing layer circuit and this reinforced layer is electrically connected.Therefore, the electric connection between the ground connection contact pad of this shielding sidewall and this semiconductor element can provide via this first increasing layer circuit.Or this shielding sidewall can be electrically connected to this first increasing layer circuit via extending through one or more coating perforation of this reinforced layer.For instance, this coating perforation is extensible through this reinforced layer, is adjacent to the conductive layer of this reinforced layer, and extends to this first increasing layer circuit and be electrically connected to this first increasing layer circuit in a first end.Therefore, this first increasing layer circuit and this coating are bored a hole the electric connection between the ground connection contact pad of this shielding sidewall and this semiconductor element can be provided.
This screening cover is to aim at this semiconductor element and cover this semiconductor element in this second vertical direction, and can be electrically connected to via this first increasing layer circuit at least one ground connection contact pad of this semiconductor element.This screening cover can be continuous metal level, and preferably can extend horizontally at least and overlap with the peripheral edge of this semiconductor element, so that effectively vertical electromagnetic shielding effect to be provided.For instance, this screening cover can in side surface direction extend laterally until with the peripheral edge copline of this semiconductor element, or laterally to the peripheral edge that extends beyond this semiconductor element, and even extend laterally to the peripheral edge of this wiring board, accordingly, this screening cover can fully cover this semiconductor element in this second vertical direction, and can minimize the electromagnetic interference of vertical direction.This screening cover spaced apart with this first increasing layer circuit can be electrically connected to this first increasing layer circuit via this reinforced layer with this first increasing layer circuit electric connection.For instance, this screening cover can be electrically connected to the conductive layer of the second surface of this reinforced layer via conductive blind hole or conduction ditch, conductive blind hole or the contact of conduction ditch and the electric connection between the conductive layer of this screening cover and this reinforced layer is provided.Therefore, the electric connection between the ground connection contact pad of this screening cover and this semiconductor element can provide by this reinforced layer and this first increasing layer circuit.Moreover this screening cover can be electrically connected to this first increasing layer circuit via one or more coating perforation, wherein this coating perforation extends through this reinforced layer.For instance, in this coating of first end, bore a hole extensible until be electrically connected to this first increasing layer circuit, and extensible until be electrically connected to this screening cover in this coating perforation of the second end.Therefore, the electric connection between the ground connection contact pad of this screening cover and this semiconductor element can be bored a hole and this first increases layer circuit and provide by this coating.
This first increasing layer circuit is to cover this keeper, this semiconductor element and this reinforced layer in this first vertical direction, and this first increasing layer circuit can comprise one first insulating barrier and one or more the first wire.For instance, this first insulating barrier is to cover this keeper, this semiconductor element and this reinforced layer in this first vertical direction, and this first insulating barrier may extend to the peripheral edge of this wiring board, and this first wire extends towards this first vertical direction from this first insulating barrier.This first insulating barrier can comprise a plurality of the first blind holes, and described the first blind hole is set up the contact pad that is adjacent to this semiconductor element.One or more first wire extends towards this first vertical direction from this first insulating barrier, and extend laterally on this first insulating barrier, and extend into described the first blind hole to form a plurality of the first conductive blind holes in this second vertical direction, thereby can provide a plurality of signal contact pads of this semiconductor element and the signal route of a plurality of ground connection contact pads.In addition, this first insulating barrier can comprise the first blind hole that one or more is extra, described the first extra blind hole is set up the selected part of this conductive layer of this first surface that is adjacent to this reinforced layer, this first wire can further extend in described the first extra blind hole in this second vertical direction, to form one or more the first extra conductive blind hole, described the first conductive blind hole is electrically connected the conductive layer of this reinforced layer, thereby the ground connection contact pad of this semiconductor element and the grounding connection between this shielding sidewall are provided.In sum, this the first increasing layer circuit is electrically connected to the described contact pad of this semiconductor element via described the first conductive blind hole, so that signal route and the ground connection of this semiconductor element to be provided, and can further be electrically connected to this shielding sidewall via described the first extra conductive blind hole, so that the ground connection of this shielding sidewall to be provided.Because this first wire can directly contact the described contact pad of this semiconductor element and this conductive layer of this reinforced layer, this semiconductor element and this first electric connection increasing between layer circuit, and the electric connection between this shielding sidewall and this first increasing layer circuit can not contain scolder.Further signal route if necessary, this first increases layer circuit and can comprise extra dielectric layer, have the extra layer of blind hole and extra wire.
According to the mode that there is this semiconductor element and be arranged at the wiring board on this screening cover, this the second increasing layer circuit is optionally provided, and this second increasing layer circuit covers this screening cover and this reinforced layer in this second vertical direction, in this mode, this second increasing layer circuit can comprise one second insulating barrier and one or more the second wire.For instance, this second insulating barrier is to cover this screening cover and this reinforced layer in this second vertical direction, and may extend to the peripheral edge of this wiring board, and this second wire extends towards this second vertical direction from this second insulating barrier, and extend laterally on this second insulating barrier.This second insulating barrier can comprise one or more second blind hole being arranged in abutting connection with the selected position of this screening cover, this second wire can further extend into described the second blind hole to form one or more the second conductive blind hole in this first vertical direction, thereby the electric connection of this screening cover can be provided.And in this screening cover, be built in this second another way that increases the wiring board of layer circuit, this the second increasing layer circuit is to cover this keeper, this semiconductor element and this reinforced layer in this second vertical direction, and can comprise one second insulating barrier, this screening cover and optionally comprise the second wire.For instance, this second insulating barrier is to cover this keeper, this semiconductor element and this reinforced layer in this second vertical direction, and may extend to the peripheral edge of this wiring board, this screening cover and this second wire extend towards this second vertical direction from this second insulating barrier, and extend laterally on this second insulating barrier.This second insulating barrier can comprise one or more the second blind hole or groove opening, and it is set up the selected part of this conductive layer of this second surface that is adjacent to this reinforced layer, and can be metallized to form one or more second conductive blind hole or conduction ditch.Accordingly, this screening cover can be electrically connected to this and first increase layer circuit with ground connection, and its be electrically connected via this reinforced layer and this second, increase layer circuit this second conductive blind hole maybe this conduction ditch provide.Further signal route if necessary, this second increases layer circuit and can comprise extra dielectric layer, have the extra layer of blind hole and extra wire.
Wiring board of the present invention can further comprise one or more coating perforation, and it extends through this reinforced layer.This coating perforation can provide this first electric connection increasing between layer circuit and this second increasing layer circuit.For instance, be positioned at this coating perforation of this first end extensible and be electrically connected to this and first increase the outer or inner conducting layer of layer circuit, and it is extensible and be electrically connected to this second outer or inner conducting layer or shielding sidewall that increases layer circuit to be positioned at this coating perforation of the second end.Therefore, this coating perforation can be provided in the electric connection of Vertical Square signal route or ground connection.
The outermost wire of this first or second increasing layer circuit, can comprise respectively one or more the first and second interior connection gasket, so that the electric connection point of an electronic component (as semiconductor chip, a Plastic Package or another semiconductor group body) to be provided.Described the first interior connection gasket can comprise and face the contact surface that one of this first vertical direction exposes, and described the second interior connection gasket can comprise and faces the contact surface that one of this second vertical direction exposes.Therefore, this wiring board can comprise electrical contact (for example this first interior connection gasket and this second interior connection gasket), it is electrically connected each other and is positioned at the opposed surface that faces contrary vertical direction, make this wiring board can be stacking, and electronic component can utilize various connection media to be electrically connected to this wiring board, connect medium and comprise that routing or solder bump using as electrical contact.
Wiring board of the present invention can further comprise a configuration guiding element of this reinforced layer configuration of guiding.This configuration guiding element of this reinforced layer is the peripheral edge near this reinforced layer in side surface direction, and lateral alignment is in the peripheral edge of this reinforced layer, and in side surface direction, extends beyond the peripheral edge of this reinforced layer.As this keeper, this configuration guiding element of this reinforced layer can be prepared from by metal, photosensitive plastic material or non-photosensitivity material, as prepared in copper, aluminium, nickel, iron, tin, its alloy, epoxy resin or polyimides.
This keeper and this configuration guiding element can contact in this first vertical direction this screening cover or an insulating barrier of this first increasing layer circuit, and this first this screening cover or insulating barrier that increases layer circuit extends towards this first vertical direction certainly; Or can towards this second vertical direction, extend from this second insulating barrier that increases layer circuit.For instance, this keeper can extend towards this first vertical direction from this second insulating barrier or screening cover that increases layer circuit, and extend beyond this non-active of this semiconductor element, or this first insulating barrier that increases layer circuit extends towards this second vertical direction certainly, and extends beyond the active surface of this semiconductor element.Similarly, this configuration guiding element can extend from this second insulating barrier or screening cover that increases layer circuit in this first vertical direction, and extends beyond the contact surface of this reinforced layer; Or in this second vertical direction, from this first insulating barrier that increases layer circuit, extend, and extend beyond the contact surface of this reinforced layer.Any in the situation that, this keeper and this configuration guiding element can contact this first increasing layer circuit and this second increasing layer circuit, and between this first increasing layer circuit and this second increasing layer circuit, or can be between this first increasing layer circuit and this screening cover.
In addition, this keeper and this configuration guiding element can have pattern to avoid respectively this semiconductor element and the unnecessary movement of this reinforced layer.For instance, this keeper and this configuration guiding element can comprise a continuous or discrete batten or protruded stigma array, and this keeper and this configuration guiding element can form simultaneously and have identical or different pattern.Specifically, can side direction align four side surfaces of this semiconductor element of this keeper, to prevent the lateral displacement of this semiconductor element.For instance, this keeper can be along four sides of this semiconductor element, two diagonal angles or four angle alignment, and the gap between this semiconductor element and this keeper is preferably within the scope of 0.001 to 1 millimeter, this semiconductor element can be spaced apart by the inwall of this keeper and this through hole, and can add grafting material between this semiconductor element and this reinforced layer to increase its rigidity.In addition, this keeper also can be near the inwall of this through hole and the inwall of this through hole that aligns to prevent the lateral displacement of this reinforced layer.In like manner, this configuration guiding element can side direction be aligned in four outer surfaces of this reinforced layer, to prevent the lateral displacement of this reinforced layer.For instance, this configuration guiding element can align along four lateral surfaces of this reinforced layer, two outer diagonal angles or four exterior angles, and the gap between the peripheral edge of this reinforced layer and this configuration guiding element is preferably within the scope of 0.001 to 1 millimeter, in addition, the thickness of this keeper and this configuration guiding element is preferably 10 to 200 microns.
The present invention also provides a kind of three-dimensional stacked group of body, it is by a plurality of stacking forming of wiring board with embedded element, built-in keeper and electromagnetic barrier, a plurality of wiring board utilizations lay respectively at the inner-dielectric-ayer between two adjacent lines plates, with back-to-back (back-to-back) or in the face of the mode of the back of the body (face-to-back) stacking, and by one or more coating perforation be electrically connected to each other.
The present invention has many advantages, and wherein, this reinforced layer can provide a mechanical support of this increasing layer circuit.This shielding sidewall and this screening cover of this reinforced layer can be respectively as level and the vertical EMI barrier of this semiconductor element, to reduce electromagnetic interference.The described ground connection contact pad of this semiconductor element and the electric connection between described shielding sidewall/screening cover can provide via this increasing layer circuit, so that the effective electromagnetic barrier effect of this semiconductor element being embedded in this wiring board to be provided.Because this increases the high routing capability (routing capability) of layer circuit, this increasing layer circuit can provide signal route and be beneficial to and represent high I/O value and high-performance.In addition, this keeper can limit the placement location of this semiconductor element exactly, to avoid causing the electric connection mistake between this semiconductor element and this increasing layer circuit because of the lateral displacement of this semiconductor element, and then has significantly improved product yield.This wiring board and use its reliability of this stacked group body high, cheap and be applicable to very much a large amount of manufacture and produce.
Accompanying drawing explanation
Fig. 1～8th, the manufacture method cutaway view of the wiring board of a preferred embodiment of the present invention, wherein this wiring board comprises positioning piece, semiconductor element, a reinforced layer, two increasing layer circuit and coating perforation; Wherein Fig. 2 A, 2A ', 3A and 5A are respectively Fig. 2,2 ', 3 and 5 vertical view, and Fig. 2 B to Fig. 2 E is respectively the vertical view of other reference patterns of this keeper.
Fig. 9～12nd, the manufacture method cutaway view of another wiring board of another preferred embodiment of the present invention, wherein this wiring board comprises a screening cover and shielding sidewall, and it is electrically connected to a plurality of ground connection contact pads of semiconductor element by a plurality of conductive blind holes.
Figure 13～15th, the manufacture method cutaway view of the another wiring board of the another preferred embodiment of the present invention, wherein this wiring board comprises a screening cover, it is electrically connected to a patterned conductive layer of a reinforced layer by a plurality of conduction ditches.Wherein, Figure 14 A is the upward view of Figure 14.
Figure 16～21st, according in another embodiment of the invention, another preparation method's cutaway views with the wiring board of two increasing layer circuit, wherein, increase layer circuit and comprise extra insulating barrier and wire, and bore a hole and be electrically connected to another increasing layer circuit by a plurality of coatings.
Figure 22～28th, according to an embodiment of the present invention in, preparation method's cutaway view of one wiring board, it comprises that positioning piece, a screening cover, semiconductor element, a reinforced layer, increase layer circuit, a plurality of conduction ditch, a plurality of terminal and a plurality of coating perforation.
Figure 29～34th, according in an execution mode more of the present invention, preparation method's cutaway view of a wiring board, it comprises positioning piece, a screening cover, semiconductor element, a reinforced layer, two increasing layer circuit and a plurality of coating perforation.
Figure 35～42nd, according in another embodiment of the present invention, one has preparation method's cutaway view of the wiring board of screening cover, and wherein this screening cover inserts in the through hole of this reinforced layer.
Figure 43～45th, according to an embodiment of the present invention in, preparation method's cutaway view of one three-dimensional stacked group of body, it comprises a plurality of with in the face of the stacking wiring board of back of the body mode.
Figure 46～48th, according in another embodiment of the present invention, preparation method's cutaway view of one three-dimensional stacked group of body, it comprises a plurality of with the stacking wiring board of back-to-back mode.
[description of reference numerals]
100,110,120,130,140,200,300,400,500,600,700 wiring boards
11,22 metal levels
113 keeper 13 dielectric layers
15 supporting bracket 16,18 adhesive agents
21 ' first coating 22' the second coating
201 first increase layer circuit 202 second increases layer circuit
203 increase layer circuit 211 first insulating barriers
213 first blind hole 215 first wires
217 first conductive blind hole 221 second insulating barriers
222 groove opening 223 second blind holes
224 screening cover 226,229 terminals
227 second conductive blind hole 228 conduction ditches
231 the 3rd insulating barrier 233 the 3rd blind holes
235 privates 241 the 4th insulating barrier
245 privates 261 inner-dielectric-ayers
31 semiconductor element 311 active surfaces
312 non-active of contact pads 313
41 reinforced layer 411 through holes
413 conductive layer 511,512 perforation
415 shielding sidewall 513,514 articulamentums
515,516 coating perforation
Embodiment
Hereinafter, will provide embodiment to describe embodiments of the present invention in detail.Other advantages of the present invention and effect will be more remarkable by the disclosed content of the present invention.It should be noted in the discussion above that described accompanying drawing is graphic for what simplify, number of elements, shape and large I shown in graphic are modified according to physical condition, and the configuration of element may be more complicated.In the present invention, also can carry out otherwise practice or application, and not deviate under the condition of the defined spirit of the present invention and category, can carry out various variations and adjustment.
[embodiment 1]
Fig. 1～8th, in one embodiment of the present invention, the preparation method's of a wiring board cutaway view, this wiring board comprises positioning piece, semiconductor element, a reinforced layer, two increasing layer circuit and coating perforation.
As shown in Figure 8, wiring board 100 comprises that keeper 113, semiconductor element 31, reinforced layer 41, first increase layer circuit 201, second and increase layer circuit 202 and coating perforation 515.Semiconductor element 31 comprises active surface 311, contrary with active surface 311 non-active 313 and in a plurality of contact pads 312 of active surface 311.First increases layer circuit 201 comprises the first insulating barrier 211 and the first wire 215, and is electrically connected to semiconductor element 31 via a plurality of the first conductive blind holes 217.Second increases layer circuit 202 comprises the second insulating barrier 221 and screening cover 224.Keeper 113 is that the first insulating barrier 211 from the first increasing layer circuit 201 extends in upward direction, and the peripheral edge of close semiconductor element 31.The second screening cover 224 that increases layer circuit 202 is to extend laterally on the second insulating barrier 211, and covers this semiconductor element 31 in upward direction.The shielding sidewall 415 of reinforced layer 41 covers semiconductor element 31 in side surface direction side direction.Coating perforation 515 provides between screening cover 224 and the ground connection contact pad of semiconductor element 31, and the electric connection between shielding sidewall 415 and the ground connection contact pad of semiconductor element 31.
Fig. 1 and Fig. 2 be according to an embodiment of the present invention in, on a dielectric layer, form the method profile of positioning piece, and Fig. 2 A is the vertical view of Fig. 2.
Fig. 1 is the profile of a laminated substrate, and it comprises metal level 11, dielectric layer 13 and supports version 15.Metal level 11 in figure for thickness be the copper layer of 35 microns, yet metal level 11 also can be various metal materials, is not limited to copper layer.In addition, metal level 11 can be deposited on dielectric layer 13 by various technology, comprises that lamination, plating, electroless-plating, evaporation, sputter and combination thereof are with the structure of deposited monolayers or multilayer, and its thickness is preferably in the scope of 10 to 200 microns.
It is made that dielectric layer 13 is generally epoxy resin, glass epoxy resin, polyimides and analog thereof, and have the thickness of 50 microns.In this execution mode, dielectric layer 13 is between metal level 11 and supporting bracket 15.Yet supporting bracket 15 can be omitted under some execution mode.Supporting bracket 15 is conventionally made by copper, but copper alloy or other materials all can be used, the thickness of supporting bracket 15 can the scope of in 25 to 1000 microns in, and using technique and cost as consideration, it is preferably in the scope of 35 to 100 microns.In this execution mode, supporting bracket 15 is the copper coin of 35 microns of thickness.
Fig. 2 and Fig. 2 A are respectively structure cutaway view and the vertical view with the keeper 113 being formed on dielectric layer 13.The selected position that keeper 113 can remove metal level 11 by photoetching process and wet etching forms.In this is graphic, keeper 113 is comprised of a plurality of metal protruded stigmas of rectangular array, and is consistent with four sides that are arranged at subsequently the semiconductor element on dielectric layer 13.Yet the form of keeper is not limited to this, and can be any pattern of the unnecessary displacement that prevents the semiconductor element that arranges subsequently.
Fig. 1 ' and 2 ' is in embodiments of the present invention, forms the other method cutaway view of positioning piece on a dielectric layer, and Fig. 2 A ' vertical view that is Fig. 2 '.
Fig. 1 ' is for having the cutaway view of the laminated substrate of one group of depression 111.This laminar structure comprises metal level 11 as above, dielectric layer 13 and supporting bracket 15, and depression 111 forms via removing the selected part of metal level 11.
Fig. 2 ' and Fig. 2 A ' keeper 113 of respectively doing for oneself is formed at structure cutaway view and the vertical view on dielectric layer 13.Keeper 113 can via disperse or printing one photosensitive plastic material (as epoxy resin, polyimides etc.) or non-photosensitivity material in depression 111, then remove bulk metal layer 11 and form.At this, the keeper 113 in graphic is a plurality of resin protruded stigma arrays, and meets two diagonal angles of the semiconductor element arranging subsequently.
Fig. 2 B～2E is the various with reference to form of keeper.For instance, keeper 113 can be comprised of a continuous or discrete batten, and meets subsequently four sides (as shown in Fig. 2 B and 2C) of the semiconductor element arranging, two diagonal angles or four corners (as Fig. 2 D and 2E).
Fig. 3 and Fig. 3 A are respectively and use adhesive agent 16 that semiconductor element 31 is arranged to structure cutaway view and the vertical view on dielectric layer 13.Semiconductor element 31 comprises active surface 311, non-active 313 and a plurality of contact pads 312 in active surface 311 on contrary with active surface 311.Semiconductor element 31 is arranged on dielectric layer 13, and its active surface 311 faces dielectric layer 13, and dielectric layer 13 is regarded as the first insulating barrier 211 of the first increasing layer circuit.
Keeper 113 can be used as the configuration guiding element of semiconductor element 31, thereby semiconductor element 31 can be positioned on a precalculated position exactly.Keeper 113 extends and surmounts the active surface 311 of semiconductor element 31 towards upward direction from dielectric layer 13, and in four sides of side surface direction lateral alignment semiconductor element 31, and extend in the lateral, four sides of semiconductor element 31.When keeper 113 in side surface direction four side surfaces near semiconductor element 31, and meet four side surfaces of semiconductor element 31, and during lower than keeper 113, can avoid any unnecessary displacement of semiconductor element 31 when solidifying adhesive agent 16 in the adhesive agent 16 of semiconductor element 31 belows.Preferably, the gap between semiconductor element 31 and keeper 113 is in the scope of 0.001 to 1 millimeter.
Fig. 4 and Fig. 5 are laminated to the process constructed profile on the first insulating barrier 211 by reinforced layer 41, and Fig. 5 A vertical view that is Fig. 5.Semiconductor element 31 and keeper 113 are aimed in the through hole 411 of reinforced layer 41, and use adhesive agent 18 that reinforced layer 41 is arranged to the first insulating barrier 211, adhesive agent 18 contact reinforced layer 41 and the first insulating barriers 211, and between reinforced layer 41 and the first insulating barrier 211.Reinforced layer 41 shown in figure is located in through hole 411 and the ceramic wafer with conductive layer 413 of upper and lower surface.Through hole 411 is formed on reinforced layer 41 by laser drill, also can the technology as punching press and mechanicalness boring form by other.The through hole 411 of reinforced layer 41 with and upper and lower surface by metal deposition to form conductive layer 413 thereon, be then patterned in the conductive layer 413 of upper and lower surface.Accordingly, through hole 411 has the shielding sidewall 415 of the side direction effectiveness that the semiconductor element 31 that is arranged in through hole 411 can be provided.For effective side direction electromagnetic shielding effect is provided, the shielding sidewall 415 of through hole 411 is preferably and extends upwardly to non-active 313 of semiconductor element 31 and at least overlap with it, and extends downward the active surface 311 of semiconductor element 31 and at least overlap with it.In this figure, reinforced layer 41 is in upward direction and downward direction and semiconductor element 31 coplines, and shielding sidewall 415 side direction of through hole 411 cover the side surface of semiconductor element 31.
The shielding sidewall 415 of semiconductor element 31 and through hole 411 is spaced apart by keeper 113.Keeper 113 also can near and four of lateral alignment through hole 411 shielding sidewalls 415, and the adhesive agent 18 under reinforced layer 41 is lower than keeper 113, thereby also can avoid any unnecessary displacement of reinforced layer 41 when solidifying adhesive agent 18.One connecting material (not shown) can make an addition between semiconductor element 31 and reinforced layer 41 to increase its rigidity.
Fig. 6 is laminated in the structure cutaway view on semiconductor element 31 and reinforced layer 41 in upward direction by the second insulating barrier 221 and metal level 22.The second insulating barrier 221 is between metal level 22 and semiconductor element 31, and between metal level 22 and reinforced layer 41, it is made that the second insulating barrier 211 can be epoxy resin, glass epoxy resin, polyimides and analog thereof, and conventionally have the thickness of 50 microns.Preferably, the first insulating barrier 211 and the second insulating barrier 221 are identical material.Metal level 22 shown in figure is for having the copper layer of 17 micron thickness, in exert pressure and high temperature under, the second insulating barrier 221 is by melting and compression, and further by putting on the downward pressure of metal level 22 and/or applying supporting bracket 15, upward pressure, in through hole 411, extend in the gap of 41 of semiconductor element 31 and reinforced layers.After the second insulating barrier 221 and metal level 22 are laminated on semiconductor element 31 and reinforced layer 41, solidify the second insulating barrier 221.Accordingly, as shown in Figure 6, the second insulating barrier 221 curing provides between metal level 22 and keeper 113, the mechanicalness of safety and firmness is connected between metal level 22 and semiconductor element 31 and between metal level 22 and reinforced layer 41.
Fig. 7 is the structure cutaway view with the first blind hole 213 and perforation 511.The first blind hole 213 extends through supporting bracket 511, the first insulating barrier 211 and adhesive agent 16, to appear the contact pad 312 of semiconductor element 31 in downward direction.The first blind hole 213 can form by various technology, and it comprises laser drill, electricity slurry (plasma) etching and micro-shadow technology, and conventionally has the diameter of 50 microns.Can use pulse laser to improve laser drill usefulness, or, metal light shield and laser beam can be used.For instance, can first etching copper coin to manufacture after a metal window illuminating laser beam again.Perforation 511 is to extend through in the vertical direction supporting bracket 15, the first insulating barrier 211, adhesive agent 18, reinforced layer 41, the second insulating barrier 221 and metal level 22.Perforation 511 can be holed and be formed by mechanicalness, also can as the electric paste etching of laser drill and wet type or non-wet type, form via other technologies.
Please refer to Fig. 8, the first wire 215 is formed on the first insulating barrier 211, its by deposition the first coating 21 ' in supporting bracket 15 and deposition enter in the first blind hole 213 and form, then supporting bracket 15 and first coating 21 ' of patterning on it.Or in the execution mode of the laminated substrate of some Flagless 15, the first insulating barrier 211 can directly be metallized to form the first wire 215.The first wire 215 is to extend from the first insulating barrier 211 in downward direction, extends laterally, and extend into the first blind hole 213 to form the first conductive blind hole 217 directly contacting with contact pad 312 in upward direction on the first insulating barrier 211.
As shown in Figure 8, the patterned conductive layer 413 of screening cover 224 and the first wire 215 and reinforced layer 41 is electrically connected, it by depositing the second coating 22 ' on metal level 22, and deposit articulamentum 513 and formation coating perforation 515 in perforation 511, and be electrically connected screening cover 224, patterned conductive layer 413 and the first wire 215.Similarly, if while being laminated on the second insulating barrier 221 without metal level 22 in previous steps, the second insulating barrier 221 also can directly be metallized to form screening cover 224.Screening cover 224 is to extend from the second insulating barrier 221 in upward direction, and extends laterally on the second insulating barrier 221, and in this figure, screening cover 224 is continuous metal level, and extends laterally to the peripheral edge of wiring board.In addition, articulamentum 513 shown in figure is hollow tubular, it is in side surface direction, to cover the sidewall of perforation 511, and vertical patterned conductive layer 413 to first wires 215 that extend with electric connection screening cover 224 and reinforced layer 41, and an insulating properties filler is optionally inserted the remaining space of perforation 511.Or when coating perforation 515 does not have for metal projection and in perforation 511 space that can fill insulating properties filler, articulamentum 513 can be filled perforation 511.Therefore, screening cover 224 can be electrically connected to by the first wire 215 and coating perforation 515 the ground connection contact pad of semiconductor element 31.And the shielding sidewall 415 of reinforced layer 41 can be electrically connected to by the first wire 215, coating perforation 515 and patterned conductive layer 413 the ground connection contact pad of semiconductor element 31.
The first coating 21 ', the second coating 22 ' and articulamentum 513 are preferably same material, and utilize identical method to deposit simultaneously and form, and have identical thickness.The first coating 21 ', the second coating 22 ' and articulamentum 513 can form single or multiple lift structure by various deposition techniques, and it comprises plating, electroless-plating, evaporation, sputter and combination thereof.For instance, its structure is first by this structure is immersed in activator solution, make insulating barrier and electroless copper produce catalyst and react, then using electroless-plating mode coating one thin copper layer as crystal seed layer, then with plating mode, the second bronze medal layer of desired thickness is formed on crystal seed layer.Or, on crystal seed layer, depositing before copper electroplating layer, this crystal seed layer can form the crystal seed layer film as titanium/copper by sputtering way.Once reach required thickness, can use various technology patterning coatings to form the first wire 215, it comprise wet etching, chemical etching, laser assisted etching and with the combination of etching light shield (not shown), to define the first wire 215.
For convenience of explanation, supporting bracket 15, the first coating 21 ', metal level 22, the second coating 22 ' and articulamentum 513 are to represent with simple layer, because copper is homogeneity coating, the boundary line of metal interlevel (all illustrating with dotted line) may be difficult for discovering even and cannot discover, yet between the first coating 21 ' and the first insulating barrier 211, between articulamentum 513 and the first insulating barrier 211, between articulamentum 513 and adhesive agent 18, between articulamentum 513 and the reinforced layer 41 and boundary line between articulamentum 513 and the second insulating barrier 221 is clearly visible.
According to more than, as shown in Figure 8, the wiring board 100 completing comprises keeper 113, semiconductor element 31, reinforced layer 41, two increasing layer circuit 201,202 and coating perforation 515.In this figure, first increases layer circuit 201 comprises the first insulating barrier 211 and the first wire 215, and a second increasing layer circuit 202 comprises the second insulating barrier 221 and screening cover 224.The first wire 215 is in upward direction, to extend into the first blind hole 213 directly to contact with contact pad 312 to form the first conductive blind hole 217, the first conductive blind holes 217.Screening cover 224 is to extend laterally on the second insulating barrier 221, and covers semiconductor element 31 completely in upward direction.Shielding sidewall 415 is in side surface direction flanked semiconductor element 31 and cover semiconductor element 31 completely in side surface direction.Coating perforation 515 is in fact to be shared by reinforced layer 41 and two increasing layer circuit 201,202, and extend through the first insulating barrier 211, adhesive agent 18, reinforced layer 41 and the second insulating barrier 221 in vertical direction, so that the electric connection between screening cover 224 and the first wire 215 and between shielding sidewall 415 and the first wire 215 to be provided.Therefore, shielding sidewall 415 and screening cover 224 are all electrically connected to the ground connection contact pad of semiconductor element 31 by the first increasing layer circuit 201 and coating perforation 515, and as semiconductor element 31 levels and vertical electromagnetic barrier.
[embodiment 2]
Fig. 9～12nd, according in another embodiment of the present invention, prepares the method cutaway view of another wiring board, and its wiring board comprises screening cover and the shielding sidewall of the ground connection contact pad that is electrically connected to semiconductor element via conductive blind hole.
For the object of brief description, any narration in embodiment 1 can be incorporated into same application part herein, and no longer repeats identical narration.
Fig. 9 is by the formed structure cutaway view of the same steps shown in Fig. 1～5, except the semiconductor element 31 that is arranged on dielectric layer 13 is to face dielectric layer 13 with its non-active 313, and keeper 113 is to extend beyond non-active 313 of semiconductor element 31 in upward direction.
Figure 10 is laminated in the structure cutaway view on semiconductor element 31 and reinforced layer 41 in upward direction by the first insulating barrier 211 and metal level 21.The first insulating barrier 211 is melted and compresses, and under pressure and high temperature, further extend into the gap of 41 of semiconductor element 31 and reinforced layers, be then cured to strengthen between metal level 21 and 31 of semiconductor elements, metal level 21 and keeper 113 and metal level 21 is connected with the mechanicalness of 41 of reinforced layers.
Figure 11 is the structure cutaway view that forms the first blind hole 213 and the second blind hole 223.The first blind hole 213 be in downward direction along stretching through metal level 21 and the first insulating barrier 211 to appear the contact pad 312 of semiconductor element 31, and the selected position that is revealed in the patterned conductive layer 413 of reinforced layer 41 upper surfaces.The second blind hole 223 is to extend through supporting bracket 15, dielectric layer 13 and adhesive agent 18 in downward direction, to be revealed in the selected position of the patterned conductive layer 413 of reinforced layer 41 lower surfaces.
Please refer to Figure 12, via deposition the first coating 21 ', on metal level 21, and deposition enters the first blind hole 213, then patterned metal layer 21 with and on the first coating 21 ' to form the first wire 215 on the first insulating barrier 211.The first wire 215 is to extend from the first insulating barrier 211 in upward direction, and extend laterally on the first insulating barrier 211, and in downward direction, extend into the first blind hole 213 and directly contact with the contact pad 312 of semiconductor element 31 and the patterned conductive layer 413 of reinforced layer 41 to form the first conductive blind hole 217, the first conductive blind holes 217.Therefore, the first wire 215 can provide the ground connection of 415 of the shielding sidewalls of the signal route of semiconductor element 31 and the ground connection contact pad of semiconductor element 31 and reinforced layer 41.
As shown in figure 12, screening cover 224 is electrically connected the patterned conductive layer 413 of reinforced layer 41, its by deposition the second coating 22 ' in supporting bracket 15 and deposition enter dielectric layer 13 the second blind hole 223, to form the second conductive blind hole 227 being electrically connected with patterned conductive layer 413, wherein, dielectric layer 13 is regarded as the second insulating barrier 221.Screening cover 224 is to extend from the second insulating barrier 221 in downward direction, extends laterally, and by the second conductive blind hole 227, conductive layer 413 and the first wire 215, be electrically connected to the ground connection contact pad of semiconductor element 31 on the second insulating barrier 221.
Accordingly, as shown in Figure 12, the wiring board 200 completing comprises keeper 113, semiconductor element 31, reinforced layer 41 and two increasing layer circuit 201,202.In this figure, a first increasing layer circuit 201 is to cover keeper 113, semiconductor element 31 and reinforced layer 41 in upward direction, and comprise the first insulating barrier 211 and the first wire 215, and the second insulating barrier 202 is to cover keeper 113, semiconductor element 31 and reinforced layer 41 in downward direction, and comprise the second insulating barrier 221, screening cover 224 and the second conductive blind hole 227.First increases the ground connection of shielding sidewall 415 that layer circuit 201 provides the signal route of semiconductor element 31 by the first wire 215 and be provided as the reinforced layer 41 of horizontal barrier.Second increases layer circuit 202 provides screening cover 224, as the vertical barrier of semiconductor element 31, and by the second conductive blind hole 227, and the ground connection between conductive layer 413 and screening cover 224 is provided.
[embodiment 3]
Figure 13～Figure 15 in another execution mode, comprises the preparation method's cutaway view that is electrically connected the patterned conductive layer of a screening cover and a reinforced layer by conduction ditch according to the present invention.
For the object of brief description, any narration in embodiment 1 can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 13 is the structure cutaway view by the step manufacturing shown in Fig. 9～10.
Figure 14 and Figure 14 A be respectively there is the first blind hole 213, groove opening 222 and perforation 511 structure cutaway view and upward view.The first blind hole 213 extends through the first insulating barrier 211 and metal level 21, to appear the contact pad 312 of semiconductor element 31 in upward direction.Groove opening 222 extends through supporting bracket 15, the second insulating barrier 221 and adhesive agent 18, to appear the selected position of the conductive layer 413 of patterning in downward direction.Perforation 511 extends through supporting bracket 15, the second insulating barrier 221, adhesive agent 18, reinforced layer 41, the first insulating barrier 211 and metal level 21, and spaced apart with the conductive layer 413 of reinforced layer 41.As shown in Figure 14 A, groove opening 222 is carried out mechanicalness cutting along four lines of cut of the patterned conductive layer 413 of reinforced layer 41, through supporting bracket 15, the second insulating barrier 221 and adhesive agent 18, forms.
With reference to Figure 15, via deposition the first coating 21 ' on metal level 21 and enter the first blind hole 213, and then patterned metal layer 21 with and on the first coating 21 ' and on the first insulating barrier 211, form the first wire 215.The first wire 215 is to extend from the first insulating barrier 211 in upward direction, and extends laterally on the first insulating barrier 211, and extends into the first blind hole 213 to form the first conductive blind hole 217 directly contacting with contact pad 312 in downward direction.And as shown in figure 15, screening cover 224 is electrically connected to patterned conductive layer 413 and the first wire 215, it is via depositing the second coating 22 ' in supporting bracket 15, and enter groove opening 222 to form the conduction ditch 228 being electrically connected with screening cover 224, and patterned conductive layer 413, and in perforation 511, deposit articulamentum 513 so that the coating perforation 515 being electrically connected with screening cover 224 and the first wire 215 to be provided.
Accordingly, as shown in figure 15, in formed circuit board 300, the electric connection between its shielding sidewall 415 and screening cover 224 is provided by conduction ditch 228.In this figure, a first increasing layer circuit 201 is to cover keeper 113, semiconductor element 31 and reinforced layer 41 in upward direction, and comprise the first insulating barrier 211 and the first wire 215, and a second increasing layer circuit 202 is to cover keeper 113, semiconductor element 31 and reinforced layer 41 in downward direction, and comprise the second insulating barrier 221, screening cover 224 and conduction ditch 228.Screening cover 224 is electrically connected to the ground connection contact pad of semiconductor element 31 by coating 515 and first wire 215 of boring a hole, and the shielding sidewall 415 of reinforced layer 41 is electrically connected to the ground connection contact pad of semiconductor element 31 by patterned conductive layer 413, conduction ditch 228, screening cover 224, coating perforation the 515 and first wire 215.
[embodiment 4]
Figure 16～21st, according in another embodiment of the invention, the preparation method's of another circuit board schematic sectional view, wherein, circuit board has the two layer circuit that increase that comprise extra insulation layer and wire, and is electrically connected to another increasing layer circuit via coating perforation.
For the object of brief description, any narration in embodiment 1 can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 16 is the formed structure cutaway view of the preparation process shown in Fig. 1～6.
Figure 17 is the structure cutaway view with the first blind hole 213.The first blind hole 213 is to extend through supporting bracket 15, the first insulating barrier 211 and adhesive agent 16, to appear the contact pad 312 of semiconductor element 31 in downward direction.
Please refer to Figure 18, by depositing the first coating 21 ' in supporting bracket 15 and deposition enters the first blind hole 213, then patterning supporting bracket 15 with and on the first coating 21 ' 211 to form the first wires 215 on the first insulating barrier.The first wire 215 is to extend from the first insulating barrier 211 in downward direction, extends laterally, and extend into the first blind hole 213 to form the first conductive blind hole 217 directly contacting with contact pad 312 in upward direction on the first insulating barrier 211.Then, remove the selected part of metal level 22, and the remainder of metal level 22 is the shielding sidewalls 224 as semiconductor element 31.
Figure 19 is the structure cutaway view with the 3rd insulating barrier 231 and the 4th insulating barrier 241.The 3rd insulating barrier 231 is to cover the first insulating barrier 211 and the first wire 215, the four insulating barriers 214 are to cover the second insulating barrier 221 and screening cover 224 in upward direction in downward direction.
Figure 20 is the structure cutaway view with the 3rd blind hole 223 and perforation 511.The 3rd blind hole 223 extends through the 3rd insulating barrier 231, and in alignment with the selected position of the first wire 215.Perforation 511 is to extend through in the vertical direction the 4th insulating barrier 241, screening cover 224, the second insulating barrier 221, reinforced layer 41, adhesive agent 18, the first insulating barrier 211, the first wire 215 and the 3rd insulating barrier 231.
With reference to Figure 21, privates 235 and privates 245 are via metal deposition and patterning and be formed at respectively on the 3rd and the 4th insulating barrier 231,241.Privates 235 is to extend from the 3rd insulating barrier 231 in downward direction, extends laterally, and extend into the 3rd blind hole 233 to form the 3rd conductive blind hole 237 being electrically connected with the first wire 215 in upward direction on the 3rd insulating barrier 231.Privates 245 are to extend from the 4th insulating barrier 241 in upward direction, and extend laterally on the 4th insulating barrier 241.In addition, articulamentum 513 is deposited on perforation 511 inwall to form coating perforation 515.
Accordingly, as shown in figure 21, the circuit board 400 completing comprises keeper 113, semiconductor element 31, reinforced layer 41, two increasing layer circuit 201,202 and coating perforation 515.In this figure, first increases layer circuit 201 comprises the first insulating barrier 211, the first wire 215, the 3rd insulating barrier 231 and privates 235, and a second increasing layer circuit 202 comprises the second insulating barrier 221, screening cover 224, the 4th insulating barrier 241 and privates 245.Coating perforation 515 is by reinforced layer 41, the first increasing layer circuit 201 and second, to increase layer circuit 202 to share substantially, and the electric connection between privates 235 and privates 245 is provided.Semiconductor element 31 is fixed on the first insulating barrier 211, and is reinforced shielding sidewall 415 encirclements of layer 41.Shielding sidewall 415 increases layer circuit 201 via patterned conductive layer 413, coating perforation 515 and first and is electrically connected to the ground connection contact pad of semiconductor element 31, and can be used as the horizontal barrier of semiconductor element 31.Screening cover 224 is electrically connected to the ground connection contact pad of semiconductor element 31 via coating perforation the 515 and first increasing layer circuit 201, and can be used as the vertical barrier of semiconductor element 31.
[embodiment 5]
Figure 22～28th, according to an embodiment of the present invention in, preparation method's cutaway view of preparing a wiring board, this wiring board comprises that positioning piece, a screening cover, semiconductor element, a reinforced layer, increase layer circuit, a plurality of conduction ditch, a plurality of terminal and a plurality of coating perforation.
For the object of brief description, any narration in embodiment 1 can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 22 has keeper 113 to be formed at the structure cutaway view on metal level 12.Keeper 113 can be patterned and be deposited on metal level 12 via various technology, and it comprises plating, electroless-plating, evaporation, sputter and combination thereof merging use photoetching process and forms.Metal level 12 in figure is for having the copper layer of 35 micron thickness, and the keeper in figure is the continuity copper bar with rectangle frame, and has the thickness of 35 microns.
Figure 23 is for being used adhesive agent 16 that semiconductor element 31 is arranged to the structure cutaway view on metal level 12, and wherein, adhesive agent 16 is contacts between metal level 12 and semiconductor element 31.Semiconductor element 31 comprises that having contact pad 312 arranges active surface 311 thereon, and non-active 313, and semiconductor element 31 is to be attached on metal level 12, and its non-active 313 faces metal level 12.Keeper 113 is to extend from metal level 12 in upward direction, and extends beyond non-active 313 of semiconductor element 31, and the configuration guiding element of usining as semiconductor element 31 near the peripheral edge of semiconductor element 31.Therefore, semiconductor element 31 can accurately be arranged on precalculated position.
Figure 24 and Figure 25 are used adhesive agent 18 that reinforced layer 41 is arranged to the step cutaway view on metal level 12, adhesive agent 18 contacts and between metal level 12 and reinforced layer 41.The through hole 411 of reinforced layer 41 is aimed at and inserted to semiconductor element 31 and keeper 113, and the shielding sidewall 415 of through hole 411 separates to come by keeper 113 and 31 of semiconductor elements.Keeper 113 four sides close and aligned through holes 411 shields sidewall 415, thus the unnecessary displacement of reinforced layer 41 before can avoiding adhesive agent 18 to solidify completely.In this execution mode, reinforced layer 41 is in upward direction and downward direction and semiconductor element 31 coplines.
Figure 26 is the structure cutaway view with the first insulating barrier 211 and metal level 21.The first insulating barrier 211 is between between metal level 21 and semiconductor element 31 and between metal level 21 and reinforced layer 41, and further extends into the gap of 41 of semiconductor element 31 and reinforced layers.
Figure 27 is the structure cutaway view with the first blind hole 213, groove opening 222 and perforation 511.The first blind hole 213 extends through metal level 21 and the first insulating barrier 211, and in alignment with the contact pad 312 of semiconductor element 31 and the selected position of conductive layer 413.Groove opening 222 extends through metal level 12 and adhesive agent 18, and in alignment with the selected position of conductive layer 413.Perforation 511 is to extend through in the vertical direction metal level 12, adhesive agent 18, reinforced layer 41, the first insulating barrier 211 and metal level 21.
Please refer to Figure 28, via deposition the first coating perforation 21 ' on metal level 21 and deposition enter the first blind hole 213, then patterned metal layer 21 and the first coating 21 ' thereon and on the first insulating barrier 211, form the first wire 215.The first wire 215 provides the ground connection of the signal route of semiconductor element 31 and the shielding sidewall 415 of reinforced layer 41 via the first conductive blind hole 217 directly contacting with patterned conductive layer 413.
As shown in figure 28, screening cover 224 is electrically connected to conductive layer 413 by conduction ditch 228 and terminal 229, wherein conducts electricity ditch 228 and terminal 229 to be bored a hole and 515 be electrically connected to the first wire 215 by coating.Screening cover 224 and terminal 229 by deposition the second coating 22 ' on metal level 12, then patterned metal layer 12 with and upper the second coating 22 ' and forming.Screening cover 224 is to cover semiconductor element 31 and keeper 113 in downward direction, and is electrically connected to patterned conductive layer 413 via conduction ditch 228.Terminal 229 is screening cover 224 dorsad, and is electrically connected to the first wire 215 via coating perforation 515.Coating perforation 515 via deposition articulamentum 513 in perforation 511 and form.
Accordingly, as shown in figure 28, the circuit board 500 completing comprises keeper 113, screening cover 224, semiconductor element 31, reinforced layer 41, increases layer circuit 203, conduction ditch 228, terminal 229 and coating perforation 515.In this figure, increase layer circuit 203 and comprise the first insulating barrier 211 and the first wire 215, and coating perforation 515 is shared by reinforced layer 41, increasing layer circuit 203 and terminal 226.Semiconductor element 31 is fixed on screening cover 224, and it is coated in side surface direction, to be reinforced layer 41 shielding sidewall 415 side direction.Shielding sidewall 415 is electrically connected to the ground connection contact pad of semiconductor element 31 via increasing layer circuit 203, and can be used as the horizontal barrier of semiconductor element 31.Screening cover 224 is electrically connected to the ground connection contact pad of semiconductor element 31 via conduction ditch 228, conductive layer 413 and increasing layer circuit 203 can be used as the vertical barrier of semiconductor element 31.Coating perforation 515 provides and has increased the electric connection between layer circuit 203 and terminal 229, and terminal 229 is to extend beyond reinforced layer 41 in downward direction.
[embodiment 6]
Figure 29～34th, according to the present invention, again in an execution mode, preparation is the method cutaway view of a wiring board again, and this wiring board comprises positioning piece, a screening cover, semiconductor element, a reinforced layer, two increasing layer circuit and a plurality of coating perforation.
For the object of brief description, any narration in above-described embodiment can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 29 is the formed section of structure of the step shown in Figure 22～26.
Figure 30 is the structure cutaway view with the first blind hole 213.The first blind hole 213 extends through metal level 21 and the first insulating barrier 211 to appear the contact pad 312 of semiconductor element 31.
With reference to Figure 31, the first wire 215 via deposition the first coating 21 ' on metal level and deposition enter the first blind hole 213, then patterned metal layer 21 with and on the first coating 21 ' and form.In addition, remove the selected part on metal level 12, and the remainder of metal level 12 as screening cover 224 so that the electromagnetic barrier effect that semiconductor element 31 is vertical to be provided.
Figure 32 is the structure cutaway view with the second insulating barrier 221 and the 3rd insulating barrier 231.The second insulating barrier 221 is to cover screening cover 224 in downward direction.The 3rd insulating barrier 231 is to cover the first insulating barrier 211 and the first wire 215 in upward direction.
Figure 33 is the structure cutaway view with the second blind hole 223, the 3rd blind hole 233 and perforation 511.The second blind hole 223 extends through the second insulating barrier 221, and in alignment with the selected position of screening cover 224.The 3rd blind hole 223 extends through the 3rd insulating barrier 231, and in alignment with the selected position of the first wire 215.Perforation 511 is to extend through in the vertical direction the second insulating barrier 221, screening cover 224, adhesive agent 18, reinforced layer 41, the first insulating barrier 211 and the 3rd insulating barrier 231.
Please refer to Figure 34, the second wire 225 and privates 235 are formed at respectively on the second and the 3rd insulating barrier 221,231 via plated metal and patterning.The second wire 225 is to extend from the second insulating barrier 221 in downward direction, extends laterally, and extend into the second blind hole 223 to form the second conductive blind hole 227 being electrically connected with screening cover 224 in upward direction on the second insulating barrier 221.Privates 235 is to extend from the 3rd insulating barrier 231 in upward direction, extends laterally, and extend into the 3rd blind hole 233 to form the 3rd conductive blind hole 237 contacting with the first wire 215 in downward direction on the 3rd insulating barrier 231.In addition the inwall that, articulamentum 513 is deposited on perforation 511 is to form coating perforation 515.
Accordingly, as shown in figure 34, the wiring board 600 completing comprises keeper 113, screening cover 224, semiconductor element 31, reinforced layer 41, two increasing layer circuit 201,202 and coating perforation 515.In this figure, first increases layer circuit 201 comprises the first insulating barrier 211, the first wire 215, the 3rd insulating barrier 231 and privates 235, and a second increasing layer circuit 202 comprises the second insulating barrier 221 and the second wire 225.Coating perforation 515 substantially by reinforced layer 41, screening cover 224, first, increases layer circuit 201 and the second increasing layer circuit 202 shared, and provides the first increasing layer circuit 201 and second to increase the electric connection of 202, layer circuit.Semiconductor element 31 is fixed on screening cover 224, and is reinforced shielding sidewall 415 flanked of layer 41.Shielding sidewall 415 increases layer circuit 201 via the conductive layer 413 of reinforced layer 41, coating perforation 515 and first and is electrically connected to the ground connection contact pad of semiconductor element 31, and as the horizontal barrier of semiconductor element 31.Screening cover 224 increases layer circuit 201 via the second increasing layer circuit 202, coating perforation 515 and first and is electrically connected to the ground connection contact pad of semiconductor element 31, and as the vertical barrier of semiconductor element 31.
[embodiment 7]
Figure 35～52nd, according in another embodiment of the present invention, prepares the method schematic sectional view of another wiring board, and this wiring board is the screening cover with the through hole that inserts reinforced layer.
For the object of brief description, any narration in above-described embodiment can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 35 is the stepped construction cutaway view that comprises metal level 12, dielectric layer 13 and supporting bracket 15.Dielectric layer 13 is between metal level 12 and supporting bracket 15.
Figure 36 forms the structure cutaway view of keeper 113 on metal level 12, keeper 113 can be patterned and be deposited on metal level 12 via various technology, and it comprises plating, electroless-plating, evaporation, sputter and combination thereof merging use photoetching process and forms.
Figure 37 has the structure cutaway view that screening cover 224 is arranged at dielectric layer 13.The selected position that screening cover 224 can remove metal level 12 by photoetching process or wet etching forms, and screening cover 224 is corresponding to a precalculated position of placing semiconductor element, and can be used as vertical electromagnetic barrier.
Figure 38 is used adhesive agent 16 that semiconductor element 31 is arranged to the structure cutaway view on screening cover 224, adhesive agent 16 contacts and between screening cover 224 and semiconductor element 31.Semiconductor element 31 comprises having contact pad 312 active surface 311 thereon, and one non-active 313, and semiconductor element 31 is face the kenel of screening cover 224 and be attached on screening cover 224 with non-active 313.Keeper 113 is to extend at upward direction self-shileding lid 224, and extends beyond non-active 313 of semiconductor element 31, and near the peripheral edge of semiconductor element 31, the configuration guiding element of usining as semiconductor element 31.
Figure 39 is used adhesive agent 18 that reinforced layer 41 is arranged to the structure cutaway view on dielectric layer 13.Semiconductor element 31, keeper 113 and screening cover 224 are aimed at the through hole 411 of reinforced layer 41 and insert in the through hole 411 of reinforced layer 41, and reinforced layer 41 is arranged on the dielectric layer 13 appearing by adhesive agent 18.In this figure, the peripheral edge of screening cover 224 is the four sides shielding sidewalls 415 near through hole 411, and lateral alignment is in the four sides of through hole 411 shielding sidewall 415, and the adhesive agent 18 under reinforced layer 41 is lower than screening cover 224, thereby can avoid adhesive agent 18 in solidifying former why not necessary displacement.Or, in some execution modes, reinforced layer 41 can be attached on the selected position of the dielectric layer 13 that appears and screening cover 224, screening cover 224 extends beyond the region of semiconductor element 31 bottoms, and keeper 113 can be avoided the unnecessary displacement of reinforced layer 41, keeper 113 is near the four sides shielding sidewall 415 of through hole 411, and lateral alignment is in the four sides of through hole 411 shielding sidewall 415.Or, can add a connecting material (not shown) between semiconductor element 31 and reinforced layer 41 to increase its rigidity.
Figure 40 is that the first insulating barrier 211 is formed at the structure cutaway view on semiconductor element 31 and reinforced layer 41 in upward direction.The first insulating barrier 211 is to cover semiconductor element 31 and reinforced layer 41 in upward direction, and extends into the gap of 41 of reinforced layers in semiconductor element 31 and through hole 411.
Figure 41 is the structural representation with the first blind hole 213, the second blind hole 223 and perforation 511.The first blind hole 213 extends through the first insulating barrier 211 to appear the contact pad 312 of semiconductor element 31 and the selected position of conductive layer 413.The second blind hole 223 extends through supporting bracket 15 and dielectric layer 13 to appear the selected position of screening cover 224 and conductive layer 413, and wherein, dielectric layer 13 is regarded as the second insulating barrier 221.Perforation 511 is to extend through in the vertical direction the first insulating barrier 211, reinforced layer 41, adhesive agent 18, dielectric layer 13 and supporting bracket 15.
With reference to Figure 42, the first wire 215 via deposition the first coating 21 ' on the first insulating barrier 211 and deposition enter the first blind hole 213, the person's of connecing patterning the first coating 21 ' and forming.Meanwhile, the second wire 225 via deposition the second coating 22 ' in supporting bracket 15 and deposition enter the second blind hole 223, then patterning supporting bracket 15 with and on the second coating 22 '.Figure 42 has also illustrated deposition articulamentum 513 and to form coating, bored a hole 515 on the inwall of perforation 511.
Accordingly, as shown in figure 42, the wiring board 700 completing comprises keeper 113, screening cover 224, semiconductor element 31, reinforced layer 41, two increasing layer circuit 201,202 and coating perforation 515.In this figure, first increases layer circuit 201 comprises the first insulating barrier 211 and the first wire 215, and a second increasing layer circuit 202 comprises the second insulating barrier 221 and the second wire 225.The first wire 215 is to extend from the first insulating barrier 211 in upward direction, and extends into the first blind hole 213 in downward direction, to form the first conductive blind hole 217 being electrically connected with contact pad 312 and conductive layer 413.The second wire 225 is to extend from the second insulating barrier 221 in downward direction, and extends into the second blind hole 223 to form the second conductive blind hole 227 being electrically connected with screening cover 224 and conductive layer 413 in upward direction.Shielding sidewall 415 increases layer circuit 201 via conductive layer 413 and first and is electrically connected to the ground connection contact pad of semiconductor element 31.Screening cover 224 is electrically connected to the ground connection contact pad of semiconductor element 31 via the second increasing layer circuit 202, conductive layer 413 and the first increasing layer circuit 201.Coating perforation 515 is by reinforced layer 41, the first increasing layer circuit 201 and second, to increase layer circuit 202 to share substantially, and the electric connection between the first wire 215 and the second wire 225 is provided.
[embodiment 8]
Figure 43～45th, according to an embodiment of the present invention in, prepare the method profile of three-dimensional stacked group of body, this three-dimensional stacked group of body comprises a plurality of with in the face of the stacking wiring board of the back of the body (face-to-back) kenel.
For the object of brief description, any narration in above-described embodiment can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 43 is at two adjacent 110,120 structure cutaway views with inner-dielectric-ayer 261 of wiring board.Wiring board 110,120 is prepared by the same steps shown in Fig. 1～8, and spaced apart by the peripheral edge of wiring board 110,120 except screening cover 224, and the second wire 225 is further formed on the second insulating barrier 221.Wiring board 110,120 is vertically stacking and use inner-dielectric-ayer 261 to be connected to each other, inner-dielectric-ayer 261 contacts and between second insulating barrier 221/ screening cover 224/ second wire 225 and the first insulating barrier 211/ first wire 215 of wiring board 120 of wiring board 110.In addition, wiring board 110,120 has respectively the 3rd insulating barrier 231 and the 4th insulating barrier 241.The 3rd insulating barrier 231 is in downward direction, to cover the first insulating barrier 211 and first wire 215 of wiring board 110, and comprises the 3rd blind hole 233 in alignment with the selected position of the first wire 215.The 4th insulating barrier 241 is in upward direction, to cover and contact the second insulating barrier 221, screening cover 224 and second wire 225 of wiring board 120.
Figure 44 is the structure cutaway view with perforation 512.Perforation 512 is to extend through in the vertical direction wiring board 110,120 and inner-dielectric-ayer 261.
Please refer to Figure 45, wiring board 110,120 has respectively privates 235 and privates 245.Privates 235 is to extend from the 3rd insulating barrier 231 in downward direction, and on the 3rd insulating barrier 231, side direction is prolonged treasure, and extends into the 3rd blind hole 233 to form the 3rd conductive blind hole 237 being electrically connected with the first wire 215.Privates 245 are to extend from the 4th insulating barrier 241 in upward direction, and extend laterally on the 4th insulating barrier 241.In addition, as shown in figure 45, in perforation 512, deposit articulamentum 514 to form coating perforation 516.Accordingly, the stacked group body 101 completing comprises a plurality of wiring boards 110,120, inner-dielectric-ayer 261 and coating perforation 516.Each wiring board 110,120 all comprises that keeper 113, semiconductor element 31, reinforced layer 41, first increase layer circuit 201, second and increase layer circuit 202 and coating perforation 515.The shielding sidewall 415 of reinforced layer 41 and screening cover 224 can bore a hole 515 and ground connection contact pad, the coating perforation 515 that is electrically connected to semiconductor element is electrically connected to conductive layer 413 and screening cover 224 via coating.Coating perforation 516 is shared by wiring board 110,120 substantially, and extends through inner-dielectric-ayer 261 and wiring board 110,120 so that the electric connection between wiring board 110,120 to be provided.
[embodiment 9]
Figure 46～48th, according in another embodiment of the present invention, prepares the method profile of another three-dimensional stacked group of body, and this three-dimensional stacked group of body comprises a plurality of with the stacking wiring board of back-to-back (back-to-back) kenel.
For the object of brief description, any narration in above-described embodiment can be incorporated into same application part herein, and no longer repeats identical narration.
Figure 46 is at two adjacent 130,140 structure cutaway views with inner-dielectric-ayer 261 of wiring board.Wiring board 130,140 is with identical shown in Figure 29, and except removing the selected position of metal level 12, and the remainder of metal level 12 is as screening cover 224.Wiring board 130,140 is vertically stacking with back-to-back form, and uses inner-dielectric-ayer 261 to be bonded to each other, and inner-dielectric-ayer 261 contacts between wiring board 130,140 and with the screening cover 224 of each wiring board 130,140.
Figure 47 is the structure cutaway view with the first blind hole 213 and perforation 512.The first blind hole 213 extends through metal level 21 and the first insulating barrier 211, to appear the contact pad 312 of the semiconductor element 31 of each wiring board 130,140.Perforation 512 is in the vertical direction through wiring board 130,140 and inner-dielectric-ayer 261.
With reference to Figure 48, each wiring board 130,140 all has by depositing the first coating 21 ' on metal level 21 and deposition enters the first blind hole 213, then patterned metal layer 21 with and on formed the first wire 215 of the first coating 21 '.The first wire 215 vertically extends from the first insulating barrier 211, extends laterally, and extend into the first blind hole 213 with the first conductive blind hole 217 of contact pad 312 electric connections of formation and semiconductor element 31 on the first insulating barrier 211.Same, as shown in figure 48, the articulamentum 514 that is deposited on perforation 512 forms coating perforation 516.Accordingly, the stacked group body 102 completing comprises wiring board 130,140, inner-dielectric-ayer 261 and coating perforation 516.Each wiring board 130,140 comprises keeper 113, screening cover 224, semiconductor element 31, reinforced layer 41 and an increasing layer circuit 203.The shielding sidewall 415 of reinforced layer 41 and screening cover 224 are electrically connected to the ground connection contact pad of semiconductor element 31 by the coating perforation 516 with conductive layer 413 and screening cover 224 electric connections.Inner-dielectric-ayer 261 and wiring board 130,140 are shared, and extended through to coating perforation 516 substantially so that the electric connection of 130,140 of wiring boards to be provided by wiring board 130,140.
Above-mentioned wiring board and three-dimensional stacked group of body are only illustrative example, and the present invention still can realize by other various embodiments.In addition, above-described embodiment can be based on design and the consideration of reliability, and being mixed with each other collocation is used or used with other embodiment mix and match.Wiring board can comprise the screening cover of a plurality of array sequences and have the through hole of shielding sidewall, for a plurality of semiconductor elements side by side; And increase layer circuit and can comprise extra lead, to hold extra semiconductor element, shielding sidewall and screening cover.In like manner, wiring board can comprise many group keepers to hold extra semiconductor element.
Semiconductor element can be and encapsulates or unpackaged chip.In addition, this semiconductor element can be bare chip or wafer-level packaging chip (wafer level packaged die) etc.Shielding sidewall in keeper, screening cover and through hole can be customized to hold single semiconductor element, for instance, the pattern of keeper can be square or rectangle so that same or similar with the shape of single semiconductor element.In like manner, screening cover also customizable with same or similar with the shape of single semiconductor element.
In this article, to mean element be one-body molded (forming single individuality) or be in contact with one another (each other continuously every or do not separate) to " adjacency " word.For example, contact pad is adjacent to the first wire, but is not adjacent to the second wire.
" overlapping " word means the periphery that is positioned at top and extends a lower element." overlapping " comprises and extends the inside and outside of this periphery or be seated in this periphery.For example, in the first increasing layer circuit face during towards upward direction, first increases layer circuit is overlapped in semiconductor element, this is can run through the first increasing layer circuit and semiconductor element because of an imaginary vertical line simultaneously, no matter first increases between layer circuit and semiconductor element whether have the element (as: adhesive agent) that another is run through by this imagination vertical line equally, no matter and also whether have another imaginary vertical line only to run through the first increasing layer circuit and do not run through semiconductor element (periphery of semiconductor element is outer).Similarly, first increases layer circuit is overlapped in reinforced layer, and reinforced layer is overlapping by the first increasing layer circuit.In addition, " overlapping " and " be positioned at top " synonym, " superimposed " with " being positioned at below " synonym.
" contact " word means direct contact.For example, the contact pad of the first conductive blind hole contact semiconductor element, but the second conductive blind hole contact pad of contact semiconductor element not.
" covering " word refers to not exclusively and completely cover in vertical and/or side surface direction.For example, in the first increasing layer circuit face, under the state of upward direction, whether first increases layer circuit covers semiconductor element in upward direction, no matter there is another element (as: adhesive agent) to increase between layer circuit at semiconductor element and first.
" layer " word comprises patterning and non-patterned layer body.For example, when metal level is arranged on dielectric layer, metal level can be the not flat board of photoetching and Wet-type etching of a blank.In addition, " layer " can comprise a plurality of overlapping layers.
The words such as " opening ", " through hole " and " perforation " refer to together perforated holes.For example, keeper is from dielectric layer when upward direction is extended, and semiconductor element is inserted in the through hole of reinforced layer, and manifests in reinforced layer in upward direction.
" insertion " word means interelement relatively moving.For example, " semiconductor element is inserted in through hole " no matter refer to whether reinforced layer moves towards reinforced layer for maintaining static semiconductor element; Or semiconductor element maintains static and is moved towards semiconductor element by reinforced layer; Or semiconductor element and reinforced layer closing each other.In addition, whether " semiconductor element is inserted in (or extending to) through hole ", no matter run through (penetrate and pass) through hole or do not run through (penetrate but do not pass) through hole.
" aligning " word means interelement relative position, and whether no matter keep at a distance each other or adjacency between element, or an element inserts and extends in another element.For example, when imaginary horizontal line runs through keeper and semiconductor element, keeper is in alignment with semiconductor element, no matter whether there is the element that other are run through by imaginary line between keeper and semiconductor element, no matter and whether there is another and run through semiconductor element but do not run through the imaginary vertical line of keeper or another runs through keeper but does not run through the imaginary vertical line of semiconductor element.Similarly, the first blind hole is in alignment with the contact pad of semiconductor element, and semiconductor element and keeper are in alignment with through hole.
The width that " close " word means interelement gap is no more than maximum tolerance interval.General knowledge as known in the art, when the gap between semiconductor element and keeper is narrow not, because causing the site error of semiconductor element, the lateral displacement of semiconductor element in gap may surpass acceptable worst error restriction, site error once semiconductor element surpasses greatest limit, can not use laser beam to aim at contact pad, and cause semiconductor element and increase the electric connection mistake between layer circuit.Therefore, according to the size of the contact pad of semiconductor element, can be via trial and error pricing to confirm the maximum tolerance interval in the gap between semiconductor element and keeper in those skilled in the art, thus the electric connection mistake between semiconductor element and keeper avoided.Thus, the term of " keeper is near the peripheral edge of semiconductor element " refers to that the peripheral edge of semiconductor element and the gap between keeper are too narrow to is enough to prevent that the site error of semiconductor element from surpassing acceptable worst error restriction.
" setting ", " stacked ", " adhering to " and " attaching " language comprise with single or multiple support component between contact and noncontact.For example, semiconductor element is arranged on screening cover, no matter this semiconductor element actual contact screening cover or be separated by with an adhesive agent with screening cover.
" electric connection " word means direct or indirect electric connection.For example, coating perforation provides the electric connection of the first wire, no matter whether its coating perforation is in abutting connection with the first wire or be electrically connected to the first wire via privates.
" top " word means to extend upward, and comprises adjacency and non-adjacent element and overlapping and non-overlapped element.For example, when the first increasing layer circuit face downward to time, keeper just extends thereon, in abutting connection with the first insulating barrier, also from the first insulating barrier projection, goes out.
" " word means to downward-extension, and comprises adjacency and non-adjacent element and overlapping and non-overlapped element in below.For example, the first increasing layer circuit face downward to time, first increases layer circuit extends semiconductor element below in downward direction, no matter whether first increase layer circuit in abutting connection with this semiconductor element.
" the first vertical direction " and " the second vertical direction " not depends on the orientation of wiring board, and all personages who is familiar with the technology of this area can understand the direction of its actual indication easily.For example, the active surface of semiconductor element faces the first vertical direction, and the non-active face of semiconductor element faces the second vertical direction, and whether this and wiring board are inverted irrelevant.Similarly, keeper is aimed at semiconductor element along a lateral plane " side direction ", and whether this and wiring board are inverted, rotate or are tilted and have nothing to do.Therefore, this first and second vertical direction is opposite each other and perpendicular to side surface direction, and the element of lateral alignment is to intersect at the lateral plane perpendicular to first and second vertical direction.Moreover when the active surface of semiconductor element faces downward direction, the first vertical direction is downward direction, the second vertical direction is upward direction; When the non-active face of semiconductor element faces upward direction, the first vertical direction is upward direction, and the second vertical direction is downward direction.
Wiring board of the present invention and use its three-dimensional stacked group of body to there is multiple advantages.For example, keeper can be used as the guiding element of configuration accurately of the semiconductor element of conductively-closed.Because semiconductor element is bonded to and is increased layer circuit or screening cover by adhesive agent, during curing can avoid any displacement that refluxes and cause because of configuration error or adhesive agent.Therefore, the reliability of wiring board and three-dimensional stacked group of body is high, price is plain and be extremely applicable to volume production.The shielding sidewall of reinforced layer and screening cover shield as level or the vertical EMI of semiconductor element respectively, to reduce electromagnetic interference.Owing to increasing the high routing capability of layer circuit, the signal route being provided by increasing layer circuit is beneficial to high I/O value and high performance application.Reinforced layer provides increasing layer circuit and the semiconductor element mechanical support being packaged in wiring board.Wiring board and use its reliability of three-dimensional stacked group of body high, price is plain and be extremely applicable to volume production.
The manufacture method of this case has height applicability, and is in conjunction with the electrically connect and the mechanicalness connecting technology that use various maturations in unique, progressive mode.In addition, the manufacture method of this case does not need expensive tool to implement.Therefore,, compared to conventional package technology, this manufacture method is improving yield, yield, usefulness and cost benefit significantly.
Embodiment described herein is the use as illustration, and wherein said embodiment may simplify or omit element or the step that the art has been known, in order to avoid fuzzy feature of the present invention.Similarly, graphic clear for making, graphic repetition or non-essential element and the component symbol of also may omitting.
Those skilled in the art for embodiment as herein described when thinking easily and the mode of various variation and modification.For example, the content of aforesaid material, size, shape, size, step and the order of step are all only example.Those skilled in the art are within the spirit and principles in the present invention all, any modification of making, are equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (13)

1. a wiring board with embedded element, built-in keeper and electromagnetic barrier, comprising:
Semiconductor element, it comprises an active surface and contrary with this active surface one non-active, on this active surface, have a plurality of contact pads, wherein this active surface faces one first vertical direction, and this non-active face faces one second vertical direction contrary with this first vertical direction;
Positioning piece, it is as a configuration guiding element of this semiconductor element, and this keeper is near the peripheral edge of this semiconductor element, and in the peripheral edge of this semiconductor element of side surface direction lateral alignment perpendicular to this first vertical direction and this second vertical direction, and extend in this semi-conductive peripheral edge lateral;
One reinforced layer, it comprises a through hole, and this semiconductor element and this keeper extend into this through hole, wherein, this through hole has the shielding sidewall that side direction covers the peripheral edge of this semiconductor element;
One first increases layer circuit, and it covers this keeper, this semiconductor element and this reinforced layer in this first vertical direction, and this first increasing layer circuit is via the described contact pad electric connection of a plurality of the first conductive blind holes and this semiconductor element; And
One second increases layer circuit, it covers this keeper, this semiconductor element and this reinforced layer in this second vertical direction, and this second increasing layer circuit comprises the screening cover in alignment with this semiconductor element, wherein, this screening cover and this shielding sidewall via this first increase layer circuit and be electrically connected to described contact pad at least one for ground connection.
2. wiring board as claimed in claim 1, is characterized in that, this keeper comprises a continuous or discrete batten or protruded stigma array.
3. wiring board as claimed in claim 1, is characterized in that, this keeper is made by a metal or a sensing optical activity plastic material.
4. wiring board as claimed in claim 1, is characterized in that, the gap between this semiconductor element and this keeper is in 0.001 to 1mm scope.
5. wiring board as claimed in claim 1, is characterized in that, the height of this keeper is in the scope of 10 to 200 microns.
6. wiring board as claimed in claim 1, is characterized in that, this barrier lid is a continuous metal layer, and this screening cover is laterally to the peripheral edge that extends beyond this semiconductor element.
7. wiring board as claimed in claim 1, is characterized in that, this shielding sidewall is electrically connected to this first increasing layer circuit via a coating perforation, and this coating perforation extends through this reinforced layer.
8. wiring board as claimed in claim 1, is characterized in that, this shielding sidewall is electrically connected to this first increasing layer circuit via a first extra conductive blind hole of this first increasing layer circuit.
9. wiring board as claimed in claim 1, is characterized in that, this screening cover is electrically connected to this first increasing layer circuit via a coating perforation, and this coating perforation extends through this reinforced layer.
10. wiring board as claimed in claim 1, is characterized in that, this screening cover is electrically connected to this first increasing layer circuit via one second conductive blind hole of this reinforced layer and this second increasing layer circuit.
11. wiring boards as claimed in claim 1, is characterized in that, this screening cover increases a conduction ditch of layer circuit via this reinforced layer and this second and is electrically connected to this and first increases a layer circuit.
12. 1 kinds of wiring boards with embedded element, built-in keeper and electromagnetic shielding, comprising:
One screening cover;
Semiconductor element, it is arranged on this screening cover by an adhesive agent, and this semiconductor element comprises an active surface and contrary with this active surface one non-active, on this active surface, there are a plurality of contact pads, wherein, this active surface faces one first vertical direction this screening cover dorsad, and this non-active face faces one second vertical direction contrary with this first vertical direction and towards this screening cover;
Positioning piece, it is as a configuration guiding element of this semiconductor element, and this keeper extends towards this first vertical direction from this screening cover, this keeper is near the peripheral edge of this semiconductor element, and in the side surface direction lateral alignment vertical with this first vertical direction and this second vertical direction in the peripheral edge of this semiconductor element, and extend in the peripheral edge lateral of this semiconductor element;
One reinforced layer, it comprises a through hole, and this semiconductor element and this keeper extend into this through hole, wherein, this through hole has the shielding sidewall that side direction covers the peripheral edge of this semiconductor element; And
One first increases layer circuit, it is to cover this keeper, this semiconductor element and this reinforced layer in this first vertical direction, and this first increasing layer circuit is electrically connected the described contact pad of this semiconductor element via a plurality of the first conductive blind holes, wherein, this screening cover and this shielding sidewall via this first increase layer circuit and be electrically connected to described contact pad at least one for ground connection.
13. wiring boards as claimed in claim 12, characterized by further comprising:
One second increases layer circuit, and it is to cover this screening cover and this reinforced layer in this second vertical direction; And
One coating perforation, it extends through this reinforced layer so that this first electric connection increasing between layer circuit and this second increasing layer circuit to be provided.
CN201310468443.9A 2012-10-02 2013-10-08 Wiring board with embedded device, built-in stopper and electromagnetic shielding Pending CN103716992A (en)

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US201261708821P 2012-10-02 2012-10-02
US61/708,821 2012-10-02
US14/043,933 2013-10-02
US14/043,933 US20140061877A1 (en) 2012-08-14 2013-10-02 Wiring board with embedded device, built-in stopper and electromagnetic shielding

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Application publication date: 20140409