TWI517312B - Wiring board with shielding lid and shielding slots as electromagnetic shields for embedded device - Google Patents

Description

Circuit board with shielding cover and shielding slot as electromagnetic barrier for embedded components

The present invention relates to a circuit board having an embedded component and an electromagnetic barrier, and more particularly to a circuit board having a shield cover and a shield slot, wherein the shield cover and the shield slot can be used as horizontal and vertical barriers of the embedded component, respectively. .

Semiconductor components are susceptible to electromagnetic interference (EMI) or other internal components such as capacitance, induction, and conductive coupling during high frequency mode operation. When semiconductor wafers are closely arranged with each other for miniaturization, the severity of such adverse interference may increase significantly. In order to reduce electromagnetic interference, a barrier may be required on certain semiconductor components and modules.

U.S. Patent No. 8,102,032 to Bolognia et al., U.S. Patent No. 8,105,872 to Pagaila et al., U.S. Patent No. 8,093,691 to Fuentes et al., U.S. Patent No. 8,314,486 to Chi et al, and U.S. Patent No. 8,349,. These include metal cans, wire fences, or ball fences. All of the above methods are designed for assembly on substrates and shielding materials (eg metal cans, metals) The components on the film, the wire or the spheroidal mesh are all externally added, which requires extra space, thus increasing the size and extra cost of the semiconductor package.

US Patent No. 7,929,313, U.S. Patent No. 7,957,154, and U.S. Patent No. 8,168,893, the disclosure of each of the entire entire entire entire entire entire entire entire entire disclosure The concave part. This structure ensures excellent electrical shielding of the embedded components in a small space, but the depth of the conductive blind holes needs to be as thick as the thickness of the semiconductor components, so that the drilling and covering of the holes are limited by the high aspect ratio, and can only accommodate some super Thin components. In addition, since the recessed portion as the wafer placement region is formed after the metallization of the conductive via hole, the semiconductor device is misaligned due to poor alignment, and the yield of the method is extremely low in mass production.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a circuit board having an embedded component and an electromagnetic barrier, which can effectively shield the embedded component from electromagnetic interference. Accordingly, the present invention provides a circuit board including a semiconductor component, a core layer, a shield slot, a shield cover, a first build-up circuit, and optionally a second build-up circuit. In addition, the present invention also provides another circuit board comprising a semiconductor component, a core layer, a shielding slot, a first build-up circuit, and a second build-up circuit having a shield cover.

In a preferred embodiment, the shielding slot and the shielding cover are electrically connected to at least one ground contact pad of the semiconductor component, and can be used as a horizontal and vertical barrier of the semiconductor component, respectively. The core layer is perpendicular to the vertical The semiconductor element is laterally covered in a lateral direction, and the shielding cover covers the semiconductor element in a second vertical direction, and the first build-up circuit and the second build-up circuit cover the semiconductor element and the core layer from the first and second vertical directions, respectively.

The wiring board of the present invention may further include a positioning member which serves as a guide member for the semiconductor element, the positioning member being adjacent to and laterally aligned with the peripheral edge of the semiconductor element in the lateral direction. The positioning member may contact the shielding cover or the insulating layer of the second build-up circuit in a first vertical direction, and extend from the shielding cover or the insulating layer of the second build-up circuit in a first vertical direction, or from the first The insulating layer of the build-up circuit extends in a second vertical direction. For example, the positioning member may extend from the insulating layer or the shielding cover of the second build-up circuit in a first vertical direction and extend beyond the inactive surface of the semiconductor component; or the second vertical layer from the insulating layer of the first build-up circuit The direction extends or extends beyond the active face of the semiconductor component. Under any condition, the locating member is located outside the peripheral edge of the semiconductor component and adjacent to the peripheral edge of the semiconductor component.

The semiconductor device includes an active surface having a plurality of contact pads and an inactive surface opposite the active surface. The active surface of the semiconductor component faces the first vertical direction and faces away from the second build-up circuit or the shield cover, and the inactive surface of the semiconductor component faces the second vertical direction and faces the second build-up circuit or Shield cover. The semiconductor component can be attached to the first or second build-up circuit or to the shield cover with an adhesive.

The core layer can contact and surround the sidewall of the semiconductor component and the positioning member, and is covered in the same shape as the sidewall of the semiconductor component and the positioning component, and laterally extend from the semiconductor component and the positioning component to the peripheral edge of the circuit board . The core layer can be made of a prepreg material, such as an epoxy tree, BT, polyimine and its resin or resin/glass composite.

The shielding slot can extend from the first build-up circuit in a second vertical direction to the shield cover or the keeper. For example, the shielding slot may extend to the outside of the first build-up circuit or the inner conductive layer at a first end, and be electrically connected to the outside of the first build-up circuit or the inner conductive layer; and at a second end Extend to the shielding cover or the positioning member and electrically connect to the shielding cover or the positioning member. In another aspect, the shielding slot can extend from the second build-up circuit in a first vertical direction to the keeper. For example, the shielding slot at the first end may extend to the positioning member and be electrically connected to the positioning member; and may extend to the shielding cover of the second build-up circuit at the second end, or be electrically connected to the second increase Shielding cover for layer circuits. The shielding slot spaced apart from the first build-up circuit can be electrically connected to the first build-up circuit through the conductive blind hole or the one or more covered through holes, and the conductive blind holes are electrically contacted with the positioning member, and the covered through-holes are Electrically contacting the shield cover and the first build-up circuit. In any condition, the shielding slot extends through the core layer and laterally covers the semiconductor component and is electrically coupled to the at least one ground contact pad of the semiconductor component through the first build-up circuitry. The shield slots can be formed by forming a slot extending through the core layer and then plating the inner sidewalls of the slots. The shielding slots can each be a continuous metallized slot and can have an open end facing the first or second vertical direction. In order to provide an effective lateral EMI barrier, each of the shielding slots preferably extends laterally along each side edge of the semiconductor component, and the two ends of the shielding slot preferably extend outwardly beyond the periphery of the semiconductor component. The edges extend even laterally to the peripheral edge of the board. For example, the wiring board can be designed to have four shielding slots, each extending continuously beyond the semiconductor component along the four sides of the semiconductor component in the lateral direction. The outer edge. Accordingly, the shield slot can completely cover the sides of the semiconductor component to reduce side electromagnetic interference. Alternatively, where the shielding slot extends to the keeper, the sides of the semiconductor component may be completely covered by a combination of the locating member and the shielding slot.

The shielding cover is aligned with the semiconductor component from the second vertical direction and covers the semiconductor component, and is electrically connected to the at least one ground contact pad of the semiconductor component through the first build-up circuit. The shield cover can be a continuous metal layer and, in order to provide an effective vertical EMI barrier, preferably extends at least laterally to coincide with the peripheral edge of the semiconductor component. For example, the shield cover may extend laterally in the lateral direction to be coplanar with the peripheral edge of the semiconductor component, or outwardly beyond the peripheral edge of the semiconductor component, and even laterally to the peripheral edge of the board. Accordingly, the shield cover can completely cover the semiconductor component from the second vertical direction to reduce vertical electromagnetic interference. The shielding cover spaced from the first build-up circuit is electrically connected to the first build-up circuit through the shield slot, and the shield slot is electrically connected to the first build-up circuit. For example, in one aspect of the invention, the circuit board having the shield slot extends to the shield cover at the second end, the shield slot contacts the shield cover and provides an electrical connection between the shield cover and the first build-up circuit. Moreover, according to another aspect, when the positioning member extends from the shielding cover toward the first vertical direction, and the shielding slot extends to the positioning member at the second end, the shielding cover can be electrically connected through the positioning member and the shielding slot. To the first build-up circuit. In another embodiment, the circuit board having the shielding slot extends to the positioning member at the second end, wherein the positioning member is spaced apart from the shielding cover by the insulating layer of the second build-up circuit, the shielding cover Electrically connected to the positioning member through the conductive blind hole or the conductive groove of the second build-up circuit, Thus, the combination of the shielding slot, the positioning member and the conductive blind hole or the conductive groove can provide an electrical connection between the shielding cover and the first build-up circuit. Alternatively, the shield cover can be electrically connected to the first build-up circuit through more than one of the coated vias extending through the core layer. For example, the coated via at the first end may extend to the first build-up circuit and be electrically connected to the first build-up circuit; and may extend to the shield cover at the second end and be electrically connected to the shield cover. Thus, the covered perforations provide an electrical connection between the shield cover and the first build-up circuitry.

The first build-up circuit covers the semiconductor component and the core layer from a first vertical direction, and may include a first insulating layer and one or more first wires. For example, the first insulating layer covers the semiconductor element and the core layer in a first vertical direction and may extend to a peripheral edge of the wiring board, and the first conductive line extends from the first insulating layer toward the first vertical direction. The first insulating layer may include a plurality of first blind vias disposed adjacent to the contact pads of the semiconductor component. One or more first wires extending from the first insulating layer in a first vertical direction and extending laterally on the first insulating layer and extending into the first blind via in a second vertical direction to form a first conductive blind via, thereby providing Signal routing of the signal contact pads of the semiconductor component, and grounding of the ground contact pads of the semiconductor component. In addition, in an embodiment of the circuit board, the positioning member extends from the first insulating layer in a first vertical direction, and the first insulating layer may further include one or more additional first blind holes, which are disposed adjacent to the positioning. Selected parts of the piece. The first wire may extend further into the additional first blind via in the second vertical direction to form one or more additional first conductive vias that are in electrical contact with the positioning member, thereby providing a ground contact pad for the semiconductor component Grounding with the positioning member. Therefore, the shielding slot electrically connected to the positioning member can be electrically transmitted through the positioning member and the first conductive blind hole. Connected to the ground contact pad of the semiconductor component. In short, the first build-up circuit is electrically connected to the contact pads of the semiconductor component through the first conductive via hole to provide signal routing and grounding of the semiconductor component, and can be electrically transmitted through the additional first conductive via hole. The connection is connected to the positioning member to provide grounding of the positioning member. When the first wire can directly contact the contact pad of the semiconductor component and the positioning component, the electrical connection between the semiconductor component and the first build-up circuit component and between the positioning component and the first build-up circuit can be free of solder.

A second build-up circuit is selectively provided that covers the shield cover and the core layer from a second vertical direction in accordance with a pattern of the circuit board having the semiconductor component disposed on the shield cover. In this aspect, the second build-up circuit can include a second insulating layer and more than one second wire. For example, the second insulating layer covers the shielding cover and the core layer from the second vertical direction, and may extend to the peripheral edge of the circuit board, and the second wire extends from the second insulating layer in the second vertical direction and is disposed on the second insulating layer. The upper side extends. The second insulating layer can include more than one second blind via that is disposed adjacent to a selected portion of the shield cover. The second wire may extend into the second blind hole in the first vertical direction to form more than one second conductive blind hole, thereby providing an electrical connection of the shielding cover. In another circuit board state, the shielding cover is built in the second build-up circuit, the second build-up circuit covers the semiconductor component and the core layer from the second vertical direction, and may include the second insulation layer, the shielding cover and the selectivity Contains the second wire. For example, the second insulating layer covers the semiconductor element and the core layer from the second vertical direction and may extend to the peripheral edge of the circuit board, and the shielding cover and the second wire extend from the second insulating layer toward the second vertical direction, and The two insulating layers extend laterally. In one embodiment of the circuit board, the positioning member is from the second insulating layer toward the first vertical side Extending, the second insulating layer can include more than one second blind or trench hole disposed adjacent to a selected portion of the keeper and can be metallized to form more than one second wire or conductive trench. Accordingly, the shielding cover can be electrically connected to the first build-up circuit through the shielding slot, the positioning member, and the second conductive blind hole or the conductive groove under the condition that the shielding slot of the second end extends to the positioning component. Ground. In another aspect of the circuit board, the shielding slot extends from the first build-up circuit to the shield cover of the second build-up circuit, and the shield cover is electrically connected to the first build-up circuit through the shield slot.

If additional signal routing is required, the first and second build-up circuits may include additional dielectric layers, additional blind via layers, and additional trace layers. For example, the first build-up circuit may further include a third insulating layer and a third wire. The third insulating layer extends from the first insulating layer and the first wire in a first vertical direction and may extend to a peripheral edge of the circuit board, and the third wire extends from the third insulating layer toward the first vertical direction. Where the shield slot extends from the first end to the first wire and has an open end facing the first vertical direction, the third insulating layer may extend further into the shield slot at the open end of the shield slot. The outermost leads of the first and second build-up circuits may each include more than one first and second inner connection pads to provide electrical contacts for electronic components such as semiconductor wafers, plastic packages or another semiconductor package. The first inner connection pad can include an exposed contact surface facing the first vertical direction, while the second inner connection pad can include an exposed contact surface facing the second vertical direction. Therefore, the circuit board can include electrical contacts (eg, first and second inner connection pads) that are electrically connected to each other and to opposite surfaces facing in opposite vertical directions, so that the circuit boards can be stacked and the electronic components can utilize various The connection medium is electrically connected to the circuit board, and the connection medium includes a wire or Solder bumps serve as electrical contacts.

The circuit board of the present invention may further comprise more than one coated perforation extending through the core layer, and the covered perforation may provide an electrical connection between the first build-up circuit and the second build-up circuit. For example, the coated via at the first end may extend outside the first build-up circuit or the inner conductive layer, and be electrically connected to the outside of the first build-up circuit or the inner conductive layer; and extend to the second end The second or additional conductive layer or shield cover is electrically connected to the outside of the second build-up circuit or to the inner conductive layer or the shield cover. Therefore, the covered perforations can provide electrical connection or grounding for vertical signal routing.

The positioning member may be prepared from a metal, a photosensitive plastic material, or a non-photosensitive material. For example, the positioning member may be substantially composed of copper, aluminum, nickel, iron, tin, an alloy thereof, and the positioning member may also be made of epoxy resin, or Made up of polyimine. Further, the positioning member may have a pattern to prevent unnecessary displacement of the semiconductor element. For example, the positioning member can comprise a continuous or discontinuous strip or array of studs. Specifically, the positioning member can laterally align the four side surfaces of the semiconductor element to prevent lateral displacement of the semiconductor element. For example, the positioning member may be aligned along four sides, two diagonals, or four corners of the semiconductor element, and the gap between the semiconductor element and the positioning member is preferably in the range of about 0.001 to 1 mm. within. Therefore, the positioning member that is not shielded from the slot and the semiconductor component can prevent the positional error of the semiconductor component from exceeding the maximum acceptable error limit. Furthermore, the positioning member can also be part of the horizontal barrier of the semiconductor component in the case where the shielding slot extends to the positioning member. Further, the positioning member preferably has a thickness of 10 to 200 μm.

The invention further provides a three-dimensional stacked group, which is composed of plural A circuit board each having an embedded component and an electromagnetic barrier is stacked, and a plurality of circuit boards are respectively used in an inner dielectric layer between two adjacent circuit boards to back-to-back or face back The (face-to-back) manner is stacked and electrically connected to each other through one or more covered perforations.

The present invention has a number of advantages in that the shield slot and the shield cover can be used as horizontal and vertical EMI barriers for the semiconductor component, respectively, to reduce electromagnetic interference. An electrical connection between the ground contact pads of the semiconductor component and the shield side slots/shield covers can be provided via the build-up circuit to provide an effective electromagnetic barrier embedded in the semiconductor component in the circuit board effect. Due to the high routing capability of the layering circuit, the layering circuit provides signal routing and facilitates high I/O values and high performance. In addition, the positioning member can be selectively provided due to actual needs. For example, in the case where a wafer having a fine pitch is embedded in a wiring board, the positioning member can accurately limit the placement position of the wafer to avoid an electrical connection error between the wafer and the build-up circuit due to lateral displacement of the wafer. , and thus greatly improved the product yield. The circuit board and the stacked assembly using the same have high reliability, low cost, and are very suitable for mass production and production.

The above and other features and advantages of the present invention will be further described hereinafter by way of various preferred embodiments.

100,200,300,400,500,600,700,800‧‧‧PCB

101,102‧‧‧Stacked group

11,21,22‧‧‧metal layer

110, 120, 130, 140‧‧‧ boards

111‧‧‧ openings

121‧‧‧ recesses

123‧‧‧ Positioning parts

13‧‧‧Dielectric layer

15‧‧‧Support board

16‧‧‧Adhesive

201,202,203‧‧‧Additional circuit

21’‧‧‧First coating

211‧‧‧First insulation

213‧‧‧ first blind hole

215‧‧‧First wire

217‧‧‧First conductive blind hole

22'‧‧‧Second coating

221‧‧‧Second insulation

222‧‧‧ terminals

223‧‧‧ second blind hole

224‧‧‧Shield cover

225‧‧‧second wire

226‧‧‧Ditch hole

227‧‧‧Second conductive blind hole

228‧‧‧ Conductive ditch

231‧‧‧ Third insulation layer

233‧‧‧ third blind hole

235‧‧‧ Third wire

237‧‧‧3rd conductive blind hole

245‧‧‧fourth wire

261‧‧‧Internal dielectric layer

31‧‧‧Semiconductor components

311‧‧‧ active face

312‧‧‧Contact pads

313‧‧‧Inactive surface

41‧‧‧ core layer

411‧‧‧Slit hole

414‧‧‧Shield slot

511‧‧‧Perforation

515‧‧‧ Covered perforation

The invention will be more apparent from the following detailed description of the preferred embodiments.

1 to 5 are cross-sectional views showing a method of manufacturing a circuit board including a positioning member, a semiconductor component, a core layer, and a preferred embodiment of the present invention. Shielding cover, shielding slot, terminal, build-up circuit and covered perforation; wherein FIGS. 1A, 2A and 4A are top views of FIG. 1, FIG. 2 and FIG. 4, respectively, and FIGS. 1B to 1G are other reference patterns of the positioning member; Top view.

6 to FIG. 15 are cross-sectional views showing a method of manufacturing another circuit board including a positioning member, a semiconductor component, a core layer, a shield cover, a shield slot, a double build-up circuit, and a cover according to another preferred embodiment of the present invention. perforation.

16 to 21 are cross-sectional views showing a method of manufacturing a further circuit board according to still another preferred embodiment of the present invention, the circuit board including a shielding slot in electrical contact with the positioning member.

22 to 27 are cross-sectional views showing another manufacturing method of a circuit board according to a preferred embodiment of the present invention, the circuit board including a positioning member, a semiconductor element, a core layer, a shielding slot, and a double-growth circuit; wherein FIG. 22' Figure 23' is a cross-sectional view of another embodiment of Figures 22-23.

26' to 27' are cross-sectional views of another embodiment of Figs. 26 to 27.

28 to 30 are cross-sectional views showing a method of manufacturing another circuit board according to another preferred embodiment of the present invention, the circuit board including a shielding slot electrically connected to the positioning member and the shielding cover.

31 to 33 are cross-sectional views showing a method of manufacturing a further circuit board according to still another preferred embodiment of the present invention, wherein the shield cover is electrically connected to the first build-up circuit through a conductive groove in contact with the positioning member; wherein FIG. 32A is Figure 32 is a bottom view.

Figure 33' is a cross-sectional view showing another embodiment of Figure 33.

34 to 36 are still another circuit board of another preferred embodiment of the present invention. A cross-sectional view of a manufacturing method in which a shield cover is electrically connected to a first build-up circuit through a covered via.

37 to 39 are cross-sectional views showing a method of manufacturing a three-dimensional stacked assembly according to a preferred embodiment of the present invention, the three-dimensional stacked assembly comprising a plurality of wiring boards stacked in a face-to-face manner.

40 to FIG. 42 are cross-sectional views showing a method of fabricating another three-dimensional stacked assembly according to another preferred embodiment of the present invention, the three-dimensional stacked assembly including a plurality of wiring boards stacked in a back-to-back manner.

In the following, examples will be provided to explain in detail embodiments of the invention. Other advantages and utilities of the present invention will be more apparent from the teachings of the present invention. It should be noted that the drawings are simplified in the drawings, and the number, shape, and size of components shown in the drawings may be modified according to actual conditions, and the configuration of components may be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[Example 1]

1 to 5 are cross-sectional views showing a method of fabricating a circuit board including a positioning member, a semiconductor component, a core layer, a shield cover, a shield slot, a terminal, a build-up circuit, and a covered via 515, in accordance with a preferred embodiment of the present invention. .

As shown in FIG. 5, the circuit board 100 includes a positioning member 123, a semiconductor element 31, a core layer 41, a shield cover 224, a shield slot 414, a terminal 222, a build-up circuit 201, and a covered via 515. Semiconductor component 31 includes The active surface 311, the inactive surface 313 opposite to the active surface 311, and the contact pad 312 on the active surface 311. The positioning member 123 is disposed outside the peripheral edge of the semiconductor element 31 and adjacent to the peripheral edge of the semiconductor element 31. The core layer 41 laterally covers the positioning member 123 and the semiconductor element 31 and extends laterally to the peripheral edge of the wiring board 100. The build-up circuit 201 includes a first insulating layer 211 and a first conductive line 215 , and is electrically connected to the semiconductor element 31 through the first conductive line 215 . The shield slot 414 extends from the first wire 215 in a downward direction to the shield cover 224 and laterally covers the semiconductor component 31. The shielding cover 224 covers the semiconductor element 31 in a downward direction. The terminal 222 extends from the core layer 41 in a downward direction and is spaced apart from the shielding cover 224. The covered through hole 515 extends through the build-up circuit 201 and the core layer 41, and provides an increase. The layer circuit 201 and the terminal 222 are electrically connected.

1 and 1A are respectively a cross-sectional view and a plan view of a positioning member 123 formed on a metal layer 11. The metal layer 11 is generally made of copper, but a copper alloy or other material may be used, and the metal layer 11 has a thickness ranging from 5 to 200 μm. In this embodiment, the metal layer 11 is shown as a copper plate having a thickness of 50 micrometers, and the positioning member 123 can be deposited on the metal layer 11 by various techniques such as electroplating, electroless plating, evaporation, sputtering, and combinations thereof in combination with lithography. And being patterned. The positioning member 123 is generally made of copper, but other metal materials may be used. Further, the positioning member 123 preferably has a thickness in the range of 10 to 200 μm. In this figure, the positioning member 123 is composed of a continuous copper strip having a thickness of 35 μm and conforms to the four sides of the semiconductor element which is subsequently disposed on the metal layer 11. However, the form of the positioning member is not limited thereto, and may be any pattern that prevents unnecessary displacement of the subsequently disposed semiconductor element.

1B to 1G are various reference forms of the positioning member. For example, the positioning member 123 may be composed of a discontinuous strip (as shown in FIGS. 1B, 1D and 1F), or a plurality of metal studs of the rectangular array (as shown in FIGS. 1C, 1E and 1G), and It conforms to the four sides of the subsequently disposed semiconductor component (as shown in FIGS. 1B and 1C), two diagonals (as shown in FIGS. 1D and 1E), or four corners (FIGS. 1F and 1G).

2 and 2A are respectively a cross-sectional view and a plan view showing a structure in which the semiconductor element 31 is disposed on the metal layer 11 using the adhesive 16, wherein the adhesive 16 is located between the metal layer 11 and the semiconductor element 31, and the adhesive 16 contacts the metal layer 11 And a semiconductor element 31. The semiconductor element 31 includes an active surface 311, an inactive surface 313 opposite to the active surface 311, and a plurality of contact pads 312 on the active surface 311. The positioning member 123 can serve as a guide for the semiconductor element 31, so that the semiconductor element 31 is accurately placed at a predetermined position with its inactive surface 313 facing the metal layer 11. The positioning member 123 extends from the metal layer 11 in the upward direction beyond the inactive surface 313 of the semiconductor element 31 and is aligned with the four sides of the semiconductor element 31. When the positioning member 123 is adjacent to the four side surfaces of the semiconductor element 31 in the side direction and conforms to the four side surfaces of the semiconductor element 31, and the adhesive 16 under the semiconductor element 31 is lower than the positioning member 123, the curing by the adhesive can be prevented. This results in any unnecessary displacement of the semiconductor component 31. The gap between the semiconductor element 31 and the positioning member 123 is preferably in the range of 0.001 to 1 mm. However, for a semiconductor element having a coarse pitch, component misalignment caused by adhesion of the adhesive generally does not cause a microvia connection error, so the positioning member 123 may be omitted, and the semiconductor component 31 may use any known alignment. The technique is attached to the metal layer 11.

3 is a cross-sectional view showing the structure in which the core layer 41, the first insulating layer 211, and the metal layer 21 are laminated. The core layer 41 is pressed and then cured with the semiconductor element 31, the positioning member 123, and the metal layer 11 under application of pressure and high temperature. Therefore, the core layer 41 contacts the positioning member 123 and the metal layer 11 in the upward direction, and extends in the upward direction from the positioning member 123 and the metal layer 11, and laterally covers, surrounds the semiconductor element 31 and the positioning member 123, and the semiconductor element 31. The positioning member 123 is coated in the same shape and extends laterally from the semiconductor element 31 and the positioning member 123 to the peripheral edge of the structure. The first insulating layer 211 contacts the metal layer 21 and the semiconductor element 31 and is located between the metal layer 21 and the semiconductor element 31 and between the metal layer 21 and the core layer 41. The first insulating layer 211 generally has a thickness of 50 micrometers, and the metal layer 21 is illustrated as a copper layer having a thickness of 17 micrometers. Under pressure and high temperature, the pressure is applied downward to the metal layer 21 or/and the metal layer 11 is applied. The upward pressure, the first insulating layer 211 is melted and compressed, whereby the curing of the first insulating layer 211 provides a secure connection between the metal layer 21 and the semiconductor element 31, and between the metal layer 21 and the core layer 41. Mechanical connection. The core layer 41 and the first insulating layer 211 may be epoxy resin, glass epoxy resin, polyimine, and the like.

4 and 4A are a cross-sectional view and a plan view, respectively, having a first blind hole 213, a slit 411, and a through hole 511. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 and is aligned with the contact pads 312 of the semiconductor component 31. The first blind via 213 can be formed by a variety of techniques including laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns. Pulsed lasers can be used to improve laser drilling performance, or metal reticle and scanning laser beams can be used. For example, the copper plate can be etched first to make After a metal window, the laser is irradiated. The slit 411 extends through the metal layer 21, the first insulating layer 211, and the core layer 41 to expose selected portions of the metal layer 11. As shown in FIG. 4A, the slits 411 are formed by mechanical cutting along the dicing lines of the four sides of the four aligned semiconductor elements 31 through the metal layer 21, the first insulating layer 211, and the core layer 41. The through hole 511 extends through the metal layer 21, the first insulating layer 211, the core layer 41, and the metal layer 11 in the vertical direction. The perforations 511 can be formed by mechanical drilling, or by other techniques such as laser drilling and wet or non-wet plasma etching.

Referring to FIG. 5, the first insulating layer 211 is deposited on the metal layer 21 by depositing a first cladding layer 21' and depositing the first cladding layer 213, then patterning the metal layer 21 and the first cladding layer 21' thereon. A first wire 215 is formed thereon. Alternatively, when the metal layer 21 is not laminated on the first insulating layer 211 in the previous step, the first insulating layer 211 may be directly metallized to form the first conductive line 215. The first conductive line 215 extends from the first insulating layer 211 in the upward direction, extends laterally on the first insulating layer 211, and extends into the first blind via 213 in a downward direction to form a first conductive via 217. The first conductive The blind via 217 is in direct contact with the contact pad 312. Therefore, the first wire 215 can provide signal routing and grounding of the semiconductor component 31.

As also shown in Fig. 5, the first covering layer 21' deposited in the slit 411 and the through hole 511 provides the shielding slit 414 and the covered perforation 515, and the first covering layer 21' is deposited on the metal layer 11. The terminal 222 and the shield cover 224 are defined by the patterned metal layer 11 and the first cladding layer 21' on the bottom surface of the structure. The shielding slot 414 extends from the first wire 215 in the upward direction to the shielding cover 224 and laterally covers the semiconductor component 31 and as a semiconductor element The horizontal EMI barrier of the piece. The shield cover 224 covers the semiconductor element 31, the positioning member 123, and the shield slot 414 in a downward direction, and serves as a vertical EMI barrier of the semiconductor element 31. The terminal 222 is spaced apart from the shield cover 224 and electrically connected to the first lead 215 via the covered via 515.

The first cladding layer 21' can be deposited by various techniques to form a single layer or multilayer structure including electroplating, electroless plating, evaporation, sputtering, and combinations thereof. For example, the structure is firstly immersed in the activator solution to cause the insulating layer to react with the electroless copper plating catalyst, and then a thin copper layer is coated as a seed layer by electroless plating, and then electroplated. A second copper layer of a desired thickness is formed on the seed layer. Alternatively, the seed layer may be formed by a sputtering method such as a titanium/copper seed layer film before the electroplated copper layer is deposited on the seed layer. Once the desired thickness is achieved, the coating can be patterned using various techniques to form first lead 215, terminal 222, and shield cover 224, including wet etching, electrochemical etching, laser assisted etching, and etching reticle ( A combination of the figures is shown to define a first wire 215, a terminal 222, and a shield cover 224.

For convenience of explanation, the metal layers 11, 21 and the first covering layer 21' are represented by a single layer. Since the copper is a homogeneous coating, the boundary between the metal layers (both shown by dashed lines) may be difficult to detect or even detect, but the first coating The boundary between the layer 21' and the first insulating layer 211 and between the first covering layer 21' and the core layer 41 is clearly visible.

Accordingly, as shown in FIG. 5, the completed circuit board 100 includes a positioning member 123, a semiconductor element 31, a core layer 41, a shield cover 224, a shield slot 414, a build-up circuit 201, a terminal 222, and a covered via 515. In this In the embodiment, the build-up circuit 201 includes a first insulating layer 211 and a first conductive line 215, and the covered via 515 is substantially shared by the core layer 41, the build-up circuit 201, and the terminal 222. The semiconductor element 31 is disposed at a predetermined position on the shield cover 224 by using the positioning member 123 as a configuration guide, and the semiconductor element 31 is laterally surrounded by the shield slot 414; wherein the shield slot 414 extends downward from the first wire 215 to the shield The cover 224 extends outward beyond the peripheral edge of the semiconductor component 31. The shielding slot 414 has an open end facing in the upward direction and is electrically connected to the ground contact pad of the semiconductor component 31 through the first wire 215 and serves as a horizontal barrier of the semiconductor component 31. The shielding cover 224 is electrically connected to the ground contact pad of the semiconductor component 31 through the shielding slot 414. The shielding slot 414 is in electrical contact with the shielding cover 224 and the first wire 215 and can serve as a vertical barrier of the semiconductor component 31. The covered via 515 provides an electrical connection between the build-up circuit 201 and the terminal 222, wherein the terminal 222 extends from the core layer 41 in a downward direction.

[Embodiment 2]

6 to FIG. 15 are cross-sectional views showing a method of manufacturing another circuit board including a positioning member, a semiconductor component, a core layer, a shield cover, a shield slot, a double build-up circuit, and a cover according to another preferred embodiment of the present invention. perforation.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

6 is a cross-sectional view of a laminate substrate including a metal layer 11, a dielectric layer 13, and a support plate 15. The dielectric layer 13 is typically made of epoxy, glass epoxy, polyimine, and the like, and has a thickness of 50 microns. The thickness. In this embodiment, the dielectric layer 13 is interposed between the metal layer 11 and the support plate 15. However, the support plate 15 may be omitted in some aspects. The support plate 15 is usually made of copper, but a copper alloy or other materials can be used. The thickness of the support plate 15 can be in the range of 25 to 1000 micrometers, and is preferably 35 to the process and cost. Within the range of 100 microns. In this embodiment, the support plate 15 is a copper plate having a thickness of 35 μm.

FIG. 7 is a cross-sectional view showing the structure of the positioning member 123 formed on the metal layer 11. The locating member 123 can be deposited on the metal layer 11 and patterned by various techniques such as electroplating, electroless plating, evaporation, sputtering, and combinations thereof in combination with lithography.

FIG. 8 is a cross-sectional view showing the structure of the shield cover 224 defined on the dielectric layer 13. The shield cover 224 can be formed by removing a selected portion of the metal layer 11 by lithography and wet etching. The shield cover 224 corresponds to a predetermined position for placing the semiconductor element and can serve as a vertical EMI barrier.

9 is a cross-sectional view showing the structure in which the semiconductor element 31 is placed on the shield cover 224 by the adhesive 16, wherein the adhesive 16 is placed between the shield cover 224 and the semiconductor element 31, and contacts the shield cover 224 and the semiconductor element 31. The semiconductor element 31 is attached to the shield cover 224 with its inactive surface 313 facing the shield cover 224. The positioning member 123 extends from the shield cover 224 in the upward direction and extends beyond the inactive surface 313 of the semiconductor component 31, and the positioning member 123 The peripheral edge of the semiconductor element 31 is reported as a configuration guide of the semiconductor element 31.

FIG. 10 is a cross-sectional view showing the structure in which the core layer 41, the first insulating layer 211, and the metal layer 21 are laminated. The core layer 41 contacts the semiconductor element 31, The positioning member 123, the shielding cover 224 and the dielectric layer 13 are pressed together with the semiconductor element 31, the positioning member 123, the shielding cover 224 and the dielectric layer 13. The first insulating layer 211 contacts the metal layer 21, the semiconductor element 31, and the core layer 41, and provides a stable mechanical connection between the metal layer 21 and the semiconductor element 31, and between the metal layer 21 and the core layer 41. The first insulating layer 211 preferably has the same material as the dielectric layer 13, wherein the dielectric layer 13 serves as the second insulating layer 221.

Figure 11 is a cross-sectional view showing the structure of the first blind hole 213. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 to expose the contact pads 312 of the semiconductor component 31.

Referring to FIG. 12, the first insulating layer 211 is deposited on the metal layer 21 and deposited into the first blind via 213, and then the metal layer 21 and the first cladding layer 21' thereon are patterned to the first insulating layer 211. A first wire 215 is formed thereon. The first wire 215 extends from the first insulating layer 211 in the upward direction, extends laterally on the first insulating layer 211, and extends into the first blind hole 213 in a downward direction to form a first conductive blind hole 217. Pad 312 is in direct contact.

FIG. 13 is a cross-sectional view showing the structure in which the third insulating layer 231 is laminated. The third insulating layer 231 contacts the first insulating layer 211 and the first conductive line 215 and covers the first insulating layer 211 and the first conductive line 215 in an upward direction.

14 is a cross-sectional view showing the structure of the second blind hole 223, the third blind hole 233, the slit 411, and the through hole 511. The second blind hole 223 extends through the support plate 15 and the second insulating layer 221 to expose selected portions of the shield cover 224. The third blind via 233 extends through the third insulating layer 231 to expose selected portions of the first conductive trace 215. The slit 411 extends through the third insulating layer 231, the first insulation Layer 211 and core layer 41 are used to expose selected portions of shield cover 224. The through hole 511 extends through the third insulating layer 231, the first insulating layer 211, the core layer 41, the second insulating layer 221, and the support plate 15 in the vertical direction.

Referring to FIG. 15, the second conductive line 225 and the third conductive line 235 are respectively formed on the second and third insulating layers 221, 231 by depositing a second covering layer 22' on the supporting plate 15 and the third insulating layer 231. And depositing into the second and third blind holes 223, 233, and then patterning the second covering layer 22' and the support plate 15 are formed. The second wire 225 extends from the second insulating layer 221 in a downward direction, extends laterally on the second insulating layer 221, and extends into the second blind hole 223 in an upward direction to form a second conductive blind hole 227. Contact the shield cover 224. The third wire 235 extends from the third insulating layer 231 in the upward direction, extends laterally on the third insulating layer 231, and extends into the third blind hole 233 in a downward direction to form a third conductive blind hole 237. The first wire 215 is contacted. Moreover, the second covering layer 22' is further deposited in the slit 411 and the through hole 511 to provide the shielding slot 414 and the covering hole 515.

Accordingly, as shown in FIG. 15, the completed circuit board 200 includes the positioning member 123, the semiconductor element 31, the core layer 41, the shield cover 224, the shield slot 414, the double build-up circuits 202, 203, and the covered via 515. The first build-up circuit 202 covers the semiconductor element 31 and the core layer 41 in an upward direction, and includes a first insulating layer 211, a first conductive line 215, a third insulating layer 231, and a third conductive line 235. The second build-up circuit 203 covers the shield cover 224 and the core layer 41 in a downward direction, and includes a second insulating layer 221 and a second conductive line 225. The shielding slot 414 contacts the third wire 235 and extends from the third wire 235 in a downward direction to the shielding cover 224, and is electrically connected through the first and third wires 215, 235. To the ground contact pad of the semiconductor component 31. The shielding cover 224 covers the semiconductor element 31 in a downward direction and is electrically connected to the ground contact pad of the semiconductor element 31 through the shielding slot 414, the first and third wires 215, 235. The covered via 515 is substantially shared by the core layer 41, the first build-up circuit 202, and the second build-up circuit 203, and provides an electrical connection between the second conductor 225 and the third conductor 235.

[Example 3]

16 to 21 are cross-sectional views showing a method of manufacturing a further circuit board according to still another preferred embodiment of the present invention, the circuit board including a shielding slot in electrical contact with the positioning member.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

Figure 16 is a cross-sectional view showing the structure produced by the same steps shown in Figures 1 to 3.

17 is a cross-sectional view showing the structure of the first blind hole 213 and the slit 411. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 to expose the contact pads 312 of the semiconductor component 31. The slit 411 extends through the metal layer 21, the first insulating layer 211, and the core layer 41 to expose selected portions of the positioning member 123.

Referring to FIG. 18, a first cladding layer 21' is deposited on the metal layer 21 and deposited into the first blind via 213, and then the metal layer 21 and the first cladding layer 21' thereon are patterned to be in the first insulation. A first wire 215 is formed on the layer 211. The first cladding layer 21' is also deposited into the slot 411 to provide a shielding slot 414. The first wire 215 provides the semiconductor component through the first wire 215 The signal routing of 31, and the grounding contact pad of the semiconductor component 31 and the shielding slot 414 are grounded. Also, the opening 111 is formed through a predetermined position of the metal layer 11 for subsequent formation of the covered perforations. In this embodiment, the metal layer 11 acts as a shield cover 224 to provide a vertical EMI barrier effect of the semiconductor component 31.

19 is a cross-sectional view showing the structure of the second insulating layer 221 and the third insulating layer 231. The second insulating layer 221 covers the shield cover 224 in a downward direction and fills the opening 111. The third insulating layer 231 covers the first insulating layer 211 and the first conductive line 215 in an upward direction, and extends from the open end of the narrow hole 414 into the slit 414.

20 is a cross-sectional view showing the structure of the second blind hole 223, the third blind hole 233, and the through hole 511. The second blind via 223 extends through the second insulating layer 221 and is aligned with selected portions of the shield cover 224. The third blind via 233 extends through the third insulating layer 231 and is aligned with a selected portion of the first conductive line 215. The through hole 511 corresponds to the opening 111, is axially aligned with the opening 111, and is located at the center of the opening 111, and extends through the third insulating layer 231, the first insulating layer 211, the core layer 41, and the second insulating layer 221 in the vertical direction.

Referring to FIG. 21, the second wire 225 and the third wire 235 are respectively formed on the second and third insulating layers 221, 231 by metal deposition and patterning. The second wire 225 extends from the second insulating layer 221 in a downward direction, extends laterally on the second insulating layer 221, and extends into the second blind hole 223 in an upward direction to form a second conductive blind hole 227. Contact the shield cover 224. The third wire 235 extends from the third insulating layer 231 in the upward direction, extends laterally on the third insulating layer 231, and extends in the downward direction into the third direction. The blind via 233 forms a third conductive via 237 that electrically contacts the first lead 215. Also, the covered perforations 515 are formed by depositing metal in the perforations 511.

Accordingly, as shown in FIG. 21, in the completed wiring board 300, the combination of the positioning member 123 and the shield slot 414 can serve as a horizontal barrier of the semiconductor component 31, and the shield cover 224 can serve as a vertical barrier of the semiconductor component 31. The shielding slot 414 contacts the first wire 215 and extends from the first wire 215 downwardly to the positioning member 123 and is electrically connected to the ground contact pad of the semiconductor component 31 through the first wire 215. The shielding cover 224 covers the semiconductor element 31 in a downward direction and is electrically connected to the ground contact pad of the semiconductor element 31 through the positioning member 123, the shielding slot 414 and the first wire 215. The covered via 515 is substantially shared by the core layer 41, the first build-up circuit 202, and the second build-up circuit 203, and provides electrical connection between the second conductor 225 and the third conductor 235.

[Example 4]

22 to 27 are cross-sectional views showing another manufacturing method of a circuit board according to a preferred embodiment of the present invention, the circuit board including a positioning member, a semiconductor element, a core layer, a shield slot, and a double build-up circuit.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

22 and 23 are cross-sectional views showing a process of forming a positioning member on a dielectric layer.

22 is a cross-sectional view of a laminate substrate including a metal layer 12, a dielectric layer 13, and a support plate 15. In this embodiment, the dielectric layer 13 Located between the metal layer 12 and the support plate 15. However, the support plate 15 may be omitted in some aspects. The metal layer 12 is illustrated as a 35 micron copper layer, but other materials may be used without limitation to the copper layer. In addition, the metal layer 12 can be deposited on the dielectric layer 13 by various techniques to form a single layer or a multilayer structure including electroplating, electroless plating, evaporation, sputtering, and combinations thereof, and preferably between 10 and 200 microns. thickness.

FIG. 23 is a cross-sectional view showing a structure in which a positioning member 123 is formed on the dielectric layer 13. The locating member 123 can be formed by removing a selected portion of the metal layer 12 by photolithography and wet etching.

22' to 23' are cross-sectional views showing another embodiment of the positioning member formed on the dielectric layer.

Figure 22' is a cross-sectional view of a laminate substrate having a plurality of pockets 121. As described above, the laminate substrate includes the metal layer 12, the dielectric layer 13, and the support plate 15, and the recess 121 is formed by removing selected portions of the metal layer 12.

23' is a cross-sectional view showing a structure in which a positioning member 123 is formed on the dielectric layer 13. The positioning member 123 can be formed by dispersing or printing a photosensitive plastic material (such as epoxy resin, polyimide, etc.) or a non-photosensitive material in the cavity 121, followed by removing the integral metal layer 12.

24 is a cross-sectional view and a plan view showing a structure in which a semiconductor element 31 is disposed on a dielectric layer 13 using an adhesive 16, wherein an adhesive 16 is disposed between the dielectric layer 13 and the semiconductor element 31, and the adhesive 16 contacts the dielectric layer 13 and Semiconductor element 31. The semiconductor element 31 is attached to the dielectric layer 13 with its active surface 311 facing the dielectric layer 13, wherein the dielectric layer 13 serves as the first insulating layer 211. The positioning member 123 extends from the dielectric layer 13 in the upward direction and extends The active surface 311 of the semiconductor element 31 is extended beyond the peripheral edge of the semiconductor element 31 to serve as a configuration guide for the semiconductor element 31.

25 is a cross-sectional view showing the structure in which the core layer 41, the second insulating layer 221, and the metal layer 22 are laminated. The core layer 41 contacts the semiconductor element 31, the positioning member 123, and the first insulating layer 211, and is pressed against the semiconductor element 31, the positioning member 123, and the first insulating layer 211. The second insulating layer 221 contacts the metal layer 22, the semiconductor element 31, and the core layer 41, and provides a stable mechanical connection between the metal layer 22 and the semiconductor element 31, and between the metal layer 22 and the core layer 41. The first insulating layer 211 and the second insulating layer 221 are preferably made of the same material.

FIG. 26 is a cross-sectional view showing the structure of the first blind hole 213 and the slit 411. The first blind via 213 extends through the support plate 15, the first insulating layer 211, and the adhesive 16 to expose the contact pads 312 of the semiconductor component. The slot 411 extends through the support plate 15, the first insulating layer 211, the core layer 41, and the second insulating layer 221 to expose selected portions of the metal layer 22.

Referring to FIG. 27, a first cladding layer 21' is deposited on the support plate 15 and deposited into the first blind via 213, and then the support panel 15 and the first cladding layer 21' thereon are patterned to the first insulating layer. A first wire 215 is formed on 211. The first wire 215 extends from the first insulating layer 211 in a downward direction, extends laterally on the first insulating layer 211, and extends into the first blind hole 213 in an upward direction to form a first conductive blind hole 217. Pad 312 is in direct contact. Moreover, the first covering layer 21' is further deposited in the slit 411 to provide the shielding slit 414, and is deposited on the metal layer 22, and then the metal layer 22 and the first covering layer 21' thereon are defined to define The cover 224 and the second wire 225 are shielded. The shielding slot 414 can serve as a horizontal barrier for the semiconductor component 31. And electrically connected to the ground contact pad of the semiconductor component 31 through the first wire 215. The shield cover 224 can serve as a vertical barrier of the semiconductor component 31 and is electrically connected to the ground contact pad of the semiconductor component 31 through the shield slot 414 and the first conductive line 215.

Accordingly, as shown in FIG. 27, the completed circuit board 400 includes the positioning member 123, the semiconductor element 31, the core layer 41, the shield slot 414, and the dual build-up circuits 202, 203. The first build-up circuit 202 covers the semiconductor element 31, the positioning member 123, and the core layer 41 in a downward direction, and the first build-up circuit 202 includes a first insulating layer 211 and a first conductive line 215. The second build-up circuit 203 covers the semiconductor element 31 and the core layer 41 in the upward direction, and the second build-up circuit 203 includes the second insulating layer 221 and the shield cover 224. The shield slot 414 contacts the first wire 215 and extends from the first wire 215 in an upward direction to the shield cover 224, and laterally covers the semiconductor component 31, and has an open end facing downward. The shield cover 224 covers the semiconductor element 31 in the upward direction and extends outward to the peripheral edge of the wiring board 400.

26' to 27' are cross-sectional views showing another embodiment of the shield slot 414 that is in electrical contact with the shield cover 224 and the first lead 215.

Figure 26' is a cross-sectional view showing the structure of the first blind hole 213 and the slit 411. The structure is similar to the structure shown in FIG. 26 except that the slits 411 extend through the metal layer 22, the second insulating layer 221, the core layer 41, and the first insulating layer 211 to expose selected portions of the support plate 15.

27' is a cross-sectional view of completed circuit board 500 in which a first lead 215, a shield slot 414, and a shield cover 224 are provided via metal deposition and patterning. The circuit board 500 is similar in structure to that shown in Figure 27 except for shielding The slot 414 has an open end facing upwardly and the shield cover extends laterally to the peripheral edge of the circuit board 500.

[Example 5]

28 to 30 are cross-sectional views showing a method of manufacturing another circuit board according to another preferred embodiment of the present invention, the circuit board including a shielding slot and a shielding cover electrically connected to the positioning member.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

Figure 28 is a cross-sectional view showing the structure produced by the same steps shown in Figures 22 to 25.

29 is a cross-sectional view showing the structure of the first blind hole 213, the slit 411, and the through hole 511. The first blind via 213 extends through the support plate 15, the first insulating layer 211, and the adhesive 16 to expose selected portions of the contact pads 312 and the locating members 123 of the semiconductor component 31 in a downward direction. The slot 411 extends through the metal layer 22, the second insulating layer 221, and the core layer 41 to expose selected portions of the keeper 123 in an upward direction. The through hole 511 extends through the metal layer 22, the second insulating layer 221, the core layer 41, the first insulating layer 211, and the support plate 15 in the vertical direction.

Referring to FIG. 30, the completed circuit board 600 is deposited and patterned via metal to provide a first lead 215, a shield slot 414, a shield cover 224, and a covered via 515. The first cladding layer 21 ′ is deposited on the support plate 15 and deposited into the first blind via 213 , and then the support layer 15 and the first cladding layer 21 ′ thereon are patterned to form a first layer on the first insulating layer 211 . Wire 215. The first wire 215 extends from the first insulating layer 211 in a downward direction. The first insulating layer 211 extends laterally and extends into the first blind via 213 in an upward direction to form a first conductive via 217 electrically in contact with the contact pad 312 and the positioning member 123.

Moreover, the first covering layer 21' is further deposited in the slit 411 and the through hole 511 to provide the shielding slit 411 and the covered through hole 515, and is deposited on the metal layer 22. In this embodiment, a combination of the metal layer 22 and the first cladding layer 21' serves as the shield cover 224 to provide a vertical barrier effect of the semiconductor element 31. The shielding slot 414 extends from the shielding cover 224 to the positioning member 123 in the downward direction, and is electrically connected to the ground contact pad of the semiconductor component 31 through the positioning member 123 and the first wire 215. The shielding cover 224 extends from the second insulating layer 221 in the upward direction and extends outwardly to the peripheral edge of the circuit board 600, that is, through the shielding slot 414, the positioning member 123 and the first wire 215, and is electrically connected to the semiconductor component 31. Ground contact pad. Moreover, the covered via 515 provides another electrical connection path between the shield cover 224 and the first build-up circuit 202, between the shield slot 414 and the first build-up circuit 202.

[Embodiment 6]

31 to 33 are cross-sectional views showing a method of manufacturing a further circuit board according to still another preferred embodiment of the present invention, wherein the shield cover is electrically connected to the first build-up circuit through a conductive groove in contact with the positioning member.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

31 is a cross-sectional view of the structure fabricated by the same steps shown in FIGS. 22 to 25, except that the semiconductor element 31 is disposed on the dielectric layer 13 with its inactive surface 313 facing the dielectric layer 13, and the first insulating layer 211 And metal The layer 21 is provided to cover the semiconductor element 31 and the core layer 41 in the upward direction. In this embodiment, the positioning member 123 extends from the dielectric layer 13 in the upward direction and extends beyond the inactive surface 313 of the semiconductor component 31. The core layer 41 contacts the semiconductor element 31, the positioning member 123, and the dielectric layer 13, and is pressed into the semiconductor element 31, the positioning member 123, and the dielectric layer 13, wherein the dielectric layer 13 serves as the second insulating layer 221. The first insulating layer 211 contacts the metal layer 21, the semiconductor element 31, and the core layer 41, and provides a stable mechanical connection between the metal layer 21 and the semiconductor element 31, and between the metal layer 21 and the core layer 41.

32 and 32A are a cross-sectional view and a bottom view, respectively, having a first blind hole 213, a groove hole 226, and a slit hole 411. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 to expose the contact pads 312 of the semiconductor component 31. The trench 226 extends through the support plate 15 and the second insulating layer 221 to expose selected portions of the positioning member 123 in a downward direction. The slit 411 extends through the metal layer 21, the first insulating layer 211, and the core layer 41 to expose selected portions of the positioning member 123 in the upward direction. As shown in FIG. 32A, the groove holes 226 are formed by mechanical cutting along the cutting lines of the four sides of the four alignment positioning members 123 through the support plate 15 and the second insulating layer 221.

33 is a cross-sectional view of completed circuit board 700 that is metal deposited and patterned to provide first lead 215, shield slot 414, shield cover 224, and conductive trench 228. The first cladding layer 21 ′ is deposited on the metal layer 21 and deposited into the first blind via 213 , and then the metal layer 21 and the first cladding layer 21 ′ thereon are patterned to form a first layer on the first insulating layer 211 . Wire 215. Moreover, the first coating layer 21' is further deposited into the slit 411 and the trench 226 to provide the shielding slot 414 and the conductive trench 228, and is deposited on the support plate. 15 on. In this embodiment, the combination of the support plate 15 and the first covering layer 21' is regarded as the shield cover 224. The combination of the shielding slot 414 and the positioning member 123 can serve as a horizontal barrier of the semiconductor component 31 and is electrically connected to the ground contact pad of the semiconductor component 31 through the first wire 215. The shielding cover 224 can serve as a vertical barrier of the semiconductor component 31 and is electrically connected to the ground contact pad of the semiconductor component 31 through the conductive trench 228, the positioning component 123, the shielding slot 414 and the first conductive line 215.

In another embodiment, as shown in FIG. 33', the shielding cover 224 is electrically connected to the positioning member 123 through the second conductive blind hole 227. Accordingly, in the circuit board 800, the shielding cover 224 is electrically connected to the ground contact pad of the semiconductor component 31 through the second conductive blind via 227, the positioning component 123, the shielding slot 414 and the first conductive line 215.

[Embodiment 7]

34 to 36 are cross-sectional views showing a method of manufacturing a further circuit board according to still another preferred embodiment of the present invention, wherein the shield cover is electrically connected to the first build-up circuit through the covered via.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

Figure 34 is a cross-sectional view showing the same structure as shown in Figure 31.

35 is a cross-sectional view showing the structure of the first blind hole 213, the slit 411, and the through hole 511. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 to expose the contact pads 312 of the semiconductor component 31. The trench hole 411 extends through the metal layer 21, the first insulating layer 211, and the core layer 41, and the selected portion of the positioning member 123 is exposed in the upward direction. Perforation 511 in the vertical The direction extends through the metal layer 21, the first insulating layer 211, the core layer 41, the second insulating layer 211, and the support plate 15.

36 is a cross-sectional view of a completed circuit board 900 that is metal deposited and patterned to provide a first lead 215, a shield slot 414, a shield cover 224, and a covered via 515. The first insulating layer 21 ′ is deposited on the metal layer 21 and deposited into the first blind via 213 , and then the metal layer 21 and the first cladding layer 21 ′ thereon are patterned to form a first layer on the first insulating layer 211 . Wire 215. Moreover, the first covering layer 21' is further deposited in the slit 411 and the through hole 511 to provide the shielding slit 414 and the covered through hole 515, and is deposited on the support plate 15. In this embodiment, a combination of the support plate 15 and the first covering layer 21' serves as the shield cover 224. The combination of the shielding slot 414 and the positioning member 123 can serve as a horizontal barrier of the semiconductor component 31 and is electrically connected to the ground contact pad of the semiconductor component 31 through the first wire 215. The shielding cover 224 can serve as a vertical barrier of the semiconductor component 31 and is electrically connected to the ground contact pad of the semiconductor component 31 through the covered via 515 and the first conductive line 215.

[Embodiment 8]

37 to 39 are cross-sectional views showing a method of manufacturing a three-dimensional stacked assembly according to a preferred embodiment of the present invention, the three-dimensional stacked assembly comprising a plurality of wiring boards stacked in a face-to-face manner.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

37 is a cross-sectional view showing the structure of an inner dielectric layer 261 between two adjacent circuit boards 110, 120. The circuit boards 110, 120 are the same as those shown in FIG. 27 except that the circuit boards 110, 120 further include a third insulating layer 231 and a Four insulating layers 241. The circuit boards 110, 120 are vertically stacked and bonded to each other by using an inner dielectric layer 261. The inner dielectric layer 261 is in contact with and located on the second insulating layer 221/shield cover 224/second wire 225 and the circuit board 120 of the circuit board 110. An insulating layer 211 / between the first wires 215. The third insulating layer 231 covers and contacts the first insulating layer 211 and the first conductive line 215 of the circuit board 110 in a downward direction, and includes a third blind via 233 that is aligned with a selected portion of the first conductive line 215. The fourth insulating layer 241 covers and contacts the second insulating layer 221 of the circuit board 120, the shielding cover 224 and the second conductive line 225 in the upward direction.

38 is a cross-sectional view of the structure having the perforations 511. The through holes 511 extend through the wiring boards 110, 120 and the inner dielectric layer 261 in the vertical direction.

Referring to FIG. 39, the circuit boards 110, 120 have a third wire 235 and a fourth wire 245, respectively. The third conductive layer 235 extends in the downward direction, extends laterally on the third insulating layer 231, and extends into the third blind via 233 to form a third conductive via 237 electrically connected to the first conductive line 215. Sexual contact. The fourth wire 245 extends in the upward direction from the fourth insulating layer 241 and laterally extends on the fourth insulating layer 241. As also shown in FIG. 39, the coated perforations 515 are formed by depositing metal in the perforations 511. Accordingly, the completed stack body 101 includes a plurality of circuit boards 110, 120, an inner dielectric layer 261, and a covered via 515. The circuit boards 110, 120 each include a positioning member 123, a semiconductor element 31, a core layer 41, a shielding slot 414, a first build-up circuit 202, and a second build-up circuit 203. The covered vias 515 are substantially shared by the circuit boards 110, 120 and extend through the inner dielectric layer 261 and the circuit boards 110, 120 to provide electrical connections between the circuit boards 110, 120.

[Embodiment 9]

40 to FIG. 42 are cross-sectional views showing a method of fabricating another three-dimensional stacked assembly according to another preferred embodiment of the present invention, the three-dimensional stacked assembly including a plurality of wiring boards stacked in a back-to-back manner.

For the purpose of brief description, any of the descriptions in Embodiment 1 may be incorporated in the same application portions herein, and the same description will not be repeated.

40 is a cross-sectional view showing the structure of an inner dielectric layer 261 provided between a plurality of wiring boards 130 and 140. The circuit boards 130 and 140 are the same as those shown in FIG. 3 and stacked vertically in a back-to-back manner, and are bonded to each other by an internal dielectric layer 261 disposed between the circuit boards 130 and 140 and contacting the circuit boards 130 and 140. Shield cover 224.

41 is a cross-sectional view showing the structure of the first blind hole 213, the slit 411, and the through hole 511. The first blind via 213 extends through the metal layer 21 and the first insulating layer 211 to expose the contact pads 312 of the semiconductor component 31 in each of the wiring boards 130, 140. The slot 411 extends through the metal layer 21, the first insulating layer 211, and the core layer 41 to expose selected portions of the shield cover 224 in each of the circuit boards 130, 140. The through holes 511 extend through the wiring boards 130, 140 and the inner dielectric layer 261 in the vertical direction.

Referring to FIG. 42, each of the circuit boards 130, 140 is deposited and patterned by metal to form a first conductive line 215. The first wire 215 extends perpendicularly from the first insulating layer 211 and extends laterally on the first insulating layer 211 and extends into the first blind via 213 to form a first conductive via 217 which is in contact with the semiconductor device 31. Electrical connection. As also shown in FIG. 42, metal is deposited in the slits 411 and the perforations 511 to form the shield slots 414 and the covered perforations 515. Accordingly, the completed stack body 102 includes the circuit boards 130, 140, and The dielectric layer 261 and the covered vias 515. Each of the circuit boards 130, 140 includes a positioning member 123, a shield cover 224, a shield slot 414, a semiconductor component 31, a core layer 41, and a build-up circuit 201. The coated vias 515 are substantially shared by the circuit boards 130, 140 and extend through the inner dielectric layer 261 and the circuit boards 130, 140 to provide electrical connections between the circuit boards 130, 140.

The above-mentioned circuit board and three-dimensional stacked assembly are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. The circuit board can include a plurality of array-sorted shield slots and shield covers for a plurality of side-by-side semiconductor components; and the build-up circuitry can include additional wires to accommodate additional semiconductor components, shield slots, and shield covers. Similarly, the board can include multiple array locators to accommodate additional semiconductor components.

The semiconductor component can be a packaged or unpackaged wafer. Further, the semiconductor element may be a bare wafer or a wafer level packaged die or the like. The locating member, the shielding cover, and the area defined by the shielding slot can be customized to accommodate a single semiconductor component. For example, the pattern of the locating member can be square or rectangular, and the 俾 is identical or similar in shape to a single semiconductor component. Each of the four shield slots can be defined as a square or rectangle, the shape of which is the same or similar to the shape of a single semiconductor component. Similarly, the shield cover can also be customized to be the same or similar to the shape of a single semiconductor component.

As used herein, the term "adjacent" means that the elements are integrally formed (forming a single individual) or in contact with one another (with or without separation from one another). For example, the contact pad is adjacent to the first wire but not adjacent to the second wire.

The term "overlapping" means located above and extending within the perimeter of a lower element. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, when the first build-up circuit surface faces upward, the first build-up circuit overlaps the semiconductor component because an imaginary vertical line can simultaneously penetrate the first build-up circuit and the semiconductor component, regardless of the first build-up circuit. Is there another element (such as an adhesive) that is also penetrated by the imaginary vertical line between the semiconductor element, and whether or not another imaginary vertical line penetrates only the first build-up circuit and does not penetrate the semiconductor element (semiconductor Outside the circumference of the component). Likewise, the first build-up circuitry is overlaid on the core layer and the core layer is overlaid by the first build-up circuitry. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

The term "contact" means direct contact. For example, the first conductive via contacts the contact pads of the semiconductor component, but the second conductive via does not contact the contact pads of the semiconductor component.

The term "overlay" means incomplete and complete coverage in the vertical and / or lateral directions. For example, in a state in which the first build-up circuit surface faces upward, the first build-up circuit covers the semiconductor element in an upward direction, whether or not another component (eg, an adhesive) is located between the semiconductor component and the first build-up circuit. between.

The "layer" word contains patterned and unpatterned layers. For example, when the metal layer is disposed on the dielectric layer, the metal layer can be a blank lithography plate that is not photolithographically and wet etched. In addition, a "layer" may comprise a plurality of superposed layers.

The terms "aligned" and "aligned" mean the relative position between elements, whether or not the elements are spaced apart from each other or adjacent, or a component is inserted and Extend into another component. For example, when an imaginary horizontal line penetrates the positioning member and the semiconductor element, the positioning member is laterally aligned with the semiconductor element regardless of whether there are other elements penetrated by the imaginary line between the positioning member and the semiconductor element, and whether or not there is another through semiconductor The component does not extend through the imaginary vertical line of the locating member, or another imaginary vertical line that extends through the locating member but does not extend through the semiconductor component. Likewise, the shield slot is laterally aligned with the semiconductor component, the first blind via is aligned with the contact pads of the semiconductor component, and the shield cap is aligned with the semiconductor component.

The term "close" means that the width of the gap between the elements does not exceed the maximum acceptable range. As is known in the art, when the gap between the semiconductor component and the positioning member is not sufficiently narrow, the positional error of the semiconductor component may exceed the acceptable maximum error limit due to the lateral displacement of the semiconductor component in the gap, once the semiconductor component When the position error exceeds the maximum limit, it is impossible to align the contact pads with the laser beam, resulting in an electrical connection error between the semiconductor element and the build-up circuit. Therefore, according to the size of the contact pads of the semiconductor element, those skilled in the art can confirm the maximum acceptable range of the gap between the semiconductor element and the positioning member by trial and error, thereby avoiding the electrical property between the semiconductor element and the build-up circuit. connection error. Thus, the term "the locating member is adjacent to the peripheral edge of the semiconductor component" means that the peripheral edge of the semiconductor component and the gap between the locating members are narrow enough to prevent the positional error of the semiconductor component from exceeding an acceptable maximum error limit.

The terms "set", "stack", "attach", and "attach" include contact and non-contact single or multiple support elements. For example, the semiconductor component is disposed on the shield cover, regardless of whether the semiconductor component is actually in contact with the shield The cover or the shield cover is separated by an adhesive.

The term "electrical connection" means direct or indirect electrical connection. For example, the coated perforations provide an electrical connection of the first wire whether it is adjacent to the first wire or electrically connected to the first wire via the third wire.

The term "upper" is intended to mean extending upwards and encompasses contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, when the first build-up circuit surface faces downward, the positioning member extends above it, adjoins the first insulating layer and protrudes from the first insulating layer.

The word "below" is intended to mean a lower extension and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, when the first build-up circuit surface faces downward, the first build-up circuit extends below the semiconductor component in a downward direction regardless of whether the first build-up circuit abuts the semiconductor component.

The "first vertical direction" and the "second vertical direction" do not depend on the orientation of the circuit board. Anyone familiar with the art can easily understand the direction in which they actually refer. For example, the active face of the semiconductor component faces the first vertical direction, and the inactive face of the semiconductor component faces the second vertical direction regardless of whether the board is inverted. The first end face of the shielding slot or the covered perforation faces the first vertical direction, and the second end surface of the shielding slot or the covered perforation faces the second vertical direction. Similarly, the locating member aligns the semiconductor components "laterally" along a lateral plane, regardless of whether the board is inverted, rotated or tilted. Thus, the first and second vertical directions are opposite to each other and perpendicular to the side direction, and the laterally aligned elements intersect in a lateral plane perpendicular to the first and second perpendicular directions. Furthermore, when the active surface of the semiconductor element faces downward In the first direction, the first vertical direction is the downward direction, and the second vertical direction is the upward direction; when the inactive surface of the semiconductor element faces the upward direction, the first vertical direction is the upward direction, and the second vertical direction is the downward direction.

The circuit board of the present invention and the three-dimensional stacked body using the same have a number of advantages. The shielding slot and the shielding cover can serve as horizontal and vertical EMI barriers for the semiconductor components, respectively, to reduce electromagnetic interference. Due to the high routing capability of the build-up circuitry, the signal routing provided by the add-on circuitry facilitates high I/O values and high performance applications. The positioning member can be selectively provided in the circuit board according to actual needs. For example, the locating member can serve as a precise configuration guide for the shielded semiconductor component. Since the semiconductor component is bonded to the build-up circuit or the shield cover by the adhesive, any displacement due to misconfiguration or adhesive backflow can be avoided during curing. Therefore, the reliability of the circuit board and the three-dimensional stacked group is high, the price is flat, and it is extremely suitable for mass production.

The production method of this case is highly applicable, and combines various mature electrical connection and mechanical connection technologies in a unique and progressive manner. In addition, the production method of this case can be implemented without expensive tools. As a result, this approach can significantly increase throughput, yield, performance and cost efficiency compared to traditional packaging techniques.

The embodiments described herein are illustrative, and the elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

Those skilled in the art will be able to readily appreciate various changes and modifications to the embodiments described herein. For example, the aforementioned materials, The dimensions, shape, size, steps, and sequence of steps are examples only. Variations, adjustments, and equalizations may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

While the invention has been described in terms of the preferred embodiments of the present invention, it is understood that modifications and changes may be made to the present invention without departing from the spirit and scope of the invention.

100‧‧‧ circuit board

11, 21‧‧‧ metal layer

123‧‧‧ Positioning parts

201‧‧‧Additional Circuit

211‧‧‧First insulation

21’‧‧‧First coating

215‧‧‧First wire

213‧‧‧ first blind hole

222‧‧‧ terminals

217‧‧‧First conductive blind hole

224‧‧‧Shield cover

31‧‧‧Semiconductor components

312‧‧‧Contact pads

311‧‧‧ active face

41‧‧‧ core layer

313‧‧‧Inactive surface

414‧‧‧Shield slot

411‧‧‧Slit hole

515‧‧‧ Covered perforation

511‧‧‧Perforation

Claims (15)

A circuit board having an embedded component and an electromagnetic barrier, comprising: a shielding cover; a semiconductor component disposed on the shielding cover by an adhesive, and the semiconductor component includes an active surface and opposite to the active surface a non-active surface having a plurality of contact pads, wherein the active surface faces a first vertical direction and faces away from the shielding cover, and the inactive surface faces a second opposite to the first vertical direction a vertical direction and facing the shielding cover; a core layer laterally covering the semiconductor component in a side direction perpendicular to the first vertical direction and the second vertical direction; a first build-up circuit from the first vertical Orienting the semiconductor device and the core layer, and the first build-up circuit is electrically connected to the contact pads of the semiconductor device through a plurality of first conductive vias; and the plurality of shield slots extend through The core layer laterally covers the semiconductor component and extends outwardly beyond the peripheral edge of the semiconductor component, wherein the shielding slots and the shielding cover pass through the first build-up layer And at least one of the contact pads is electrically connected to be grounded; and a positioning member is disposed as one of the semiconductor components, and the positioning member extends from the shielding cover toward the first vertical direction, adjacent to the The peripheral edge of the semiconductor component is laterally aligned with the peripheral edge of the semiconductor component. The circuit board of claim 1, further comprising: a second build-up circuit covering the shield cover and the core layer from the second vertical direction; A covered via extending through the core layer to electrically connect the first build-up circuit to the second build-up circuit. The circuit board of claim 1, wherein the shielding slots extend from the first build-up circuit toward the second vertical direction to the shield cover. The circuit board of claim 1, wherein the shielding slots extend from the first build-up circuit toward the second vertical direction to the positioning member. The circuit board of claim 1, wherein the shielding slots are each a continuous metallized slot and extend outwardly to a peripheral edge of the circuit board. The circuit board of claim 1, wherein the shielding cover is a continuous metal layer and extends outwardly beyond a peripheral edge of the semiconductor component. The circuit board of claim 1, wherein the positioning member comprises a continuous or discontinuous strip or array of studs. The circuit board according to claim 1, wherein a gap between the semiconductor element and the positioning member is in a range of 0.001 to 1 mm. The circuit board of claim 1, wherein the height of the positioning member is in the range of 10 to 200 μm. A circuit board having an embedded component and an electromagnetic barrier, comprising: a semiconductor component comprising an active surface and an inactive surface opposite to the active surface, the active surface having a plurality of contact pads, wherein the active Facing a first vertical direction, and the inactive surface faces a second perpendicular direction opposite to the first vertical direction; a core layer on a side perpendicular to the first vertical direction and the second vertical direction The direction laterally covers the semiconductor component; a first build-up circuit covering the semiconductor component and the core layer from the first vertical direction, and the first build-up circuit is electrically connected through the plurality of first conductive vias a contact pad connected to the semiconductor device; a second build-up circuit covering the semiconductor device and the core layer from the second vertical direction, and the second build-up circuit includes a shield cover Aligning the semiconductor component; a plurality of shielding slots extending through the core layer and laterally covering the semiconductor component and extending outwardly beyond a peripheral edge of the semiconductor component, wherein the shielding cover and the shielding slots And electrically connected to at least one of the contact pads to ground through the first build-up circuit; and a positioning member configured as a guide member of the semiconductor component, and the positioning component is configured A first shield cover extends toward the vertical direction, close to the peripheral edge of the semiconductor element, and laterally aligned with the peripheral edge of the semiconductor element. The circuit board of claim 10, wherein the shielding cover is electrically connected to the first build-up circuit through the shield slots, the shield slots being from the first build-up circuit The second vertical direction extends to the shield cover. The circuit board of claim 10, wherein the shielding slots extend from the first build-up circuit toward the second vertical direction to the positioning member. The circuit board of claim 12, wherein the shielding cover is electrically connected to the shielding slot through the shielding slot, the positioning member and the second conductive blind hole of the second build-up circuit A layer-up circuit. The circuit board of claim 12, wherein the shielding cover is electrically connected to the first build-up layer through the shielding slots, the positioning member and a conductive groove of the second build-up circuit Circuit. The circuit board of claim 12, wherein the shielding cover is electrically connected to the first build-up circuit through a covered perforation, the covered perforation extending through the core layer.