CN103594444B - There is between intermediary layer and coreless substrate the semiconductor subassembly of dual interface channel - Google Patents

There is between intermediary layer and coreless substrate the semiconductor subassembly of dual interface channel Download PDF

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Publication number
CN103594444B
CN103594444B CN201310350222.1A CN201310350222A CN103594444B CN 103594444 B CN103594444 B CN 103594444B CN 201310350222 A CN201310350222 A CN 201310350222A CN 103594444 B CN103594444 B CN 103594444B
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layer
intermediary layer
intermediary
coreless substrate
enhancement layer
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CN201310350222.1A
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Chinese (zh)
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CN103594444A (en
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林文强
王家忠
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钰桥半导体股份有限公司
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Priority to US13/917,776 priority patent/US20140048951A1/en
Priority to US13/917,776 priority
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
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Abstract

The invention relates to a kind of semiconductor subassembly between intermediary layer and coreless substrate with dual interface channel.This semiconductor subassembly includes semiconductor element, one has the intermediary layer of perforation, a coreless substrate and an enhancement Layer.This semiconductor element upside-down mounting is on this intermediary layer, and this intermediary layer is fixed on this coreless substrate via adhesive agent, and extends into a through hole of an enhancement Layer, and this enhancement Layer provides this coreless substrate mechanical support.Electric connection between this intermediary layer and this coreless substrate includes routing and conduction micropore, and this coreless substrate can provide and be route by the fan-out of this intermediary layer.

Description

There is between intermediary layer and coreless substrate the semiconductor subassembly of dual interface channel

Technical field

The present invention is about a kind of semiconductor subassembly, espespecially have on an intermediary layer upside-down mounting semiconductor element half Conductor assembly, wherein this intermediary layer is fixed on a coreless substrate.This intermediary layer has a perforation, and this intermediary layer and this nothing Connection between core substrate connects flexibly via conduction micropore and routing.

Background technology

High performance semiconductor chip generally uses the dielectric layer with low k-value as intermediate layer material.When having low k-value Dielectric material be cellular structure, fragility and docking port stress very sensitive time, there is traditional flip envelope of laminated substrate Dress can face owing between low k-value chip and laminated substrate, thermal coefficient of expansion does not mates, and cause various reliability issues with And the problem of qualification rate.In order to solve problem above, attempt the intermediary layer (such as silicon) by combining matched coefficients of thermal expansion and existed Between chip and laminated substrate, to attempt to lower interface stress.Additionally, intermediary layer more can provide superfine circuit to route, Therefore, before chip being connected to laminated substrate via perforation, first multiple chips are arranged on intermediary layer, pile up close with preparation height The preparation method of the semiconductor subassembly of degree and performance improvement is of concern.

Further it is provided that the laminated substrate of intermediary layer mechanical support and signal route generally includes a two-sided circuit Plate " core layer ", it has multiple " increasing layer " structure at each mask of core layer.This two-sided core layer uses multiple coating perforation As the connection of internal vertical, and use has the layer reinforced structure of micropore as connection between layers.For example, one 4-2-4 substrate refers to a kind of have four layer reinforced structures and be attached to the two-layer core layer of each, in order to lower a base plate for packaging Buckling deformation, it will usually use thickness to be about the core layer of 0.8-0.4 millimeter.The use of thick core layer can reduce buckling deformation Problem, but high-performance components is for the requirement of shorter route length, the most hardly possible reaches.Ask for solving this Topic, considerable research and development goes out a kind of coreless substrate with multiple reinforcement supporting member, to minimize warpage and deformation.

Therefore, by having the intermediary layer with perforation of similar thermal coefficient of expansion with silicon, with solve productivity ratio and Problem in terms of its reliability, and use the coreless substrate of seedless central layer with the method for the electrical property efficiency of improving assembly for very Preferably.

The U.S. Patent No. of the U.S. Patent No. of Ohno et al. 7,738,258, Lee et al. 8,183,678, The U.S. Patent No. of the U.S. Patent No. of Sanuhara 8,379,400, Rahman et al. 8,384, No. 225 and Wang U.S. Patent No. 8,310, No. 063 discloses a kind of assembly, and the silicon intermediary layer wherein with through hole is stacked in chip and lamination Between substrate, to provide the connection of side surface direction and vertical direction.Although the perforation of silicon intermediary layer can improve the performance of system, so And when the density of perforation is the highest, interfering between perforation will become a big limiting factor, additionally, the through hole that diameter is little And highdensity through hole can make production cost increase, and owing to yielding poorly, and the price of this product also will be enhanced.

The U.S. Patent No. 7 of the U.S. Patent No. of Ahn et al. 6,570, No. 248 and the 6th, 281, No. 042, Do et al., The U.S. Patent No. of 750, No. 452 and Pagaila et al. 8,263,434 discloses one and includes that a silicon intermediary layer is in base Modular construction in plate depression.It is positioned at silicon intermediary layer for pairing by forming the multiple perforation through silicon intermediary layer for micro Process Opposed surface on multiple semiconductor elements.This kind of structure can provide electrical performance excellent between the element of attaching, but The restriction of performance can be suffered from traditional routing technology intermediary layer and laminated substrate, and be only capable of receiving low amount Leaded molded.Additionally, when having different thermal coefficient of expansions between silicon from resin substrate, and intermediary layer is attached at hardly The sidewall of surrounding base, the fragility that underbraced is caused, and cross the character of thin and fragile due to intermediary layer and cause thermal cycle Journey is the problem such as easily crack so that the preparation of this kind of structure is made us hanging back, and unrealistic.

The U.S. Patent No. of the U.S. Patent No. of Lee et al. 7,902,660, Lin et al. 7,754,598, The U.S. Patent Application No. 2012/ of the U.S. Patent No. of Maruyamo et al. 8,227,703, Monensen et al. The U.S. Patent Application No. of No. 0005887 and Wu et al. 2012/0074209 discloses the centreless base of multiple encapsulation Plate structure.Some coreless substrates can have acceptable copline character via reinforcing material or the improvement of structure, but sticks up Bent phenomenon is generally when the size of substrate reaches certain size or the meeting when substrate meets with high-temperature process in component process Again occur.For example, when encapsulating a semiconductor chip more than 10 square millimeters, after the reflow of the solder, being total to of substrate Plane character may increased to over 30 microns, and for the requirement in encapsulation, is unacceptable.

U.S. of the U.S. Patent No. of Gfini 7,605,476, the U.S. Patent No. 7,663,245 of Lim, Liou et al. The U.S. Patent No. 7 of state's patent the 8th, 372, No. 692 and Shim et al., 309, No. 913 disclose a kind of modular construction, its There is the intermediary layer being stacked in semiconductor element and base plate for packaging, when intermediary layer does not have perforation to provide in vertical direction During shortest route, when system needs the signal sending or receiving high frequency, the signal integrity of component element will be by disadvantageous Impact.

Although document has been reported the component architecture of multiple use actively or passively intermediary layer, many performances or reliability Problem yet suffer from.For example, although using resin material to fill its interface to strengthen its structure, in order to connect silicon intermediary The problem that solder between layer and base plate for packaging may have reliability.

Summary of the invention

The present invention is to develop in view of above situation, its object is to provide a kind of semiconductor subassembly, wherein should be partly Conductor element upside-down mounting is on an intermediary layer, and this intermediary layer is fixed on as on a coreless substrate of mechanical support.One enhancement Layer Further support as this intermediary layer and this coreless substrate, can be used for suppressing warpage and the bending of assembly.This reinforcement Layer has a through hole, and this intermediary layer extends into the through hole of this enhancement Layer, and is electrically connected to this coreless substrate.This intermediary layer And being electrically connected with via in the one or more conductive through holes in this intermediary layer and this coreless substrate between this coreless substrate One or more conduction micropores and connect flexibly, and the routing formed by one or more mechanicalnesses is connected directly to this Centreless base meal, therefore can reduce the quantity of this conductive through hole of this intermediary layer, and can use routing balance according to the requirement of system It, thus the productivity of assembly and the cost received more tangible benefits can be improved.For example, the I/ of the power supply/ground connection of semiconductor element Os can connect via conductive through holes, and the I/Os of signal can connect via routing, and vice versa.Accordingly, the present invention provides A kind of composite circuit board and a kind of semiconductor subassembly, it semiconductor element including being electrically connected to composite circuit board, its In this composite circuit board include an intermediary layer, a coreless substrate and an enhancement Layer.

It is preferable to carry out in aspect one, such as the semiconductor element of microprocessor, controller or memory chip, can be through It is arranged on the first surface of this intermediary layer by a bump array upside-down mounting.But, at most of conditions, have more than one Chip need to be connected on this intermediary layer.For example, a logic chip may connect four memory chips with quickly Process data, or the segmentation logic chip of an array is connected to each other on an intermediary layer, compared to manufacturing single big core Sheet can reduce its cost.This projection can be solder, gold or the copper post through solder-coated, the selection of projection can be depending on its for The requirement of spacing.For example, in an element with the thinnest spacing, it is preferable to use the copper post of coated with solder, its Reason is in solder reflow process, and solder can be made to cave in small amount to avoid the bridge joint between solder.

Intermediary layer by made by silicon, pottery or glass, and can have multiple engagement pad on two contrary surfaces.Tool For body, in intermediary layer, face and multiple first engagement pad on a first surface of one first vertical direction, can be included, and one Or multiple joint refers to (bond finger), and face and there is on a second surface of one second vertical direction multiple second contact Pad.It is right that this first engagement pad on this first surface can be electrically connected to via vertical connecting element (such as conductive through holes) This second engagement pad on this second surface answered.Or, the first engagement pad on this first surface can be through being formed from This joint on this first surface that side in this intermediary layer is electrically connected with to circuit refers to.This circuit in this intermediary layer Can have one or more wiring layer, and signal can be distributed on a position in the lateral direction to other positions.Therefore, part This first engagement pad can be via vertical the connecting as the second engagement pad on second surface of conductive through holes, and other parts This first engagement pad can be connected to this joint of this first surface via circuit and refer to.Accordingly, when, in the chipset body of upside-down mounting, being somebody's turn to do half After conductor element is connected in the first engagement pad of this intermediary layer, the I/O connection pad of the semiconductor element of this upside-down mounting can be via leading Electroporation is connected in the second engagement pad of this intermediary layer, is then connected on this coreless substrate via conduction micropore, or can Being connected to this joint refer to, this joint refers to that this conductive through holes replacing in this intermediary layer with routing is to be electrically connected to this without duty base Plate.More particularly, this first engagement pad in the peripheral edge of this flip-chip can send/receive and wear from circuit, conduction Hole and the electronic signal of the second engagement pad, maybe can send/receive from circuit, engage refer to and the electronic signal of routing. Although this intermediary layer described by this enforcement aspect is a non-active element, it being understood, however, that can include whole to this intermediary layer Together in the transistor in this intermediary layer, consequently, it is possible to this intermediary layer can become a semiconductor element actively.

Routing can be made up of gold, aluminum, copper or its alloy.This routing is as between this intermediary layer and this coreless substrate Interface channel, and can have with this intermediary layer and engage one end of abutment, and with a connection gasket of this coreless substrate The other end connected.

This connection gasket of this coreless substrate can be made up of metal.For example, as the purpose connected, this connection gasket base In basis can by copper and through nickel, palladium, gold coating copper or its alloy formed.This routing can be in this first vertical direction by this Coreless substrate surface open, and in alignment with this through hole of this enhancement Layer, and extend to this through hole of this enhancement Layer.More specifically come Saying, this connection gasket can be in side surface direction lateral alignment in the peripheral edge of this intermediary layer and the side of this through hole of this enhancement Layer Wall, and extend laterally between the sidewall of the peripheral edge of this intermediary layer and this through hole of this enhancement Layer in side surface direction.Should Connection gasket is electrically connected to this connection gasket of this intermediary layer via this routing, it is possible to micro-via this conduction in this coreless substrate Hole and be electrically connected to the circuit of this coreless substrate.

This coreless substrate can cover this intermediary layer and this enhancement Layer in this second vertical direction, and includes one or more Connection gasket, one first dielectric layer and one or more first wire.For example, this first dielectric layer is second vertical in this Direction covers this intermediary layer, this connection gasket and this enhancement Layer, and extends to the peripheral edge of this assembly.This first dielectric layer Including one or more first micropores, and this micropore is arranged at this second engagement pad of this connection gasket adjacent and this intermediary layer, And optionally it is adjacent to this enhancement Layer.One or more first wires are arranged on this first dielectric layer (such as: from being somebody's turn to do First dielectric layer extends towards this second vertical direction, and extends laterally on this first dielectric layer) and in this first vertical direction Extend into this first micropore to form one or more conduction micropores, and this conduction micropore be electrically connected to this connection gasket and This second engagement pad, thus provide the signal of this second engagement pad of this connection gasket and this intermediary layer to route, and optionally Provide the electric connection of this enhancement Layer.Specifically, this first wire can directly contact this connection gasket and this second contact Pad, to provide the signal of this intermediary layer to route, therefore, the electric connection between this intermediary layer and this coreless substrate can be via double To passage, and can be free of solder.This first wire also can directly contact this enhancement Layer as ground connection, or adds as being arranged at this On strong layer such as the electric connection of the passive element such as thin film transistor (TFT) or capacitance body.

If any further signal route need, this coreless substrate can include extra dielectric layer, extra microporous layers, And extra conductor layer.For example, this coreless substrate can further include one second dielectric layer, one or more second Micropore and one or more second wire.Its this second dielectric layer being internally provided with one or more second micropore is arranged On this first dielectric layer and this first wire (such as: second vertical towards this from this first dielectric layer and this first wire Direction extends), and may extend to the peripheral edge of this assembly.This second micropore arranges and is adjacent to this first wire.One or many Individual second wire be arranged on this second dielectric layer (such as: from this second dielectric layer towards this second vertical direction extend, and in Extend laterally on this second dielectric layer), and extend into this second micropore to provide this first wire in this first vertical direction Electric connection.Additionally, this first micropore and this second micropore can have an identical size, and this first dielectric layer, this One wire, this second dielectric layer and this second wire can have elongated and smooth surface, and it faces this second Vertical Square To.

This coreless substrate can include connection gasket in one or more, with provide next stage assembly (such as mainboard) and/or another Electronic component (such as semiconductor element) or the electric connection of second half conductor assembly (such as BGA semiconductor subassembly).This interior connection gasket This first wire can be extended in this second vertical direction, or extend beyond this first wire, and include one face this second hang down Nogata is to the contact surface appeared.For example, this interior connection gasket can adjoin and integrally formed with this second wire.Additionally, should First wire and this second wire can provide between the second engagement pad of this interior connection gasket, this connection gasket and this intermediary layer It is electrically connected with.Therefore, this electric connection point is (such as: this first engagement pad of this intermediary layer and the interior connection of this coreless substrate Pad) can be electrically connected to each other, and be seated in the opposed surface facing opposed vertical direction, make one or more semiconductor chip Can upside-down mounting on semiconductor assembly.

This enhancement Layer has a through hole, and may extend to the peripheral edge of this assembly, to provide this coreless substrate and should The mechanical support of intermediary layer, and this enhancement Layer can be single layer structure or multiple structure (such as one wiring board or multi-layer ceramics Version or the laminate of substrate and conductive layer).This enhancement Layer can be by made by pottery, metal or other inorganic material, such as oxidation Aluminum (Al2O3), aluminium nitride (AlN), silicon nitride (SiN), silicon (Si), copper (CU, copper alloy (such as: Cu/Mo/Cu), aluminum (AI), no Rust steel etc..This enhancement Layer also can be by as made by the organic material of copper-clad laminate.

This coreless substrate of the present invention can further include positioning piece, and this keeper is as the configuration of this intermediary layer Guiding element, and lateral alignment is in the peripheral edge of this intermediary layer and this connection gasket, and in the peripheral edge of this intermediary layer and this even Connection pad lateral extends, during to prevent from attaching this intermediary layer, and the unnecessary displacement of this intermediary layer.In the case of any, should Intermediary layer and this keeper in alignment with this through hole of this enhancement Layer, and can extend into this through hole of this enhancement Layer.This location Part can be by prepared by the metal such as copper, aluminum, nickel, ferrum, stannum or its alloy.

The coreless substrate of the present invention can also include a configuration guiding element, and the configuration guiding element of this enhancement Layer can be near this enhancement Layer Peripheral edge, lateral alignment is in the peripheral edge of this enhancement Layer, and extends in the peripheral edge lateral of this enhancement Layer.Such as this Keeper, the configuration guiding element of this enhancement Layer can be by made by the metal such as copper, aluminum, nickel, ferrum, stannum or its alloy.

This keeper, this configuration guiding element and this connection gasket can contact this first dielectric layer of this coreless substrate, and from being somebody's turn to do This first dielectric layer of coreless substrate extends towards this first vertical direction, and can be formed with identical material (such as copper) simultaneously.Additionally, This keeper and this configuration guiding element can have pattern to avoid the unnecessary movement of this intermediary layer and this enhancement Layer respectively.Lift For example, this keeper and this configuration guiding element can include a continuous or discrete batten or protruded stigma array, this keeper with And this configuration guiding element can concurrently form and have identical or different pattern.Specifically, this keeper can be laterally aligned in this Four side surfaces of interlayer, to stop the lateral displacement of this intermediary layer.For example, this keeper can be along the four of intermediary layer Gap between side, two diagonal angles or the alignment of four angles, and this intermediary layer and this keeper is preferably from about in 0.001 to 1 millimeter Within the scope of, this intermediary layer can be kept at a distance by the inwall of this keeper and this connection gasket with this through hole, and can add Grafting material between this intermediary layer and this enhancement Layer to increase its rigidity.In like manner, this configuration guiding element can be laterally aligned in this Four outer surfaces of enhancement Layer, to stop the lateral displacement of this enhancement Layer.For example, this configuration guiding element can be along this reinforcement Align in four lateral surface of layer, two outer diagonal angles or four exterior angles, and between the peripheral edge of this enhancement Layer and this configuration guiding element Gap preferably from about within the scope of 0.001 to 1 millimeter, additionally, the thickness range of this keeper and this configuration guiding element is excellent Elect 10 to 200 microns as.

This intermediary layer and this enhancement Layer an adhesive agent can be used to fix and mechanical be connected to this coreless substrate should On first dielectric layer.This adhesive agent can contact this intermediary layer, this enhancement Layer, this keeper, this configuration guiding element and this first Jie Electric layer, and between this intermediary layer and this coreless substrate, and between this enhancement Layer and this coreless substrate.In office In the case of He, this adhesive agent can with this keeper, this configuration guiding element and this be connected and be padded on this second vertical direction copline, And in first vertically below this keeper, this configuration guiding element and this connection gasket.Below this intermediary layer and this enhancement Layer This adhesive agent in this first vertically below this keeper and this configuration guiding element time, this keeper and this configuration guiding element The unnecessary displacement that this intermediary layer and this enhancement Layer cause can be prevented because of solidification adhesive agent.

Present invention provides a kind of 3 D semiconductor assembly, wherein this intermediary layer is an active semiconductor element.At this Plant in application, as one first semiconductor element of chip can use various connection medium to be electrically connected to being somebody's turn to do by this enhancement Layer This first engagement pad of this intermediary layer (such as semiconductor chip) that through hole appears, this connection medium includes gold, solder or copper post Salient point.

The present invention has many advantages, the conductive through holes in this intermediary layer can improve the power supply stability attaching chip. In addition to the perforation in this intermediary layer, this routing can provide the interior connection substituted between this intermediary layer and this coreless substrate to lead to Road, thus decrease the number of holes required in intermediary layer.Therefore, the size of this intermediary layer can be reduced, or due to this intermediary layer In relatively low density of such perforation, the productivity of this product can be improved.Therefore, increase routing can significantly reduce this intermediary layer and be somebody's turn to do half The cost of conductor assembly.This keeper of this coreless substrate can limit the placement location of this intermediary layer exactly, with avoid this because of The lateral displacement of this intermediary layer causes the electric connection mistake between this intermediary layer and this coreless substrate, and then significantly improves Conforming product rate.Electric connection between this intermediary layer and this coreless substrate is directly connected to without solder, is thus advantageous to Represent high I/O value, high-performance and high-reliability.This enhancement Layer can provide the platform of power supply/ground connection, radiating seat and this intermediary Layer and the stable mechanical support of this coreless substrate.The reliability using its this semiconductor subassembly is high, cheap and non- Often it is suitable for manufacturing production in a large number.

Accompanying drawing explanation

With reference to annexed drawings, the present invention can be of greater clarity, wherein by the narration in detail of embodiments discussed below:

Figure 1A-1J is in the present invention one enforcement aspect, including an intermediary layer, semiconductor chip, an enhancement Layer, Yi Ji electricity Property is connected to the manufacture method sectional view of the semiconductor subassembly of a coreless substrate of this intermediary layer.

Fig. 1 K is in the present invention one enforcement aspect, is attached at the three-dimensional group of composite circuit board both sides including semiconductor element Part sectional view.

Fig. 2 be in another enforcement aspect of the present invention for have between this enhancement Layer and this coreless substrate one extra in Portion connects and a radiating seat is attached at the three-dimensional micromodule sectional view on this semiconductor chip and this enhancement Layer.

[symbol description]

Composite circuit board 101 keeper 113 connection gasket 111

Adhesive agent 131 metal level 11 configures guiding element 115

Semiconductor subassembly 110,210 gripper shoe 23 coreless substrate 20

Opening 293 first wire 241 coating 24

Connection gasket 284 in first dielectric layer 21 second wire 281

Second dielectric layer 261 first micropore 213 welding resisting layer material 291

First conduction micropore 243 second micropore 263 second conduction micropore 283

Three-dimensional micromodule 310 first surface 311 second surface 313

Intermediary layer 31 first engagement pad 312 second engagement pad 314

Routing 321 conductive through holes 318 engages and refers to 316

Lateral circuit 320 enhancement Layer 41 through hole 411

Semiconductor chip 51,53 solder projection 61,63 encapsulant 71

Radiating seat 81 heat conduction adhesive agent 801

Detailed description of the invention

Hereinafter, it will thus provide embodiment is to describe the enforcement aspect of the present invention in detail.Other advantages of the present invention and Effect is the most notable by the content by disclosed herein.It should be noted that, those annexed drawings are the accompanying drawing simplified, Component count shown in accompanying drawing, shape and big I are modified according to physical condition, and the configuration of element may be more For complexity.The present invention also can carry out otherwise practice or application, and without departing substantially from spirit and scope defined in the present invention Under conditions of, various change and adjustment can be carried out.

[embodiment 1]

Figure 1A-1J is in the enforcement aspect according to the present invention, the manufacture method of semiconductor assembly, this semiconductor subassembly Including an intermediary layer, semiconductor chip, an enhancement Layer and a coreless substrate, this coreless substrate is via routing and conduction Micropore is electrically connected to this intermediary layer.

As shown in figure ij, semiconductor subassembly 110 includes intermediary layer 31, enhancement Layer 41, semiconductor chip 51, coreless substrate 20 and routing 321.Intermediary layer 31 includes second surface 313 that first surface 311 is contrary with first surface 311, in first The first engagement pad 312 on surface 311 and engaging refers to 316, the second engagement pad 314 on second surface 313, part connect To the first engagement pad 312 and the conductive through holes 318 of the second engagement pad 314 and be electrically connected to joint and refer to 316 and part The lateral circuit 320 of the first connection pad 312.Intermediary layer 31 can be a silicon intermediary layer, a glass intermediary layer or pottery intermediary layer, It comprises wire pattern, this wire pattern is fanned out to the second engagement pad 314 by the fine pitch of part the first engagement pad 312 Thick spacing, and also include a wire pattern, this conductive pattern extends laterally to joint from the first engagement pad 312 of part and refers to 316. Coreless substrate 20 is electrically connected to intermediary layer 31, and includes connection gasket 111, keeper 113, configuration guiding element the 115, first dielectric layer 21, the first wire the 241, second dielectric layer 261 and the second wire 281.Keeper 113 is from the first dielectric layer 21 upward To extension, and near the peripheral edge of intermediary layer 31.Connection gasket 111, keeper 113 and intermediary layer 31 are aligned in enhancement Layer The through hole 411 of 41, and extend into the through hole 411 of enhancement Layer 41.

Figure 1A is the sectional view of a laminated substrate, and this laminated substrate includes metal level the 11, first dielectric layer 21 and supports Plate 23.The layers of copper that metal level 11 is thickness 35 microns shown in figure.But, metal level 11 is alternatively various metal materials, and It is not only restricted to layers of copper.Additionally, metal level 11 can be deposited on dielectric layer 21 by various technology, including lamination, plating, nothing Electricity electroplate, is deposited with, sputtering and combinations thereof with the structure of deposition single or multiple lift, and its thickness is preferably the model of 10 to 200 microns In enclosing.

First dielectric layer 21 usually epoxy resin, glass epoxy resin, poly-imines of indulging in, and the like made, and There is the thickness of 50 microns.In in terms of this enforcement, the first dielectric layer 21 is between metal level 11 and gripper shoe 23.So And, gripper shoe 23 in some aspects under can be omitted.Gripper shoe 23 is generally by made by copper, but copper alloy and other materials are all Can be used, the thickness of gripper shoe 23 can be in the range of 25 to 1000 microns, and using technique and cost as consideration, it is excellent Elect as in the range of 35 to 100 microns.In in terms of this enforcement, gripper shoe 23 is the copper coin of thickness 35 microns.

Figure 1B and 1B' is respectively and forms connection gasket 111, keeper 113 and configuration guiding element 115 in the first dielectric layer 21 On structure sectional view and top view.Connection gasket 111, keeper 113 and configuration guiding element 115 can be by photoetching processes and wet Formula etching method removes the selected position of metal level 11 and is formed, and at this in diagram, as shown in Figure 1B ', keeper 113 comprises rectangle Multiple metal protruded stigmas of array, and be consistent with four sides of the intermediary layer being arranged at subsequently on dielectric layer 21.Similarly, configuration Guiding element 115 comprise rectangle fall row multiple metal protruded stigmas, and with the four of the enhancement Layer 41 being arranged at subsequently on the first dielectric layer 21 Individual side is consistent.But, the form of keeper 113 and configuration guiding element 115 is not only restricted to this, and can be to prevent from arranging subsequently Any pattern of the unnecessary displacement of intermediary layer and enhancement Layer.For example, keeper 113 and configuration guiding element 115 also may be used Be made up of continuous or discrete batten, and meet four sides of intermediary layer and the enhancement Layer arranged subsequently, two right Angle or four corners.Additionally, keeper 113 and configuration guiding element 115 are to omit, but in view of the element configured subsequently Degree of accuracy, keeper 113 and configuration guiding element 115 exist for preferably.

Fig. 1 C is to use adhesive agent 131 that intermediary layer 31 is arranged at the structure sectional view on the first dielectric layer 21.Intermediary layer 31 include second surface 313 that first surface 311 is contrary with first surface 311, the first engagement pad on first surface 311 312 and engage refer to 316, on second surface 313 the second engagement pad 314, be electrically connected to part the first engagement pad 312 And second the conductive through holes 318 and being electrically connected to of engagement pad 314 engage and refer to 316 and the first engagement pad 312 of part Lateral circuit 320.Intermediary layer 31 can be a silicon intermediary layer, a glass intermediary layer or a ceramic dielectric layers, it comprises wire Pattern, this wire pattern is fanned out to the thick spacing of the second engagement pad 314 by the fine pitch of part the first engagement pad 312, and goes back Including a wire pattern, this conductive pattern extends laterally to joint from the first engagement pad 312 of part and refers to 316.

Keeper 113 can as the configuration guiding element of intermediary layer 31, and thus intermediary layer 31 be precisely placed in one make a reservation for On position, and its second surface 313 faces the first dielectric layer 21.Keeper 113 from the first dielectric layer 21 upward to extension, And extend beyond the second surface 313 of intermediary layer 31, and in side surface direction lateral alignment in four sides of intermediary layer 31, and in The lateral, four sides of intermediary layer 31 extends.When keeper 113 near four sides of intermediary layer 31 and meets intermediary layer 31 Four sides, and adhesive agent under intermediary layer 31 131 less than keeper 113 time, intermediary layer 31 can be avoided to stick together in solidification Any unnecessary displacement during agent.Preferably, the gap between intermediary layer 31 and keeper 113 is at 0.001 to 1 millimeter In the range of.

Fig. 1 D is to use adhesive agent 131 that enhancement Layer 41 is arranged at the structure sectional view on the first dielectric layer 21.Intermediary layer 31, keeper 113 and connection gasket 111 are in alignment with the through hole 411 of enhancement Layer 41, and insert the through hole 411 of enhancement Layer 41.Logical Hole 411 is formed on enhancement Layer 41 by laser drill, it is possible to formed by other technology holed such as punching press and mechanicalness. Enhancement Layer 41 in accompanying drawing is about the potsherd of 0.6 millimeter for thickness but it also may be other single or multiple lift structures, such as multilamellar Circuit board, glass plate or metallic plate.

The medial wall of intermediary layer 31 and through hole 411 by keeper 113 and connection gasket 111 with keep each other away from From, in this figure, enhancement Layer 41 can be arranged on a precalculated position exactly via configuration guiding element 115, configures guiding element 115 From the first dielectric layer 21 upward to extension, and extend beyond the wall-attached surface of enhancement Layer 41, and extend laterally beyond reinforcement Four peripheral edges of layer 41, and four peripheral edges of lateral alignment enhancement Layer 41, it addition, sticking together under enhancement Layer 41 Agent 131 is less than configuration guiding element 115.When configuration guiding element 115 is close in side surface direction and meets four outer surfaces of enhancement Layer 41, And the adhesive agent 131 under enhancement Layer 41 is less than when configuring guiding element, thus can avoid enhancement Layer 41 before adhesive agent 131 is fully cured There is any unnecessary displacement.Preferably, the gap between enhancement Layer 41 and configuration guiding element 115 is in the model of 0.001 to 1 millimeter In enclosing.

Fig. 1 E is to be formed through gripper shoe the 23, first dielectric layer 21 and the first micropore 213 of adhesive agent 131, to appear Second engagement pad 314 and the structure sectional view of connection gasket 111.First micropore 213 can be formed by various technology, and it includes swashing Light boring, etc. from body etching and photoetching technique.Pulse laser can be used to improve laser drill usefulness, or, metal can be used Mask and scanning laser beam.For example, copper coin can first be etched to manufacture after a metal window irradiating laser bundle again.First is micro- Hole 213 is generally of the diameter of 50 microns.With reference to Fig. 1 F, the first wire 241 being formed on the first dielectric layer 21 is via deposition Coating 24 is in gripper shoe 23, and is deposited in the first micropore 213, then patterning gripper shoe 23 and thereon coating Layer 24 and formed.Or, when laminated substrate does not have gripper shoe 23 or removes some realities of gripper shoe 23 after the step of Fig. 1 D Execute in aspect, can be after forming the first micropore 213, direct metallized the first dielectric layer 21 is to form the first wire 241.

Coating 24 can form single or multiple lift structure by various deposition techniques, and it includes plating, electroless-plating, steaming Plating, sputtering and combinations thereof.For example, deposition coating 24 first passes through and this structure is immersed in activator solution, makes first Dielectric layer 21 and electroless copper produce catalyst reaction, are then coated to a thin copper layer as crystal seed layer in electroless-plating mode, so After with plating mode, the second layers of copper of desired thickness is formed on crystal seed layer.Or, on the seed layer before deposition copper electroplating layer, This crystal seed layer can form the crystal seed layer thin film such as titanium/copper by sputtering mode, once reaches required thickness, can use various Technology patterning gripper shoe 23 and coating 24 are to form the first wire 241, and it includes wet etching, electrochemical etching, laser Auxiliary etch and the combination with etch mask (not shown) thereof, to define the first wire 241.Therefore, the first wire 241 is from One dielectric layer 21 to extension, extends laterally on the first dielectric layer 21, and it is micro-to extend into first in upward direction downward Hole 213 is with the first conduction micropore 243 being electrically connected to the second engagement pad 314 and connection gasket 111.

For convenience of description, gripper shoe 23 and coating thereon 24 represent with simple layer, owing to copper is homogeneity quilt Covering, the boundary line (all illustrating with dotted line) of metal interlevel may be difficult to discover even cannot be discovered, but coating 24 and first is situated between Boundary line between electric layer 21 is the most clearly visible.

Fig. 1 G is the section of structure being arranged at by the second dielectric layer 261 on first wire 241 and the first dielectric layer 21. Second dielectric layer 261 can be epoxy resin, glass epoxy resin, polyimides, and the like made, and via various skills Art is formed, and it includes mould conjunction, running roller coating, rotary coating and spray deposition, and is generally of the thickness of 50 microns.Preferably Ground, the first dielectric layer 21 and the second dielectric layer 261 are identical material.

Fig. 1 H is to form the second micropore 263 through the second dielectric layer 261, to appear the selected part of the first wire 241 Structure sectional view.Such as the first micropore 213, the second micropore 263 can be formed by various technology, it include laser drill, etc. Plasma etching and photoetching technique, and its diameter is usually 50 microns.Preferably, the first micropore 213 and the second micropore 263 have There is identical size.

With reference to Fig. 1 I, on the second dielectric layer 261, form the second wire 281 to complete composite circuit board 101.Compound circuit Plate 101 includes intermediary layer 31, enhancement Layer 41 and coreless substrate 20.In this figure, coreless substrate 20 include keeper 113, Connection gasket 111, configuration guiding element 115 and include first dielectric layer the 21, first wire the 241, second dielectric layer 261 and second The build-up circuitry of wire 281.Second wire 281 from the second dielectric layer 261 downward to extension, and in the second dielectric layer 261 On extend laterally, and extend into the second micropore 263 to be formed and second the leading of the first wire 241 electric connection in upward direction Electricity micropore 283.

Second wire 281 can be a conductive layer via various deposition techniques, it include plating, electroless-plating, sputtering and Combination, then pattern this conductive layer via various modes, it include wet etching, electrochemical etching, laser assisted etching and With the combination of etch mask (not shown), to define the second wire 281.Preferably, the first wire 241 and the second wire 281 use identical material and have identical thickness.

Intermediary layer 31 and enhancement Layer 41 are attached on the first dielectric layer 21 via adhesive agent 131, in adhesive agent 131 contact Interlayer 31 and the first dielectric layer 21, and between intermediary layer 31 and the first dielectric layer 21 and enhancement Layer 41 and the first dielectric layer Between 21, intermediary layer 31 and enhancement Layer 41 are by the keeper 113 between intermediary layer 31 and enhancement Layer 41 and centreless The connection gasket 111 of substrate 20 and with keep at a distance each other.Keeper 113, connection gasket 111 and configuration guiding element 115 are situated between from first The bright upward direction of electric layer 21 extends, and wherein keeper 113 is positioned at keeper near peripheral edge, the connection gasket 111 of intermediary layer 31 Between the peripheral edge of 113 and the medial wall of enhancement Layer 41, and configure the guiding element 115 periphery near the lateral wall of enhancement Layer 41 Edge.If glutinous agent 131 contacts keeper 113, connection gasket 111 and configuration guiding element 115, and in downward direction with keeper 113, connection gasket 111 and configuration guiding element 115 copline, and in upward direction less than keeper 113, connection gasket 111 and Configuration guiding element 115.

As shown in figure ij, the joint utilizing connection gasket 111 and intermediary layer 31 that routing 321 is electrically connected with coreless substrate 21 refers to 316, and via the solder projection 61 in the first engagement pad 312 of intermediary layer 31 by semiconductor chip 51 upside-down mounting in intermediary layer 31 First surface 311 on.First wire 241 of coreless substrate 20 directly contacts with the second engagement pad 314 of intermediary layer 31.First Wire 241 also directly contacts with connection gasket 111, and the connection gasket 111 of coreless substrate 21 is electrically connected to intermediary via routing 321 The joint of layer 31 refers to 316.Thus, the electric connection between intermediary layer 31 and coreless substrate 20 is led via routing 321 and first The electricity combination of micropore 243 and connect flexibly, and without solder between intermediary layer 31 and coreless substrate 20.Accordingly, in upside-down mounting After chipset body, the connection between semiconductor chip 51 and coreless substrate 20 can be via the first engagement pad 312 of intermediary layer 31, conduction Perforation 318 and the second engagement pad 314 of intermediary layer 31, be then connected to coreless substrate 20 via micropore, pass through intermediary simultaneously The joint of layer 31 refers to 316, then passes through routing and is connected to coreless substrate 20.

Fig. 1 K is to have semiconductor subassembly 210 sectional view that second half conductor chip 53 is attached on coreless substrate 20.Half Conductor chip 53 is in alignment with the allocation position of intermediary layer 31, and is electrically connected to via the solder projection 63 on interior connection gasket 284 Coreless substrate 20, interior connection gasket 284 appears from the opening 293 of welding resisting layer material 291.Accordingly, semiconductor chip 51,53 can be via Intermediary layer 31, coreless substrate 20 and solder projection 61,63 are electrically connected to each other.

Additionally, appear from the opening 293 of welding resisting layer material 291 remaining in connection gasket 284 can accommodate a conductive contact, As solder projection, stannum ball, pin, and the like, using electrically interconnection and mechanicalness as other assemblies or outer member Attach.Welding resisting layer opening 293 can be formed by various methods, and it includes photoetching process, laser drill and plasma etching.

[embodiment 2]

Fig. 2 be according to another enforcement of the present invention in terms of another three-dimensional micromodule 310 have and directly contact with intermediary layer 41 Extra first conduction micropore 243, using as ground connection or the structure sectional view of the electric connection with passive element.Fig. 2 also shows that Encapsulant 71 and radiating seat 81.Encapsulant 71 (such as molding compounds) fills through hole 411 and the company of covering in upward direction Connection pad 111, keeper the 113, first dielectric layer 21 and intermediary layer 31.Radiating seat 81 (such as copper or aluminum) is via heat conduction adhesive agent 801 be attached at enhancement Layer 41 and semiconductor chip 51 with assist heat radiation, and radiating seat 81 in upward direction cover enhancement Layer 41, Encapsulant 71 and semiconductor chip 51.

Above-mentioned semiconductor subassembly and wiring board are only illustrative example, and the present invention still can be real by other various embodiments Existing.Additionally, above-described embodiment can be based on design and the consideration of reliability, the collocation that is mixed with each other uses or mixes with other embodiments Collocation uses.Such as, enhancement Layer can include ceramic material or epoxies layered product, and can be embedded with layer of wires or multilamellar is led Line.Enhancement Layer can include multiple through hole to accommodate extra intermediary layer, passive element or other electronic components, and coreless substrate Extra wire can be included, to accommodate high I/O element, passive element or other electronic components.

As shown in above-described embodiment, the semiconductor element of the present invention can be used alone or share one with other semiconductor elements Intermediary layer.Such as, single semiconductor element can be arranged on intermediary layer, or multiple semiconductor elements are arranged at intermediary layer On.For example, the small chip that four pieces are arranged in 2 × 2 arrays can be attached on intermediary layer, and this intermediary layer can provide use In extra chips extra electric connection point with receive extra chips pad route.Compare each chip and one intermediary layer is set, this The practice more economic benefit.Similarly, the through hole of enhancement Layer can include organizing more keeper with accommodate multiple extra intermediary layers in Wherein, and build-up circuitry can include that extra wire is to accommodate extra intermediary layer.

The semiconductor element of this case can be to have encapsulated or unpackaged chip.Additionally, this semiconductor element can be bare chip or Wafer-level packaging chip (wafer level packaged die) etc..Available multiple connection medium is by semiconductor element machinery Property connect and be electrically connected to intermediary layer, including utilize gold or solder bump.Keeper can customize according to intermediary layer (customized), for example, the pattern of keeper can be square or rectangle, with or phase identical with the shape of intermediary layer Seemingly.Heat dissipation element such as fin or radiating seat can be attached at semiconductor element via electrical conductivity adhesive agent or welding material, should Heat dissipation element also can be attached at enhancement Layer to extend contact area to increase the sinking path efficiency of semiconductor element.

In this article, " adjoin " word mean element be one-body molded (forming single individuality) or contact with each other (each other without It is spaced or is not separated by).Such as, the first wire is adjacent to the second engagement pad, but is not adjacent to the first engagement pad.

In " overlapping " word means periphery that is above and that extend a lower element." overlapping " comprises and extends this week Edge inside and outside or be seated in this periphery.Such as, when the second engagement pad of intermediary layer faces upward direction, enhancement Layer is overlapping In dielectric layer, this is because an imagination vertical line can run through this enhancement Layer and this dielectric layer simultaneously, no matter enhancement Layer and dielectric Whether there is another element worn by this imagination vertical line person equally (such as adhesive agent) between Ceng, and the most whether has another false Think vertical line only to run through dielectric layer and do not run through enhancement Layer (being positioned at the through hole of enhancement Layer).Similarly, adhesive agent is overlapped in Jie Electric layer, enhancement Layer is overlapped in adhesive agent, and the enhancement Layer agent that gets adhered is overlapping.Additionally, " overlapping " and " above " synonym, " quilt Overlapping " then with " being positioned at lower section " synonym.

" contact " word to mean directly to contact.Such as, conductive contact the second engagement pad but and not in contact with the first engagement pad.

" cover " word refer in vertical and/or side surface direction not exclusively and be completely covered.Such as, at intermediary layer Under the state that first engagement pad faces upward direction, coreless substrate covers intermediary layer in downward direction, but intermediary layer not to Upper direction covers coreless substrate.

" layer " word comprises patterning and non-patterned layer body.Such as, when metal level is arranged on dielectric layer, metal level Can be the non-photoetching of blank and a flat board for wet etching.Additionally, " layer " can comprise multiple layer that coincides.

The word such as " opening ", " through hole " and " perforation " refers to together perforated holes.Such as, the first engagement pad of intermediary layer is facing to upper During direction, intermediary layer is inserted in the through hole of enhancement Layer, and manifests in upward direction is by enhancement Layer.

" insert " word and mean interelement relative movement.Such as, " intermediary layer is inserted in through hole " no matter being enhancement Layer For maintaining static and intermediary layer moves towards enhancement Layer;Intermediary maintains static layer by layer and is moved layer by layer towards intermediary by enhancement Layer;In or Interlayer and enhancement Layer closing each other.The most such as, comprise " by intermediary layer insertion (or extending to) through hole ": run through and (penetrate And pass) through hole;And insert but do not run through (penetrate but do not pass) through hole.

" it is directed at " word and means interelement relative position, no matter keeping at a distance the most each other between element or adjacent, or One element inserts and extends in another element.Such as, when imaginary horizontal line person wears keeper and intermediary layer, keeper Lateral alignment is in intermediary layer, no matter whether having the element that other horizontal lines being supposed to run through between keeper and intermediary layer, And whether there is another run through intermediary layer but not through the vertual (virtual) horizontal line of keeper.Similarly, the first micropore in alignment with Second engagement pad of intermediary layer, and intermediary layer and keeper are in alignment with through hole.

" close " word means that the width in interelement gap is less than maximum acceptable scope.As existing in this area logical Know, when gap when between intermediary layer and keeper is the narrowest, the position caused due to intermediary layer lateral displacement in gap Putting error and may exceed the restriction of acceptable maximum error, the site error once intermediary layer exceedes maximum limit, the most not Laser beam alignment engagement pad may be used, and cause the electric connection mistake between intermediary layer and coreless substrate.Therefore, according in The size of the engagement pad of interlayer, for those skilled in the art can via trial and error pricing to confirm between intermediary layer and keeper between The maximum acceptable scope of gap, thus avoid the electric connection mistake between intermediary layer and coreless substrate.Thus, " keeper leans on The peripheral edge of nearly intermediary layer " term refer to that the gap between the peripheral edge of intermediary layer and keeper is too narrow to be enough to prevent The site error of interlayer exceedes acceptable maximum error and limits.

" arrange " language to comprise and contacting and noncontact between single or multiple support component.Such as, intermediary layer is arranged at On dielectric layer, contact dielectric layer no matter this intermediary layer is actual or is separated by with an adhesive agent with dielectric layer.

" it is electrically connected with " word to mean directly or indirectly to be electrically connected with.Such as, the first wire provide interior connection gasket and The electric connection of the second engagement pad, no matter whether its first wire adjoins interior connection gasket or is electrically connected to via the second wire Interior connection gasket.

" top " word means to upwardly extend, and comprises adjacent and non-adjacent element and overlapping and non overlapping elements.Example As, when the first connection gasket of intermediary layer faces upward direction, keeper the most just extends, adjacent dielectric layer from dielectric layer Projection and go out.

" lower section " word means to downwardly extend, and comprises adjacent and non-adjacent element and overlapping and non overlapping elements.Example As, when the second connection gasket of intermediary layer faces upward direction, coreless substrate extends below, and adjacent adhesive agent also sticks together certainly Agent goes out to projection downward.Similarly, even if build-up circuitry does not adjoin enhancement Layer or intermediary layer, it is the most extensible in adding Below strong layer and intermediary layer.

" the first vertical direction " and " the second vertical direction " is not dependent on the orientation of assembly, all people being familiar with this skill Scholar can will readily appreciate that the direction of its actual indication.Such as, the first engagement pad of intermediary layer faces the first vertical direction, and intermediary Second engagement pad of layer faces the second vertical direction, and whether this is inverted unrelated with assembly.Similarly, keeper along side to flat Face " laterally " alignment intermediary layer, it is unrelated whether this is inverted with wiring board, rotates or tilts.Therefore, this first and second Vertical Square Contrary to each other and be perpendicular to side surface direction, and the element of lateral alignment is being perpendicular to the lateral flat of first and second vertical direction Face is intersected.Furthermore, when the second engagement pad of intermediary layer faces upward direction, the first vertical direction is in downward direction, and second hangs down Nogata is to for upward direction;When the second engagement pad of intermediary layer faces in downward direction, the first vertical direction is upward direction, the Two vertical direction are in downward direction.

The semiconductor subassembly of the present invention has multiple advantages.The reliability of semiconductor subassembly is high, price is plain and is extremely suitable for Volume production.Enhancement Layer provides mechanical support, dimensional stability and controls overall planarization, and coreless substrate is (such as intermediary Layer) thermal expansion, even if the thermal coefficient of expansion between intermediary layer from coreless substrate (CTE) is different, in the case of thermal cycle, intermediary Layer still can consolidate and be connected to coreless substrate.Being directly to be electrically connected with between intermediary layer and coreless substrate, it has without solder It is beneficial to high I/O value and high-performance.Particularly keeper can define the position that intermediary layer is arranged accurately, and avoids by intermediary layer The intermediary layer that caused of lateral displacement and coreless substrate between electric connection mistake, thus improve the qualification rate of production.

The manufacture method of this case has high applicability, and the electricity of the various maturation of R. concomitans in the way of unique, progressive Property connect and mechanicalness interconnection technique.Can implement additionally, the manufacture method of this case is not required to expensive tool.Therefore, compared to biography System encapsulation technology, this manufacture method can be substantially improved yield, qualification rate, usefulness and cost benefit.

Embodiment described herein is used for illustrating, and wherein those embodiments may simplify or omit the art Known to element or step, in order to avoid the feature of the fuzzy present invention.Similarly, for making accompanying drawing clear, accompanying drawing is likely to omit and repeats Or non-essential element and component symbol.

Those skilled in the art should think easily for embodiment as herein described and various change and the side of amendment Formula.Such as, aforesaid material, size, shape, size, the content of step are all only example with the order of step.Art technology Personnel can be changed under conditions of without departing substantially from spirit and scope of the present invention as defined in appended claims, adjust with Equivalents.

Although the present invention is in being preferable to carry out in aspect explanation, but it will be appreciated that without departing substantially from right of the present invention Under conditions of the spirit and scope required, possible amendment and change can be carried out for the present invention.

Claims (4)

1. a semiconductor subassembly, it is characterised in that including:
One intermediary layer, it includes that multiple first engagement pad and a joint refer on a first surface, and multiple second contact Being padded on a second surface, this first surface faces one first vertical direction, and this second surface faces and this first Vertical Square To one second contrary vertical direction, wherein, at least one this first engagement pad via a conductive through holes of this intermediary layer with electrically It is connected to this second engagement pad of a correspondence;
Semiconductor element, its upside-down mounting is arranged on this first surface of this intermediary layer, and is connected to those the first engagement pads;
One enhancement Layer, it includes a through hole, and this intermediary layer extends in this through hole;
One adhesive agent, it contacts this intermediary layer and a coreless substrate, and between this intermediary layer and this coreless substrate;And
This coreless substrate, it covers this adhesive agent, this intermediary layer and this enhancement Layer, and this centreless in this second vertical direction Substrate includes a connection gasket, and this joint that this connection gasket is electrically connected to this intermediary layer via a routing refers to, and also includes one Conduction micropore, this conduction micropore is electrically connected to this second engagement pad of this intermediary layer;
Wherein, this coreless substrate also includes positioning piece, and this keeper is aligned in this through hole of this enhancement Layer, and as this intermediary The configuration guiding element of layer, and near peripheral edge and this connection gasket of this intermediary layer, and in this intermediary layer peripheral edge with should Extend laterally between connection gasket.
Semiconductor subassembly the most according to claim 1, wherein, the electric connection between this intermediary layer and this coreless substrate is not Containing solder.
Semiconductor subassembly the most according to claim 1, wherein this connection is padded on this first vertical direction from this coreless substrate Appear, and extend laterally between the sidewall of the peripheral edge of this intermediary layer and this through hole of this enhancement Layer in lateral.
Semiconductor subassembly the most according to claim 1, wherein this coreless substrate also includes a configuration guiding element, this configuration guiding element Near the peripheral edge of this enhancement Layer, and the peripheral edge of this enhancement Layer of lateral alignment, and outside the peripheral edge of this enhancement Layer Extend laterally.
CN201310350222.1A 2012-08-14 2013-08-12 There is between intermediary layer and coreless substrate the semiconductor subassembly of dual interface channel CN103594444B (en)

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US13/917,776 US20140048951A1 (en) 2012-08-14 2013-06-14 Semiconductor assembly with dual connecting channels between interposer and coreless substrate
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US20150257316A1 (en) * 2014-03-07 2015-09-10 Bridge Semiconductor Corporation Method of making thermally enhanced wiring board having isolator incorporated therein
US20160174365A1 (en) * 2014-12-15 2016-06-16 Bridge Semiconductor Corporation Wiring board with dual wiring structures integrated together and method of making the same
CN109087908A (en) * 2015-12-31 2018-12-25 华为技术有限公司 Encapsulating structure, electronic equipment and packaging method
TWI647805B (en) * 2016-09-09 2019-01-11 矽品精密工業股份有限公司 Electronic package and method
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US7098528B2 (en) * 2003-12-22 2006-08-29 Lsi Logic Corporation Embedded redistribution interposer for footprint compatible chip package conversion
US7042077B2 (en) * 2004-04-15 2006-05-09 Intel Corporation Integrated circuit package with low modulus layer and capacitor/interposer
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