CN110875264A - 电子芯片封装 - Google Patents

电子芯片封装 Download PDF

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CN110875264A
CN110875264A CN201910823708.XA CN201910823708A CN110875264A CN 110875264 A CN110875264 A CN 110875264A CN 201910823708 A CN201910823708 A CN 201910823708A CN 110875264 A CN110875264 A CN 110875264A
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conductive layer
support
semiconductor chip
semiconductor
package
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O·奥里
R·贾勒特
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STMicroelectronics Tours SAS
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STMicroelectronics Tours SAS
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Abstract

本发明涉及一种器件，包括支持件、覆盖支持件的导电层、位于导电层上的半导体衬底和绝缘壳体。

Description

电子芯片封装
技术领域
本公开涉及电子器件，并且更具体地，涉及包括容纳在封装中的电子芯片的电子器件。
背景技术
电子芯片通常由半导体衬底来限定，半导体衬底的内部和顶表面处定位有一个或多个互连部件(诸如晶体管)，用于形成芯片的电路。在特定应用(诸如静电放电保护)中，芯片包括雪崩二极管。
通常地，芯片被容纳在封装中。封装包括连接端子，通常用于焊接或锡焊至诸如PCB(“印刷电路板”)的印刷电路。对于包括紧凑地容纳在封装中的电子芯片的器件，通常使用CSP型封装(“芯片级封装”)，也就是说，该封装占据较小的表面积，通常小于芯片衬底的1.2倍。
发明内容
一个或多个实施例的目的在于一种器件，其包括支持件、覆盖支持件的导电层、位于导电层上的半导体衬底或芯片以及绝缘壳体。
根据一个实施例，该器件包括位于衬底内和衬底顶部上的电子部件。
根据一个实施例，导电层是金属。
根据一个实施例，衬底包括限定雪崩二极管的电极的掺杂区域。
根据一个实施例，壳体限定CSP型封装。
一个实施例提供了一种形成上述限定的器件的方法。
根据一个实施例，该方法包括同时形成多个上述限定的器件的步骤。
根据一个实施例，器件的衬底是同一半导体晶圆的部分。
根据一个实施例，该方法包括在半导体晶圆的后表面上形成导电层的步骤。
根据一个实施例，该方法包括在导电层的后表面侧上布置支持板的步骤。
根据一个实施例，该方法包括形成界定衬底的沟槽的步骤，沟槽优选达到位于支持板中的水平。
附图说明
将在以下结合附图的具体实施例的非限制性描述中详细讨论上述和其他特点和优点。
图1以示图1A和示图1B的截面图和顶视图示意性示出了在封装中包括电子芯片的器件的实施例；
图2是示意性示出了图1的器件在操作中的示例的截面图；
图3示出了同时形成图1的多个器件的方法的步骤3A至3D；以及
图4示出了同时形成图1的多个器件的方法的步骤4A至4C。
具体实施方式
在不同的附图中，相同的元素用相同的参考标号表示。具体地，不同实施例共同的结构和/或功能元件可以用相同的参考标号指定，并且可以具有相同的结构、尺寸和材料特性。
为了清楚，仅示出了有助于理解所述实施例的那些步骤和元素并进行详细说明。特别地，未示出电子芯片电路，所述实施例与当前芯片电路兼容。
贯穿本公开，术语“连接”用于指定电路元件之间的直接电连接，而术语“耦合”用于指定电路元件之间的电连接，其可以是直接的或者可以经由一个或多个中间元件(诸如电阻器、电容器、晶体管或缓冲器)。除非另有说明，否则当使用术语“耦合”时，可通过直接连接来实施连接。
在以下描述中，除了图1B，当提及限定绝对位置的术语(诸如“上”、“下”、“左”、“右”等)或相对位置的术语(诸如“之上”、“之下”、“上部”、“下部”等)或限定方向的术语(诸如术语“水平”、“垂直”等)时，所指的是附图的定向。
本文使用术语“约”、“基本”和“…的数量级”来指定所指值的正负10％、优选正负5％的公差。
图1以示图1A和示图1B示意性示出了在封装中包括电子芯片的器件的实施例。示图1A和示图1B分别是沿着相应的截面A-A和B-B截取的侧视图和顶视图。
器件100包括支持件104、导电层106和衬底108的叠层102。层106位于支持件104与衬底108之间。
支持件104优选为半导体，优选由硅制成，但可以由任何导电或电绝缘材料制成，优选为可通过常用手段减薄的材料(诸如玻璃、蓝宝石、氮化镓或碳化硅)。层106优选为金属，例如由铜或铝制成。层106覆盖衬底108的后表面，优选整体覆盖。衬底108是电子芯片或半导体芯片，其具有其中集成有一个或多个电子电路部件的有源(active)表面。衬底108由半导体材料制成，优选由硅制成。
优选地，支持件104、金属层106和衬底108被堆叠以使它们的边缘重合。支持件104、金属层106和衬底108的边缘限定叠层的侧面109。叠层102优选具有平行六面体的形状。然后，壳体覆盖平行六面体的六个表面。
器件100还包括覆盖叠层102的绝缘壳体110，即，壳体110覆盖叠层102的前表面、后表面和侧面109，并且与侧面109粘合接触。优选地，壳体110整体覆盖后表面和侧面109。优选地，壳体110通过连接端子112在前表面侧上相交。优选地，除了连接端子112，壳体110整体覆盖叠层102的前表面。由此，壳体110限定电子芯片封装。封装优选为CSP类型。
支持件104的存在使得能够提供薄衬底108，例如具有约150微米(μm)或小于150μm、优选或约100μm或小于100μm的厚度，同时易于利用当前手段进行操作。
如以下所示示例的情况所描述的，由于薄衬底和薄衬底的后表面上的导电层的关联性，器件的操作相对于不具有薄衬底和后表面上的金属层的器件相比得到了改进。
在所示示例中，衬底108例如为P型掺杂。彼此分离的N型掺杂区114和P型掺杂区116位于衬底108的前表面上。区域114和116的掺杂等级(N+、P+)优选大于衬底108的掺杂等级。衬底108和区域114可一起形成雪崩二极管的PN结。
优选地，叠层102包括覆盖衬底108的绝缘层118。在所示实施例中，层118穿过导电区域120(例如，金属)，从区域114和116延伸到端子112。
图2是示出图1所示的器件100的示例的操作的截面图。
例如，连接端子112耦合至施加参考电位(例如，地GND)的端子和将被保护免受静电放电的端子IO。在静电放电引起端子IO的电位增加的情况下，掺杂区域114和衬底108之间的PN结开始雪崩。电流从区域114流向区域116，这将放电排至地。
由于衬底108较薄且覆盖金属层106的事实，电流在区域114和112中的每一个与金属层106之间垂直流动(箭头202)。通过导电层106将电流横向地从区域114下方的位置传导至区域112下方的位置(箭头204)。得到从区域114出来的电流的均匀分布。与衬底不薄且在其后表面上不具有金属层的情况相比，这种分布能够将具有较高强度的电流排至地。确实地，对于非薄衬底或无金属层的情况，电流将通过衬底在区域114和116之间横向流动。电流从区域114流出，并且集中在区域114靠近区域116的一侧。这种浓度将限制电流的最大强度。
图1和图2的实施例与大多数电子芯片电路兼容。层112可包括位于衬底106内部及顶部的电路部件(诸如晶体管)之间的互连轨道。电路连接至与端子120接触的导电区域120。
图3和图4是示出同时形成图1类型的多个器件的方法实施的步骤3A至3D和4A至4C的部分简化截面图。
在图3A的步骤中，提供半导体晶圆308。晶圆308将划分为各个衬底或芯片。每个未来衬底108对应于晶圆的一部分。未来衬底(future substrate)108优选是分离的，例如通过带302分离。作为示例，未来衬底108以阵列进行布置。
电子芯片电路形成在未来衬底108的内部和顶部。晶圆308的前表面具有导电区域120，连接至形成于其上的电路。区域120优选可从前表面接近。作为示例，区域120位于覆盖前表面的绝缘层(未示出)中。绝缘层包括可能的互连轨道。
为使晶圆308具有未来衬底108的厚度，晶圆308例如被减薄，优选在形成电路之后。
然后，用导电层106(优选为金属)覆盖晶圆308的后表面。层106优选具有0.5μm到0.5μm的范围内的厚度。优选地，基于层106的材料的导电性选择该厚度。
在步骤3B中，在106层的后表面下方布置支持板304。未来支持件104是板304的一部分。板304的厚度优选大于未来支持件104的厚度。例如，板304通过粘合剂粘合至金属层106。优选地，粘合剂分布在板304的整个表面。
在步骤3C中，形成覆盖导电区域120的金属焊盘312。然后形成界定衬底108的沟槽330(诸如通过蚀刻)。沟槽330从衬底108的前表面一直延伸到支持板304中的水平。沟槽330的深度优选大于未来叠层102的高度。板304的部分332留在沟槽下方。
在步骤3D中，在步骤3C中获得的整个结构覆盖有填充沟槽330的绝缘体310A。然后，例如通过表面处理(诸如抛光)，去除位于穿过金属焊盘312的水平上方的所有元件。这使得连接端子112对应于焊盘312的剩余部分。除了端子112的位置，绝缘体310A覆盖衬底108的上表面。端子112与绝缘体310A的上表面齐平。
在步骤4A中，诸如通过抛光，对板的后表面进行表面处理，至少直到从板304完全去除在抛光之前位于沟槽330下方的区域332。然后，使绝缘体310A与抛光后获得的结构下表面齐平。由此得到通过将绝缘体粘合至它们的侧面彼此机械连接的叠层102。
在步骤4B中，形成覆盖在步骤4A中获得的结构的后表面的绝缘体310B。绝缘体310B优选与绝缘体310A具有相同材料(例如，树脂)。
在步骤4C中，步骤4B获得的结构被切割成各个器件100。为此，例如通过切割，跨越结构的整个高度从区域350去除绝缘体310A。区域350位于带302中并且具有的宽度小于沟槽330的宽度，以留下绝缘体310A的覆盖叠层102侧面的部分。每个壳体110都包括覆盖对应叠层102的前表面和侧面的绝缘体部分310A以及覆盖该叠层的后表面的绝缘体部分310B。
已经描述了各种实施例和变型。这些各种实施例和变型可以组合，并且本领域技术人员将意识到其他变型。最后，所述实施例和变型的实际实施在本领域技术人员基于上文给出的功能指示的能力范围内。
上述各个实施例可以进行组合来提供进一步的实施例。可根据上面的详细描述对实施例进行这些和其他更改。一般地，在下列权利要求中，所用术语不应解释为将权利要求限于说明书和权利要求书公开的具体实施例，而是应解释为包括所有可能的实施例以及这些权利要求所要求的等效物的全部范围。因此，不通过本公开限制权利要求。

Claims (20)

1.一种器件，包括：
支持件；
导电层，覆盖所述支持件；
半导体芯片，位于所述导电层上，其中所述半导体芯片具有约150微米以下的厚度；以及
绝缘壳体。
2.根据权利要求1所述的器件，其中所述半导体芯片包括集成电子部件的有源表面。
3.根据权利要求1所述的器件，其中所述导电层是金属。
4.根据权利要求1所述的器件，其中所述半导体芯片包括限定雪崩二极管的电极的掺杂区域。
5.根据权利要求1所述的器件，其中所述绝缘壳体限定CSP型封装。
6.根据权利要求1所述的器件，其中所述半导体芯片的厚度小于100微米。
7.根据权利要求1所述的器件，其中所述支持件、所述半导体芯片和所述导电层在二维中具有彼此相同的尺寸和形状。
8.根据权利要求1所述的器件，其中所述支持件、所述半导体芯片和所述导电层形成平行六面体形状的叠层。
9.一种方法，包括：
在半导体晶圆的后表面上形成导电层；
将支持件耦合至所述导电层；
在所述半导体晶圆中形成多个沟槽，使所述半导体晶圆的多个芯片彼此分离；以及
在所述多个芯片、所述导电层和所述支持件周围形成绝缘壳体，其中所述支持件的表面保持从所述绝缘壳体暴露。
10.根据权利要求9所述的方法，包括：在保持从所述绝缘壳体暴露的所述表面处去除所述支持件的一部分。
11.根据权利要求9所述的方法，在形成所述导电层之前，所述方法包括在所述后表面处减薄所述半导体晶圆。
12.根据权利要求11所述的方法，其中所述半导体晶圆被减薄以具有约150微米以下的厚度。
13.根据权利要求9所述的方法，其中将所述支持件耦合至所述导电层包括：使用粘合材料来将所述支持件耦合至所述导电层。
14.根据权利要求9所述的方法，其中形成所述多个沟槽包括：蚀刻所述半导体晶圆、所述导电层和所述支持件。
15.一种半导体封装，包括：
支持件；
半导体芯片，位于所述支持件上；
导电层，位于所述半导体芯片和所述支持件之间，所述支持件、所述半导体芯片和所述导电层具有彼此共面的侧表面；以及
绝缘材料，位于共面的所述侧表面上。
16.根据权利要求15所述的半导体封装，其中所述半导体芯片具有约150微米以下的厚度。
17.根据权利要求15所述的半导体封装，其中所述半导体芯片包括限定雪崩二极管的电极的掺杂区域。
18.根据权利要求15所述的半导体封装，其中所述导电层是金属材料。
19.根据权利要求15所述的半导体封装，其中所述绝缘材料覆盖所述支持件的底表面。
20.根据权利要求19所述的半导体封装，其中除了所述半导体芯片的多个端子，所述绝缘材料覆盖所述半导体芯片的有源表面。
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