CN110870391A - 用于电路装置的公差补偿元件 - Google Patents

用于电路装置的公差补偿元件 Download PDF

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CN110870391A
CN110870391A CN201880045267.9A CN201880045267A CN110870391A CN 110870391 A CN110870391 A CN 110870391A CN 201880045267 A CN201880045267 A CN 201880045267A CN 110870391 A CN110870391 A CN 110870391A
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compensation element
tolerance compensation
gap
pcb
circuit board
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R.克诺夫
B.米勒
J.斯特罗吉斯
K.威尔克
R.布兰克
M.弗兰克
P.弗鲁豪夫
S.内雷特
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Siemens AG
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
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Abstract

本发明涉及一种用于电路装置的公差补偿元件，所述电路装置具有DCB(Direct Copper Bonded)衬底(1)和PCB(Printed Circuit Board)印刷电路板(2)，并且本发明还涉及一种具有所述公差补偿元件的电路装置。本发明的特征在于，公差补偿元件在DCB衬底(1)与PCB印刷电路板(2)之间、在用于使DCB衬底(1)上的构件(5)触点接通的间隙A(3)中借助增材制造法目标性地调节并且以封闭间隙的方式构造。

Description

用于电路装置的公差补偿元件
本发明涉及一种用于电路装置的公差补偿元件，所述电路装置具有DCB(DirectCopper Bonded)衬底和PCB(Printed Circuit Board)印刷电路板，并且本发明还涉及一种具有所述公差补偿元件的电路装置。
为了使PCB(印刷电路板)空腔中的功率电子设备中的半导体构件(裸芯片)在两侧触点接通，空腔的深度必须相当准确地匹配于半导体构件的结构高度。由于在PCB制造时、尤其在铣削空腔时以及在所使用的玻璃纤维树脂复合材料的选定材料特性下的制造公差，不能总是可靠地实现所需的窄公差。
附加地存在如下必要性，即处理各种不同的可来自于不同来源的半导体构件。在此，结构高度并非总是能够被影响，从而由此产生的技术问题是必须补偿非常不同的结构高度、即差>100μm，以便确保安全的触点接通。由此产生的较大的闭合尺寸无法可靠地通过烧结连接或常规的软焊连接的补偿能力来封闭。对于尺寸较小的间隙，相应尺寸的焊料施加将导致焊料在侧面渗出，由此使高压绝缘性能明显变差。相应地，在明显更大尺寸的间隙中会缺少焊料，从而会损害导热性并且可能还会损害导电性。
现在，每个空腔的结构高度(总高度)必须匹配于三维的芯片结构。在此，PCB购置是有问题的，因为变体多样性升高。迄今为止不可能通过缩放(Skalierung)实现成本降低。此外，由于通过空腔的铣削导致的工艺公差，在制造中技术上没有缺陷的最终产品的百分比下降。
来自迄今为止的现有技术的另外的解决方案是对接合配对件进行100％的单独测量，并且随后进行单独定尺寸的焊料施加。该方法结合了两个附加的过程，即测量和单独的焊料施加，这带来了牵涉成本和运行时间的所有负面影响。
因此，本发明所要解决的技术问题在于，提供用于电路装置(Schaltbild,Schaltbilder)、尤其电子电路装置的公差补偿元件以及电路装置(或称为电路配置或电路图案)，所述公差补偿元件以及电路装置可以以简单的方式单独制造。
根据本发明，该技术问题通过具有权利要求1的特征的尤其用于电子电路装置的公差补偿元件以及通过具有权利要求10的特征的电路装置解决。可以单独或相互组合地使用的有利的设计方案和扩展方案是从属权利要求的主题。
根据本发明，该技术问题通过用于电路装置、尤其电子电路装置的公差补偿元件解决，所述电路装置具有DCB(Direct Copper Bonded)衬底和PCB(Printed CircuitBoard)印刷电路板。在此，本发明的特征在于，公差补偿元件在DCB衬底与PCB印刷电路板之间、在用于使DCB衬底上的构件触点接通的间隙A中借助增材制造法目标性地调节并且以封闭间隙的方式构造。
为了在上侧和下侧都在窄的公差范围内确保用于使电气构件、尤其半导体元件可靠地触点接通的间隙尺寸，PCB印刷电路板与DCB衬底之间的间隙A在PCB印刷电路板的制造过程中首先尺寸不足地被制造，从而在DCB衬底(Direct Copper Bond)与PCB(PrintedCircuit Board)印刷电路板之间存在限定的距离。
本发明的核心是，在间隙A中的该距离借助公差补偿元件、尤其AM层，通过增材制造法以限定的方式被调节和封闭。在此规定，公差补偿元件、即AM层优选以粉末形式要么施加到PCB印刷电路板上，要么施加到DCB衬底上，并且尤其通过激光射束逐点地被融化。有利的是，公差补偿元件由对于常规焊料可润湿的材料或由合金制成，从而所述公差补偿元件可以在随后的焊接过程中材料接合地连接。DCB衬底与PCB印刷电路板之间的距离可以直接在实施的制造过程中确定，并且是通过闭合的调节回路、为了由DCB衬底和PCB印刷电路板构成的相应的配对而针对工件地进行调节。
根据本发明的设计的扩展可以是，DCB衬底具有铜-铝-铜的排布结构(电介质)。
根据本发明的设计的特殊的设计方案可以是，DCB衬底具有铜-陶瓷-铜的排布结构。
根据本发明的设计的有利的设计方案可以是，公差补偿元件在间隙A中要么施加到PCB印刷电路板上，要么施加到DCB衬底上，并且逐点地被融化(或称为熔化)。
根据本发明的设计的扩展可以是，公差补偿元件能够借助激光射束在间隙A中融化。
根据本发明的设计的特殊的设计方案可以是，要电触点接通的构件是半导体构件。
根据本发明的设计的有利的设计方案可以是，PCB印刷电路板与DCB衬底之间的间隙A在PCB印刷电路板的制造过程中尺寸不足地被制造，从而在DCB衬底与PCB印刷电路板之间构造出目标性的距离。
根据本发明的设计的扩展可以是，不仅对于半导体构件的上侧的间隙B、而且也在下侧的间隙C中，在窄的公差范围内构造用于使半导体元件电触点接通的间隙尺寸。
根据本发明的设计的特殊的设计方案可以是，公差补偿元件由对于焊料来说可润湿的材料或由合金构造。
根据本发明的设计的有利的设计方案可以是，在间隙A中的距离能够直接在制造过程中确定，并且是通过闭合的调节回路、为了由DCB衬底和PCB印刷电路板构成的相应的配对而针对材料地进行调节。
该技术问题此外通过根据本发明的具有带有上述特性的公差补偿元件的电路装置解决。
根据本发明的公差补偿元件布置在DCB(Direct Copper Bonded)衬底与PCB(Printed Circuit Board)印刷电路板之间。PCB印刷电路板在DCB衬底上构造出空腔，构件、尤其半导体构件可以定位到空腔中。对于电子构件是半导体构件的情况，DCB衬底以铜-陶瓷-铜的组成三层地构造。也可想到其他构件，所述其他构件接受组成为铜-铝-铜的电介质作为DCB衬底。
半导体构件具有上侧，该上侧形成相对于PCB印刷电路板的间隙B。此外，半导体构件具有下侧，该下侧定位在相对于DCB衬底的间隙C的上方。
为了在上侧(间隙B)和下侧(间隙C)都在窄的公差范围内确保用于使电气构件、尤其半导体元件可靠地触点接通的间隙尺寸，PCB印刷电路板与DCB衬底之间的间隙A在PCB印刷电路板的制造过程中首先尺寸不足地被制造，从而在DCB衬底(Direct Copper Bond)与PCB(Printed Circuit Board)印刷电路板之间存在限定的距离。规定了，在间隙A中的该距离借助公差补偿元件、尤其AM层，通过增材制造法以限定的方式被调节和封闭。在此还规定，公差补偿元件、即AM层优选以粉末形式要么施加到PCB印刷电路板上，要么施加到DCB衬底上，并且尤其通过激光射束逐点地被融化。
随后根据实施例和附图阐述本发明的另外的实施例和优点。
在此示出：
图1以示意图示出了具有根据本发明的公差补偿元件的电路装置。
图1示出了具有根据本发明的公差补偿元件的电路装置，所述公差补偿元件在DCB(Direct Copper Bond)衬底1与PCB(Printed Circuit Board)印刷电路板2之间布置在间隙A 3中。PCB印刷电路板2在DCB衬底1上方构造出空腔4，电子构件5、尤其半导体构件6可以定位到所述空腔中。对于电子构件5是半导体构件6的情况，DCB衬底1以三层的方式构造，优选以铜-陶瓷-铜的组成构造。也可以设想其他构件5，所述其他构件接受组成为铜-铝-铜的电介质作为DCB衬底1。
半导体构件6具有上侧7，该上侧形成相对于PCB印刷电路板2的间隙B 8。此外，半导体构件6具有下侧9，该下侧定位在相对于DCB衬底1的间隙C10的上方。
为了在上侧(间隙B，8)和下侧(间隙C，10)都在窄的公差范围内确保用于可靠地触点接通电构件5、尤其半导体元件6的间隙尺寸，PCB印刷电路板2与DCB衬底1之间的间隙A 3在PCB印刷电路板2的制造过程中首先尺寸不足地被制造，从而在DCB衬底1(Direct CopperBond)与PCB(Printed Circuit Board)印刷电路板2之间存在限定的距离。规定了，在间隙A3中的该距离借助公差补偿元件、尤其AM层，通过增材制造法以限定的方式被调节和封闭。在此还规定，公差补偿元件、即AM层优选以粉末形式要么施加到PCB印刷电路板2上，要么施加到DCB衬底1上，并且尤其通过激光射束逐点地被融化。
根据本发明的用于电子电路装置的公差补偿元件的特征在于，可以以简单的、单独的方式在增材制造工艺中为了DCB衬底与PCB印刷电路板之间的间隙封闭而设计和制造所述公差补偿元件。
附图标记清单
1DCB(Direct Copper Bonded)衬底
2PCB(Printed Circuit Board)印刷电路板
3间隙A
4空腔
5电子构件
6半导体构件
7上侧
8间隙B
9下侧
10间隙C

Claims (11)

1.一种用于电路装置的公差补偿元件，所述电路装置具有DCB(Direct CopperBonded)衬底(1)和PCB(Printed Circuit Board)印刷电路板(2)，其特征在于，公差补偿元件在DCB衬底(1)与PCB印刷电路板(2)之间、在用于使DCB衬底(1)上的构件(5)触点接通的间隙A(3)中借助增材制造法目标性地调节并且以封闭间隙的方式构造。
2.根据权利要求1所述的公差补偿元件，其特征在于，所述DCB衬底(1)具有铜-铝-铜的排布结构(电介质)。
3.根据权利要求1所述的公差补偿元件，其特征在于，所述DCB衬底(1)具有铜-陶瓷-铜的排布结构。
4.根据权利要求1至3中任一项所述的公差补偿元件，其特征在于，所述公差补偿元件在间隙A(3)中要么施加到PCB印刷电路板(2)上，要么施加到DCB衬底(1)上，并且逐点地被融化。
5.根据权利要求4所述的公差补偿元件，其特征在于，所述公差补偿元件能借助激光射束在间隙A(3)中被融化。
6.根据权利要求3至5中任一项所述的公差补偿元件，其特征在于，要电触点接通的构件(5)是半导体构件(6)。
7.根据权利要求6所述的公差补偿元件，其特征在于，PCB印刷电路板(2)与DCB衬底(1)之间的间隙A(3)在PCB印刷电路板(2)的制造过程中尺寸不足地被制造，从而在DCB衬底(1)与PCB印刷电路板(2)之间构造出目标性的距离。
8.根据权利要求6或7所述的公差补偿元件，其特征在于，不仅对于半导体构件(6)的上侧(7)的间隙B(8)、而且也在下侧(9)的间隙C(10)中，都在窄的公差范围内构造用于使半导体元件(6)电触点接通的间隙尺寸。
9.根据权利要求6至8中任一项所述的公差补偿元件，其特征在于，所述公差补偿元件由对于焊料来说可润湿的材料或由合金构造。
10.根据权利要求1至9中任一项所述的公差补偿元件，其特征在于，间隙A中的距离能够直接在制造过程中确定，并且是通过闭合的调节回路、为了由DCB衬底(1)和PCB印刷电路板(2)构成的相应的配对而针对工件地进行调节。
11.一种电路装置，具有根据权利要求1至10中任一项所述的公差补偿元件。
CN201880045267.9A 2017-07-04 2018-06-07 用于电路装置的公差补偿元件 Pending CN110870391A (zh)

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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834839A (en) * 1997-05-22 1998-11-10 Lsi Logic Corporation Preserving clearance between encapsulant and PCB for cavity-down single-tier package assembly
US20020189091A1 (en) * 2001-06-19 2002-12-19 Advanced Semiconductor Engineering, Inc. Method of making printed circuit board
US20080263860A1 (en) * 2007-04-30 2008-10-30 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board having embedded component
CN101794742A (zh) * 2009-01-23 2010-08-04 赛米控电子股份有限公司 按照压力接触方式实施的功率半导体模块
US20140300001A1 (en) * 2013-04-09 2014-10-09 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and manufacturing method thereof, and semiconductor package including the printed circuit board
US20150223320A1 (en) * 2014-01-31 2015-08-06 Hs Elektronik Systeme Gmbh Pcb embedded power module
CN106133892A (zh) * 2014-04-04 2016-11-16 西门子公司 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖
CN106133895A (zh) * 2014-04-04 2016-11-16 西门子公司 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100825793B1 (ko) * 2006-11-10 2008-04-29 삼성전자주식회사 배선을 구비하는 배선 필름, 상기 배선 필름을 구비하는반도체 패키지 및 상기 반도체 패키지의 제조방법
US8927345B2 (en) * 2012-07-09 2015-01-06 Freescale Semiconductor, Inc. Device package with rigid interconnect structure connecting die and substrate and method thereof
DE102012219145A1 (de) * 2012-10-19 2014-05-08 Robert Bosch Gmbh Elektronikanordnung mit reduzierter Toleranzkette
US9053972B1 (en) * 2013-11-21 2015-06-09 Freescale Semiconductor, Inc. Pillar bump formed using spot-laser
US9508667B2 (en) * 2014-12-23 2016-11-29 Intel Corporation Formation of solder and copper interconnect structures and associated techniques and configurations
EP3246941A1 (de) * 2016-05-18 2017-11-22 Siemens Aktiengesellschaft Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe
DE102017212739A1 (de) * 2017-07-25 2019-01-31 Siemens Aktiengesellschaft Halbleiterbauteil sowie Verfahren zu dessen Herstellung

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834839A (en) * 1997-05-22 1998-11-10 Lsi Logic Corporation Preserving clearance between encapsulant and PCB for cavity-down single-tier package assembly
US20020189091A1 (en) * 2001-06-19 2002-12-19 Advanced Semiconductor Engineering, Inc. Method of making printed circuit board
US20080263860A1 (en) * 2007-04-30 2008-10-30 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing printed circuit board having embedded component
CN101794742A (zh) * 2009-01-23 2010-08-04 赛米控电子股份有限公司 按照压力接触方式实施的功率半导体模块
US20140300001A1 (en) * 2013-04-09 2014-10-09 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and manufacturing method thereof, and semiconductor package including the printed circuit board
US20150223320A1 (en) * 2014-01-31 2015-08-06 Hs Elektronik Systeme Gmbh Pcb embedded power module
CN106133892A (zh) * 2014-04-04 2016-11-16 西门子公司 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖
CN106133895A (zh) * 2014-04-04 2016-11-16 西门子公司 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖

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