CN110867430A - 异质整合组装结构及其制造方法 - Google Patents

异质整合组装结构及其制造方法 Download PDF

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CN110867430A
CN110867430A CN201910802867.1A CN201910802867A CN110867430A CN 110867430 A CN110867430 A CN 110867430A CN 201910802867 A CN201910802867 A CN 201910802867A CN 110867430 A CN110867430 A CN 110867430A
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layer
die
substrate
hetero
wafer
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CN110867430B (zh
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林育民
林昂樱
吴昇财
张道智
骆韦仲
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Industrial Technology Research Institute ITRI
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Abstract

本发明公开一种异质整合组装结构及其制造方法，其中该异质整合组装结构包括基底、管芯、钝化层、第一重布线层、第二重布线层以及连接部。管芯安装于所述基底上。管芯具有有源面与无源面。有源面具有接垫。钝化层覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面。第一重布线层位于钝化层上，电连接接垫。第二重布线层位于基底上，与管芯相邻。连接部连接第一重布线层与第二重布线层。

Description

异质整合组装结构及其制造方法
技术领域
本发明涉及一种异质整合组装结构及其制造方法。
背景技术
随着电子装置的轻薄化，目前的趋势正致力于将异质的半导体的组件直接连接而减少中介基底的使用，一方面可减少半导体封装的尺寸，同时可缩短电性通路，提升半导体封装中的运算速度。传统的异质组装方式为在高温下进行焊接，但高温会影响芯片的性能。因应更先进的需求并避免传统焊接连接的高温影响芯片性能，需要持续寻求新的组装方法。
发明内容
本发明提出一种异质整合组装结构，包括基底、管芯、钝化层、第一重布线层、第二重布线层以及连接部。管芯安装于所述基底上。管芯具有有源面与无源面。有源面具有接垫。钝化层覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面。第一重布线层位于钝化层上，电连接接垫。第二重布线层位于基底上，与管芯相邻。连接部连接第一重布线层与第二重布线层。
依照本发明实施例所述，所述连接部的宽度大于所述第一重布线层的宽度，且大于所述第二重布线层的宽度。
依照本发明实施例所述，异质整合组装结构还包括粘着层，位于所述管芯与所述基底之间。
依照本发明实施例所述，所述管芯的所述无源面与所述粘着层接触。
依照本发明实施例所述，所述管芯的侧壁与所述粘着层接触。
依照本发明实施例所述，所述管芯的所述有源面比所述无源面接近所述粘着层。
依照本发明实施例所述，所述粘着层具有亲水性。
依照本发明实施例所述，所述基底具有凹槽，所述管芯安装于所述凹槽中。
依照本发明实施例所述，所述管芯的所述有源面的面积大于或等于所述无源面的面积。
依照本发明实施例所述，所述管芯的所述有源面的面积小于所述无源面的面积。
依照本发明实施例所述，所述管芯的具有垂直侧壁、倾斜侧壁、阶梯侧壁、弧形侧壁或其组合。
本发明还提出一种异质整合组装结构的制造方法，包括提供晶片，所述晶片包括多个管芯，其中每一所述管芯具有有源面与无源面，所述有源面具有接垫。在所述管芯之间形成缺口，所述缺口裸露出所述管芯的第一侧壁。在所述晶片上形成钝化层，覆盖所述管芯的表面，裸露出所述接垫的表面。于所述钝化层上形成第一重布线层，电连接所述接垫。进行切割制作工艺，使所述晶片上的所述管芯彼此分离。将所述管芯安装于基底上，所述基底上具有第二重布线层。形成连接部，连接所述第一重布线层与所述第二重布线层。
依照本发明实施例所述，所述形成连接部的方法包括：在所述钝化层与所述第一重布线层上形成第一保护层，裸露出所述第一重布线层的第一末端；在所述基底与所述第二重布线层上形成第二保护层，裸露出所述第二重布线层的第二末端；以及以电镀法或无电镀法形成所述连接部。
依照本发明实施例所述，所述在所述管芯之间形成所述多个缺口包括：在所述晶片上形成所述钝化层之前，从所述管芯的所述有源面向所述无源面进行预切所述晶片制作工艺，或是进行光刻制作工艺与蚀刻制作工艺，且其中所述钝化层还覆盖所述晶片的所述第一侧壁。
依照本发明实施例所述，所述在所述管芯之间形成所述多个缺口包括：在所述晶片上形成所述钝化层之后，从所述管芯的所述无源面向所述有源面进行预切所述晶片制作工艺。
依照本发明实施例所述，所述将所述管芯安装于所述基底上是通过形成在所述基底上的粘着层。
依照本发明实施例所述，所述将所述管芯安装于所述基底上是通过形成在所述基底上的所述粘着层以及所述粘着层上的液滴。
依照本发明实施例所述，所述管芯的所述有源面比所述无源面接近所述粘着层。
依照本发明实施例所述，所述管芯的所述无源面比所述有源面接近所述粘着层接触。
依照本发明实施例所述，所述基底包括凹槽，且所述管芯安装于所述基底的所述凹槽中，且所述粘着层位于所述凹槽中。
基于上述，本发明实施例的方法可以采用低温的方式进行接合。此外，本发明以采用晶片级或面板级制作工艺来进行多个管芯的安装。此外，利用液体状的粘着层或是通过液滴可以在安装时具有自行对准组装的功效。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至1C是本发明实例的第一管芯的制造流程的剖面示意图；
图1D是图1C的上视图；
图2A至2D是本发明实例的第二管芯的制造流程的剖面示意图；
图2E是图2D的上视图；
图3A至3D是本发明实例的第三管芯的制造流程的剖面示意图；
图3E是图3D的上视图；
图4A至4D是本发明实例的第四管芯的制造流程的剖面示意图；
图4E是图4D的上视图；
图5A至5D是本发明实例的第五管芯的制造流程的剖面示意图；
图5E是图5D的上视图；
图6A至6D是本发明第一实例的一种异质整合组装结构的制造流程的剖面示意图；
图6E是图6D的上视图；
图7A至7C是本发明第二实例的一种异质整合组装结构的制造流程的剖面示意图；
图7D是图7C的上视图；
图8A至8C是本发明第三实例的一种异质整合组装结构的制造流程的剖面示意图；
图8D是图8C的上视图；
图9A至9D是本发明实例的一种异质整合组装结构的制造流程的剖面示意图；
图10A至10C是本发明第四实例的一种异质整合组装结构的制造流程的剖面示意图；
图10D是图10C的上视图；
图11A至11D是本发明实例的一种异质整合组装结构的制造流程的剖面示意图；
图12是依据本发明实例的多个管芯的剖面示意图。
具体实施方式
第一管芯的制作
请参照图1A，提供晶片40a。晶片40a包括多个彼此连接的芯片10a(chip)。芯片10a可分别为存储器芯片、逻辑芯片、数字芯片、模拟芯片、传感器芯片(sensor chip)、无线射频芯片(wireless and radio frequency chip)、发光二极管(LED)、微机电元件(MEMSdevice)或电压调节器芯片等。传感器芯片可为影像传感器芯片或压力传感器、空气微粒传感器…等，至少包括电荷耦合元件(CCD)或互补金属氧化物半导体影像传感器(CMOS imagesensor)。芯片10a可为相同类型的芯片或不同类型的芯片。芯片10a可通过芯片切割制作工艺沿切割道58分隔开。
在一些实施例中，晶片40a可包括基底50、元件层52、金属化结构54以及多个接垫56。金属化结构54包括介电层以及位于介电层中的金属内连线结构(图中未示出)。换句话说，芯片10a分别包括基底50、元件层52、金属化结构54以及多个接垫56。接垫56通过金属化结构54的金属内连线结构与位于元件层52之中的元件电连接。
基底50是半导体基底，例如硅基底。举例来说，基底50是块状(bulk)硅基底、掺杂硅基底、未掺杂硅基底或绝缘体上覆硅(silicon-on-insulator，SOI)基底。掺杂硅基底的掺质可为P型掺质、N型掺杂质，或N型掺质与P型掺杂质的组合。基底50也可以其他半导体材料形成。所述其他半导体材料包括硅锗、碳化硅、砷化镓或其类似物，但不限于此。基底40中还可包括有源区及隔离结构(图中未示出)。
元件层(device layer)52包括形成在基底40的有源区上的多种元件(图中未示出)。在一些实施例中，所述元件包括有源元件、无源元件或有源元件与无源元件的组合。在一些实施例中，举例来说，所述元件包括集成电路元件。在一些实施例中，所述元件例如为晶体管、二极管、光电二极管、电容器、电阻器、熔丝元件或其他类似元件。也就是说，晶片40a是形成有元件的晶片，而非载体。金属化结构54形成在基底50及元件层52上。在一些实施例中，金属化结构54包括多层介电层以及形成在多层介电层中的金属内连线结构。所述金属内连线结构与元件层52中的元件电连接，其包括多层金属线及多个插塞。
接垫56形成在金属化结构54上，并且于金属化结构54中的金属内连线结构电连接，以提供元件层52中的元件的外部连接。接垫56的材料可包括金属或金属合金，例如镍(Ni)、锡(Sn)、金(Au)、铜(Cu)、银(Ag)、其合金或其复合材料等，但不限于此。接垫56的顶面与金属化结构54的顶面形成晶片40a的有源面80a。在一些实施例中，所述有源面80a被称为晶片40a的第一表面(或称为前表面)，而晶片40a的第二表面(或称为背表面)(即，底表面)与第一表面相对，又称为无源面82a。
请参照图1B，在晶片40a上形成具有顶通孔(top via hole)的钝化层60。顶通孔裸露出部分的接垫56的表面。钝化层60覆盖金属化结构54的表面以及另一部分的接垫56的表面。钝化层60层可为单层结构或多层结构。钝化层60包含绝缘材料，例如氧化硅、氮化硅、聚合物或其组合。所述聚合物为例如聚苯并恶唑(PBO)、聚酰亚胺(Polyimide,PI)、苯并环丁烯(BCB)、其组合或其类似物。
请继续参照图1B，在钝化层60上形成第一重布线层62。第一重布线层62又可以称为第一线路层。第一重布线层62与接垫56电连接。第一重布线层62包括彼此连接的多个通孔(via)64和多个第一迹线(trace)66。通孔64纵向延伸，穿过钝化层60，以连接接垫56。第一迹线66分别位于钝化层60上，并且分别在钝化层60的顶面上水平方向上延伸。在一些实施例中，通孔64的横截面形状是正方形、矩形或倒梯形。在一些实施例中，通孔64的底角δ是钝角或直角。
第一重布线层62的材料包括金属，例如铜、镍、钛及其组合等。第一重布线层62可以通过电镀或无电镀制作工艺形成。在一些实施例中，第一重布线层62包括晶种层(未示出)和在其上形成的金属层(未示出)。晶种层(seed layer)可以是金属种子层，例如铜晶种层。在一些实施例中，晶种层包括第一金属层(例如钛层)以及第二金属层(例如第一金属层上的铜层)。晶种层上的金属层可以是铜或其他合适的金属。
请继续参照图1B，在晶片40a上形成多个保护层70。保护层70覆盖位于芯片10a的中心区的钝化层60与第一重布线层62。保护层70裸露出每一芯片10a边缘区的钝化层60与第一迹线66的末端(第一端)66E1。保护层70的材料与钝化层60的材料不同。保护层70可为单层结构或多层结构。保护层70可以是绝缘材料。保护层70可以是无机材料或是有机材料，例如氧化硅、氮化硅、聚合物或其组合。所述聚合物为例如聚苯并恶唑(PBO)、聚酰亚胺(Polyimide,PI)、苯并环丁烯(BCB)、其组合或其类似物。
请参照图1C与图1D，进行晶片40a的切割制作工艺，沿切割道58将多个芯片10a彼此分离，以形成多个第一管芯12a。
第一管芯12a的有源面80a的中心区CA被保护层70覆盖。第一管芯12a的有源面80a的边缘区EA未被保护层70覆盖，而裸露出第一重布线层62的末端。换言之，第一重布线层62位于中心区CA之中的部分，亦即连接接垫56的第一迹线66的末端(第二端)66E2以及第一迹线66的主体部66S被保护层70覆盖。第一重布线层62位于边缘区EA之中的另一部分，亦即第一迹线66的末端(第一端)66E1未被保护层70覆盖，而裸露出来。
第一管芯12a具有垂直的侧壁S1，且被裸露出来。换言之，第一迹线66的末端66E1、钝化层60、金属化结构54、元件层52以及基底50的侧壁大致共平面，而形成垂直的侧壁S1。
第二管芯的制作
请参照图2A与图2B，依照制作第一管芯12a的方式，提供晶片40b，并在晶片40b上形成钝化层60、第一重布线层62与保护层70。
请参照图2C，在进行切割制作工艺之前，从芯片10b的无源面82b的向有源面80b进行预切晶片制作工艺，以在晶片40b的切割道58周围形成缺口72。缺口72相邻的两个芯片10b局部地分离。缺口72裸露出芯片10b的侧壁。缺口72的剖面形状例如是呈倒V字型。缺口74的深度D1可以小于、等于或是大于基底50的总厚度T1。请参照图2D与图2E，进行切割制作工艺，使晶片40b上的芯片10b彼此完全分离，以形成多个第二管芯12b。请参照图2D与图2E，第二管芯12b的有源面80b投影在基底50的表面上的面积大于无源面82b投影在基底50表面上的面积。
第二管芯12b的有源面80b的中心区CA被保护层70覆盖。第二管芯12b的有源面80b的边缘区EA未被保护层70覆盖，而裸露出部分的第一重布线层62。换言之，第一重布线层62位于中心区CA之中的部分，亦即连接接垫56的第一迹线66的末端(第二端)66E2以及第一迹线66的主体部66S被保护层70覆盖。第一重布线层62位于边缘区EA之中的另一部分，亦即第一迹线66的末端(第一端)66E1未被保护层70覆盖，而裸露出来。
第二管芯12b具有倾斜的侧壁S2。侧壁S2与基底50的底面(无源面82b)所夹的内角α为钝角。第二管芯12b的侧壁S2裸露出来，而未被保护层70以及钝化层60覆盖。
第三管芯的制作
请参照图3A，提供晶片40c。晶片40c包括多个彼此连接的芯片10c。晶片40c、芯片10c分别与晶片40a、芯片10a相似。每一芯片10c具有有源面80c与无源面82c。有源面80c具有接垫56。
请参照图3B，从芯片10c的有源面80c向无源面82c进行预切晶片制作工艺，以在晶片40c的切割道58周围形成缺口74。缺口74分离相邻的两个芯片10c。缺口74的剖面形状例如是呈V字型。缺口74裸露出芯片10c的侧壁S3。无源面82c与侧壁S3所夹的内角β为锐角。缺口74延伸至晶片40c的基底50之中。在基底50中的缺口74的深度D2可以小于、等于或是大于基底50的总厚度T1。
请参照图3C，在进行预切晶片制作工艺之后，在晶片40c上形成钝化层60与第一重布线层62。钝化层60覆盖芯片10c的表面以及缺口74所裸露的侧壁S3，并且钝化层60的顶通孔裸露出接垫56的表面。第一重布线层62形成在芯片10c以及缺口74上的钝化层60上，并且与接垫56电连接。
请参照图3C，在晶片40c上形成多个保护层70。保护层70覆盖位于芯片10c的中心区的钝化层60与第一重布线层62。保护层70裸露出芯片10c的边缘区以及侧壁S3上的钝化层60与第一迹线66。
请参照图3D与图3E，自缺口74处进行切割制作工艺，使晶片40c上的芯片10c彼此分离，以形成多个第三管芯12c。第三管芯12c的有源面80c投影在基底50的表面上的面积小于无源面82c投影在基底50的表面上的面积。第三管芯12c具有倾斜的侧壁S3。侧壁S3被钝化层60覆盖，且侧壁S3上的钝化层60上有第一重布线层62。
第三管芯12c的有源面80c的中心区CA被保护层70覆盖。第三管芯12c的边缘区EA以及侧壁S3未被保护层70覆盖，而裸露出部分的钝化层60以及部分的第一重布线层62。换言之，第一迹线66位于中心区CA之中的部分，亦即连接接垫56的第一迹线66的末端(第二端)66E2以及第一迹线66的主体部66S被保护层70覆盖。第一迹线66位于边缘区EA以及侧壁S3上的部分66p以及末端(第一端)66E1未被保护层70覆盖，而裸露出来。
第四管芯的制作
请参照图4A，提供晶片40d。晶片40d包括多个彼此连接的芯片10d。晶片40d、芯片10d分别与晶片40a、芯片10a相似。每一芯片10d具有有源面80d与无源面82d。有源面80d具有接垫56。
请参照图4B，从芯片10d的有源面80a向无源面82a进行光刻与蚀刻制作工艺，以在晶片40的切割道58周围形成缺口76。缺口76将相邻的两个芯片10d部分分离。缺口76的剖面形状例如是呈U字型。依据蚀刻制作工艺的不同，缺口76的形状可以有些微不同。以各向同性各向异性蚀刻制作工艺所形成的缺口76的侧壁S4大致为垂直平面或倾协平面。侧壁S4与晶片40d的基底50的表面的夹角θ1为锐角或直角。缺口76延伸到基底50中。在基底50中的缺口76的深度D3小于基底50的总厚度T1。请参照图4C，在所述晶片40上形成钝化层60，覆盖芯片10d的表面以及缺口76的侧壁S4与底面，裸露出接垫56的表面。于钝化层60上形成第一重布线层62，电连接接垫56。第一重布线层62覆盖接垫56的表面，并延伸覆盖芯片10d的边缘上的钝化层60以及缺口76上的部分的钝化层60。
请参照图4D，自缺口76的底面进行切割制作工艺，使晶片40上的芯片10d彼此分离，以形成多个第四管芯12d。
第四管芯12d的有源面80a投影在基底50的表面上的面积小于无源面82a投影在基底50的表面上的面积。第四管芯12d具有阶梯状的侧壁St4。阶梯状的侧壁St4包括第一侧壁S41与第二侧壁S42。第一侧壁S41与无源面82a的夹角γ1可以是直角。第一侧壁S41裸露出基底50，其未被钝化层60覆盖，也未被第一重布线层62覆盖。第二侧壁S42与基底50的表面的夹角θ1为锐角或直角。第二侧壁S41被钝化层60覆盖，且第二侧壁S41上的钝化层60上有第一重布线层62。
第四管芯12d的有源面80d的中心区CA被保护层70覆盖。第四管芯12d的边缘区EA以及侧壁St4未被保护层70覆盖，而裸露出部分的钝化层60以及部分的第一重布线层62。换言之，第一迹线66位于中心区CA之中的部分，亦即连接接垫56的第一迹线66的末端(第二端)66E2以及第一迹线66的主体部66S被保护层70覆盖。第一迹线66位于边缘区EA以及侧壁St4上的部分66p以及末端(第一端)66E1未被保护层70覆盖，而裸露出来。
第五管芯的制作
请参照图5A至图5C，第五管芯12e的制作方法与第四管芯12d的制作方法相似，差异点在于缺口78是以光刻制作工艺与各向同性蚀刻制作工艺形成。以各向同性蚀刻制作工艺所形成的缺口78的剖面形状例如是呈U字型，但缺口78具有弧状的侧壁S5。缺口78的侧壁S5与基底50的表面的夹角θ2为直角或钝角。在缺口78延伸到基底50中。基底50中的缺口78的深度D4小于基底50的总厚度T1。
请参照图5D与图5E，自缺口78的底面进行切割制作工艺，使晶片40e上的芯片10e彼此分离，以形成多个第五管芯12e。
第五管芯12e与第四管芯12d相似。第五管芯12e的有源面80e投影在基底50的表面上的面积小于无源面82a投影在基底50的表面上的面积，且第五管芯12e也是具有阶梯状的侧壁St5。阶梯状的侧壁St5包括第一侧壁S51与第二侧壁S52。第一侧壁S51与无源面82a的夹角γ2可以是直角。第一侧壁S51裸露出基底50，其未被钝化层60覆盖，也未被第一重布线层62覆盖。第二侧壁S52与基底50的表面的夹角θ2为直角或钝角。第二侧壁S52被钝化层60覆盖，并且第二侧壁S52上的钝化层60上覆有第一重布线层62。
请参照图12，在以上第一管芯12a、第二管芯12b、第三管芯12c、第四管芯12d以及第五管芯12e的制作的过程中，可以在进行切割之前，在保护层70的上方或是基底50的上方形成突起物75，如图12中的管芯12a’、12b’、12c’、12c”、12d’以及12e’。突起物75可以是由介电材料、半导体材料或金属材质制作。突起物75的形成方法例如是利用光刻与蚀刻制程。突起物75可以提供组装过程中取放芯片的自由度。此外，在组装后，突起物75可以做为架构的一部分。
上述的管芯可以采用晶片级或面板级制作工艺来安装在基底上，可以采用批次的方式，同时将多个管芯安装在基底上，然而，为了简化起见，以下的实施例以单一个管芯来说明之。
第一实施例
请参照图6A，提供基底100。基底100的材料可以是有机材料或是无机材料。基底100可为封装基板例如可挠式基板、软性基板、中介基板或印刷电路板等。或者，基底100可例如是包含多个半导体芯片的半导体晶片或包含多个管芯的重构晶片(reconstructedwafer)。基底100可为例如半导体管芯或形成有半导体集成电路的半导体芯片，包括存储器芯片、逻辑芯片、数字芯片、模拟芯片、传感器芯片、无线射频芯片或电压调节器芯片等。其中传感器芯片可为影像传感器芯片，至少包括电荷耦合元件或互补金属氧化物半导体影像传感器。
在基底100上形成第二重布线层102。在一些实施例中，在基底100和第二重布线层102之间还包括介电层，或更包括其他的元件层。第二重布线层102又称为第二线路层。第二重布线层102可以包括通孔(未示出)与迹线106。第二重布线层102的材料包括金属，例如铜、镍、钛及其组合等。第二重布线层1022可以通过电镀或无电镀制作工艺形成。在一些实施例中，第二重布线层102包括晶种层(未示出)和在其上形成的金属层(未示出)。晶种层可以是金属种子层，例如铜晶种层。在一些实施例中，晶种层包括第一金属层(例如钛层)以及第二金属层(例如第一金属层上的铜层)。晶种层上的金属层可以是铜或其他合适的金属。
请参照图6B，移除部分的基底100以及部分的第二重布线层102，以在基底100中形成多个凹槽(cavity)104。移除部分基底100的方法例如是进行光刻制作工艺与蚀刻制作工艺。凹槽104的底角σ的角度例如是直角或是钝角。
请参照图6B，在基底100上形成保护层105。保护层105覆盖部分的第二重布线层102。保护层105裸露出凹槽104周围的第二重布线层102的迹线106的末端106E。保护层105的材料可以与保护层70的材料相同或相异。保护层105可为单层结构或多层结构。保护层105可以是绝缘材料。保护层105可以是无机材料或是有机材料，例如氧化硅、氮化硅、聚合物或其组合。所述聚合物为例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合或其类似物。
请参照图6C，在基底100的凹槽104之中形成粘着层116a。粘着层116a的材料可以是有机材料或是无机材料。有机材料例如是环氧树脂、聚二甲基硅氧烷(PDMS)等。无机材料包括氧化物，例如是氧化硅。在一些实例中，粘着层116a可以是以固态状的方式形成在基底100的凹槽104之中。在另一些实施例中，粘着层116a可以是以液态状的方式形成在基底100的凹槽104之中，并且可以在后续将管芯放置在凹槽104之后，通过加热以固化之。
请参照图6C，以拾取与放置(pick and place)的方式将多个第一管芯12a的无源面82a朝向基底100，使第一管芯12a安装于多个凹槽104之中。第一管芯12a的有源面80a上的第一重布线层62的末端66E1对准基底100上的第二重布线层102的迹线106的末端106E，并且使第一管芯12a的无源面82a与凹槽104之中的粘着层116a接触。在粘着层116a为液态状的实施例中，在将第一管芯12a放置于凹槽104之后，通过低温加热以固化之。通过粘着层116a厚度/体积的适当控制，可以避免溢胶，并且粘着层116a固化之后，可以使得第一重布线层62的表面与第二重布线层102的表面大致在相同的高度。在一实施例中，第一重布线层62的表面与第二重布线层102的表面共平面。
请参照图6D与图6E，在第一重布线层62的末端66E1与第二重布线层102的迹线106的末端106E形成连接部108a，以连接第一重布线层62与第二重布线层102。形成连接部108a的方法可以包括电镀、无电镀等。在以电镀或无电镀形成连接部108a的实施例中，在制作工艺初期，在第一重布线层62的末端66E1与第二重布线层102的迹线106的末端106E分别形成第一导体材料与第二导体材料。第一导体材料环绕包覆第一重布线层62的末端66E1的顶面与侧壁。第二导体材料环绕包覆第二重布线层102的迹线106的末端106E的顶面与侧壁。在制作工艺后期，第一导体材料与第二导体材料逐渐向外成长而彼此接触连接之后，即可形成连接部108a。换言之，通过电镀、无电镀的方式，连接部108a可以自行对准第一重布线层62的末端66E1与第二重布线层102的迹线106的末端106E。进行电镀、无电镀制作工艺的温度相当低，例如是摄氏100度以下，因此，管芯可以以低温的方式接合在基底100上。
在以电镀或无电镀形成连接部108a的实施例中，连接部108a覆盖第一重布线层62的末端66E1的顶面与侧壁以及第二重布线层102的迹线106的末端106E的顶面与侧壁。因此，连接部108a的宽度W31大于第一重布线层62的迹线的66宽度W11，且大于第二重布线层102的宽度W21。此外，连接部108a的形状例如是呈不规则状或是具有弧形的轮廓。
至此，形成了异质整合组装结构180a。之后，可以将再进行切割制作工艺。保护层70以及105可以在切割制作工艺之前移除，或者保留下来。
第二实施例
请参照图7A，以上述第一实例的方式提供基底100。基底100上有第二重布线层102以及保护层105。基底100有多个凹槽104。
请参照图7B，在基底100的凹槽104之中形成粘着层116b，并以拾取与放置的方式将多个第二管芯12b无源面82b朝向基底100，使安装于凹槽104之中。第二管芯12b的无源面82b接触粘着层116b，并且第一重布线层62的末端66E对准第二重布线层102的迹线106的末端106E。
请参照图7C与7D，在第一重布线层62的末端66E1的表面与侧壁上以及第二重布线层102的迹线106的末端106E的表面与侧壁上形成连接部108b，以连接第一重布线层62与第二重布线层102。连接部108b的形成方法以及其轮廓与连接部108a的形成方法以及其轮廓相似，于此不再赘述。
至此，形成了异质整合组装结构180b。之后，可以将再进行切割制作工艺。异质整合组装结构180b中的第二管芯12b具有倾斜侧壁S2。第二管芯12b的有源面80a投影在基底50表面上的面积大于无源面82a投影在基底50的表面上的面积。无源面82a与侧壁S2所夹的内角α为钝角。粘着层116b不仅与管芯的无源面82a接触，还与第二管芯12b的侧壁S2接触。
第三实施例
请参照图8A，提供具有平坦表面的基底100。在基底100上形成第二重布线层102以及保护层105。
请参照图8B，在基底100的第二重布线层102之间的基底100上形成粘着层116c。粘着层116c可以是以液态状的方式形成在基底100上。在一实施例中，液体状的粘着层116c具有亲水性(hydrophilic)，第二重布线层102具有疏水性(hydrophobic)。
请参照图8B，以拾取与放置的方式将多个第三管芯12c的无源面82a朝向基底100，使第三管芯12c安装于基底的平坦面上。第三管芯12c的无源面82a与粘着层116c接触，并且第三管芯12c的侧壁S3上的迹线66的末端66E1对准基底100上的第二重布线层102的迹线106的末端106E。
请参照图9A，在一实施例中，在进行安装之前，粘着层116c为具有亲水性的固体、胶体或是液体；第二重布线层102为固体，且具有疏水性。
请参照图9B，在粘着层116c上可以覆上亲水性的液滴120a，例如是水滴。有些液滴120a覆盖在第二重布线层102上，如图9B所示。
请参照图9C，将第三管芯12c安装在基底100的粘着层116c上。若安装时发生偏移，使得第三管芯12c的偏移至第二重布线层102上的液滴120a上。随着时间的递延，第三管芯12c还是可以自行对准在第二重布线层102之间的粘着层116c，而移动到第二重布线层102之间，如图9D所示。这是因为粘着层116c与第二重布线层102具有不同的表面张力，随着时间的递延，覆盖在第二重布线层102上的部分的液滴120a会倾向与位于第二重布线层102之间的另一部分的液滴120a聚集在一起，藉此，第三管芯12c可以自行对准组装在第二重布线层102之间的粘着层116c上。之后，可以进行加热制作工艺，将液滴120a移除，使第三管芯12c与粘着层116c接触，而安装在基底100上。
请参照图8C与8D，将第三管芯12c安装在基底100上之后，在迹线66的末端66E1的表面与侧壁上以及迹线106的末端106E的表面与侧壁上形成连接部108c，以连接第一重布线层62与第二重布线层102。在一些实施例中，连接部108c还覆盖第三管芯12c的侧壁S3上的迹线66的部分66p。形成连接部108c的方法的形成方法以及其轮廓与连接部108a的形成方法以及其轮廓相似，于此不再赘述。
至此，形成了异质整合组装结构180c。之后，可以将再进行切割制作工艺。
第四实施例
在第三实施例中，在进行安装时，第三管芯12c的无源面82a朝向基底100。请参照图10A与图10B，在本实施例中，仍是以拾取与放置的方式将多个第三管芯12c安装于基底100之上。但是，在进行安装时，第三管芯12c的有源面80c朝向基底100，使第三管芯12c的保护层70与粘着层116d接触。在第三管芯12c的侧壁S3上的迹线66的部分66p与基底100上的迹线106对准。
请参照图11A至11D，相似于第三实施例，在一实施例中，在进行安装之前，粘着层116d可以是具有亲水性的固体、胶体或是液体；第二重布线层102为固体，且具有疏水性。在粘着层116d上覆上亲水性的液滴120b，即使安装第三管芯12c时发生偏移，通过表面张力不同的特性，第三管芯12c通过液滴120b移动，而自行对准组装在第二重布线层102之间的粘着层116d。之后，可以进行加热制作工艺，将液滴120b移除，使第三管芯12c与粘着层116d接触，而安装在基底100上。
此外，在一些实施例中，为了提升第三管芯12c与粘着层116d之间的粘着性，可以对第三管芯12c的侧壁S3上的第一重布线层62以及钝化层60进行表面处理，以增加其表面张力，使液滴120b不仅与第三管芯12c的有源面80a接触，而且还与第三管芯12c的侧壁S3上的第一重布线层62以及钝化层60接触，如图11D所示。表面处理例如是等离子清洁或者紫外线照射清洁。
之后，请参照图10C与10D，将第三管芯12c安装在基底100上之后，在迹线66的部分66p的表面与侧壁上以及迹线106的末端106E的表面与侧壁上形成连接部108d，以连接第一重布线层62与第二重布线层102。在一些实施例中，连接部108d会延伸至保护层70边缘，甚至与保护层70接触。
至此，形成了异质整合组装结构180d。之后，可以将再进行切割制作工艺。
上述的第四管芯12d与第五管芯12e可以通过粘着层安装在具有凹槽的基底上，如上述第二实施例所述。
综上所述，本发明可以通过超低温制作工艺例如是电镀或无电镀的方式，可以在大气环境下实现低温接合。再者，本发明以采用晶片级或面板级制作工艺来进行多个管芯的安装。此外，利用液体状的粘着层或是通过液滴可以在安装时具有自行对准组装的功效。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种异质整合组装结构，其特征在于，包括：
基底；
管芯，安装于所述基底上，其中所述管芯具有有源面与无源面，所述有源面具有接垫；
钝化层，覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面；
第一重布线层，位于所述钝化层上，电连接所述接垫；
第二重布线层，位于所述基底上，与所述管芯相邻；以及
连接部，连接所述第一重布线层与所述第二重布线层。
2.如权利要求1所述的异质整合组装结构，其中所述连接部的宽度大于所述第一重布线层的宽度，且大于所述第二重布线层的宽度。
3.如权利要求1所述的异质整合组装结构，还包括粘着层，位于所述管芯与所述基底之间。
4.如权利要求3所述的异质整合组装结构，其中所述管芯的所述无源面与所述粘着层接触。
5.如权利要求3所述的异质整合组装结构，其中所述管芯的侧壁与所述粘着层接触。
6.如权利要求4所述的异质整合组装结构，其中所述管芯的所述有源面比所述无源面接近所述粘着层。
7.如权利要求3所述的异质整合组装结构，其中所述粘着层具有亲水性。
8.如权利要求1所述的异质整合组装结构，其中所述基底具有凹槽，所述管芯安装于所述凹槽中。
9.如权利要求8所述的异质整合组装结构，其中所述管芯的所述有源面的面积大于或等于所述无源面的面积。
10.如权利要求1所述的异质整合组装结构，其中所述管芯的所述有源面的面积小于所述无源面的面积。
11.如权利要求1所述的异质整合组装结构，其中所述管芯的具有垂直侧壁、倾斜侧壁、阶梯侧壁、弧形侧壁或其组合。
12.一种异质整合组装结构的制造方法，包括：
提供晶片，所述晶片包括多个管芯，其中每一所述管芯具有有源面与无源面，所述有源面具有接垫；
在所述管芯之间形成缺口，所述缺口裸露出所述管芯的第一侧壁；
在所述晶片上形成钝化层，覆盖所述管芯的表面，裸露出所述接垫的表面；
在所述钝化层上形成第一重布线层，电连接所述接垫；
进行切割制作工艺，使所述晶片上的所述管芯彼此分离；
将所述管芯安装于基底上，所述基底上具有第二重布线层；以及
形成连接部，连接所述第一重布线层与所述第二重布线层。
13.如权利要求12所述的异质整合组装结构的制造方法，其中所述形成连接部的方法包括：
在所述钝化层与所述第一重布线层上形成第一保护层，裸露出所述第一重布线层的第一末端；
在所述基底与所述第二重布线层上形成第二保护层，裸露出所述第二重布线层的第二末端；以及
以电镀法或无电镀法形成所述连接部。
14.如权利要求12所述的异质整合组装结构的制造方法，其中所述在所述管芯之间形成所述多个缺口包括：
在所述晶片上形成所述钝化层之前，从所述管芯的所述有源面向所述无源面进行预切所述晶片制作工艺，或是进行光刻制作工艺与蚀刻制作工艺，且其中所述钝化层更覆盖所述晶片的所述第一侧壁。
15.如权利要求14所述的异质整合组装结构的制造方法，其中所述在所述管芯之间形成所述多个缺口包括：
在所述晶片上形成所述钝化层之后，从所述管芯的所述无源面向所述有源面进行预切所述晶片制作工艺。
16.如权利要求12所述的异质整合组装结构的制造方法，其中所述将所述管芯安装于所述基底上是通过形成在所述基底上的粘着层。
17.如权利要求16所述的异质整合组装结构的制造方法，其中所述将所述管芯安装于所述基底上是通过形成在所述基底上的所述粘着层以及所述粘着层上的液滴。
18.如权利要求16所述的异质整合组装结构的制造方法，其中所述管芯的所述有源面比所述无源面接近所述粘着层。
19.如权利要求16所述的异质整合组装结构的制造方法，其中所述管芯的所述无源面比所述有源面接近所述粘着层接触。
20.如权利要求16所述的异质整合组装结构的制造方法，其中所述基底包括凹槽，且所述管芯安装于所述基底的所述凹槽中，且所述粘着层位于所述凹槽中。
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