CN110854223A - Preparation method of drift detector and drift detector - Google Patents
Preparation method of drift detector and drift detector Download PDFInfo
- Publication number
- CN110854223A CN110854223A CN201911155931.8A CN201911155931A CN110854223A CN 110854223 A CN110854223 A CN 110854223A CN 201911155931 A CN201911155931 A CN 201911155931A CN 110854223 A CN110854223 A CN 110854223A
- Authority
- CN
- China
- Prior art keywords
- region
- isolation
- layer
- masking layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 220
- 230000000873 masking effect Effects 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 60
- 229920002120 photoresistant polymer Polymers 0.000 claims description 60
- 150000002500 ions Chemical class 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 32
- 238000005468 ion implantation Methods 0.000 claims description 30
- 238000000059 patterning Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000005658 nuclear physics Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention provides a preparation method of a drift detector, which comprises the steps of respectively forming a first masking layer and a second masking layer on two sides of a substrate, selectively removing the first masking layer and the second masking layer to form a first isolation region and a second isolation region, carrying out ion doping on the first isolation region to form a first doped isolation region, respectively forming a first isolation layer and a second isolation layer on the surfaces of the first doped isolation region and the second isolation region, removing the first masking layer to form an anode region and a drift ring region, and removing the second masking layer to form a collection region; respectively carrying out ion doping and annealing on the anode region, the drift ring region and the collecting region; forming a dielectric layer and a contact hole in the anode region, the drift ring region and the collecting region; and forming a metal lead in the contact hole. According to the invention, different doping types between the first doping isolation region and the drift ring region are designed, so that electric leakage between the drift ring regions is avoided, and high breakdown voltage and low dark current are realized. The invention also provides a drift detector obtained by applying the preparation method.
Description
Technical Field
The invention belongs to the field of semiconductor detectors, and particularly relates to a drift detector and a preparation method thereof.
Background
The silicon drift detector is characterized in that a large-area uniform PN abrupt junction is prepared on a ray incidence surface of a high-purity N-type silicon chip, a point-shaped N-type anode is prepared in the center of the other surface opposite to the ray incidence surface, and a plurality of concentric P-type drift electrodes are arranged around the N-type anode. When the silicon drift detector works, reverse voltage is applied to PN junctions on two sides of the silicon drift detector, and therefore a potential well is generated in the silicon drift detector. After a potential difference is added on the P-type drift electrode, a transverse electric field can be generated in the silicon drift detector, and the transverse electric field bends the potential well, so that electrons generated by the radiation of the incident surface are forced to drift towards the N-type anode under the action of the electric field and reach the vicinity of the N-type anode to generate signals. The lateral PN junction structure of the silicon drift detector enables the capacitance of the silicon drift detector to be small, and meanwhile, the leakage current of the silicon drift detector is small, so that electronic signals can be output quickly with low noise. In view of the above advantages of the silicon drift detector, the silicon drift detector is widely applied to the fields of medical imaging, X-ray energy spectrum, national security, celestial physics, high-energy nuclear physics and the like.
The manufacturing process and flow of the existing silicon drift detector are more complicated than those of a common semiconductor device, and particularly the manufacturing difficulty of a conventional semiconductor factory only having a single-side photoetching process is higher. In the existing silicon drift detector manufacturing process, an isolation layer is usually grown on a substrate, and then an anode region, a drift ring region and a collection region are etched, so that the anode region, the drift ring region and the collection region are damaged by the etching process, and the performance of a device is reduced.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a drift detector and a method for manufacturing the same.
In order to achieve the purpose, the invention adopts the following technical scheme: a method of making a drift detector, comprising: providing a semiconductor substrate, forming a first masking layer on the front side of the semiconductor substrate, forming a second masking layer on the back side of the semiconductor substrate, selectively removing the first masking layer to form a first isolation region, and selectively removing the second masking layer to form a second isolation region; carrying out ion doping on the first isolation region to form a first doped isolation region, forming a first isolation layer on the surface of the first doped isolation region, and forming a second isolation layer on the surface of the second isolation region; removing the first masking layer, forming an anode region and a drift ring region in the interval of the first doped isolation region, removing the second masking layer, and forming a collecting region in the interval of the second isolation region; or forming a second masking layer on the front surface of the semiconductor substrate, forming a first masking layer on the back surface of the semiconductor substrate, selectively removing the second masking layer to form a second isolation region, and selectively removing the first masking layer to form a first isolation region; carrying out ion doping on the first isolation region to form a first doped isolation region, forming a first isolation layer on the surface of the first doped isolation region, and forming a second isolation layer on the surface of the second isolation region; removing the first masking layer, forming an anode region and a drift ring region in the interval of the first doped isolation region, removing the second masking layer, and forming a collecting region in the interval of the second isolation region; respectively carrying out ion doping on the anode region, the drift ring region and the collecting region, wherein the ion doping type of the anode region is the same as that of the first doping isolation region, and the ion doping types of the drift ring region and the collecting region are opposite to that of the anode region; annealing the semiconductor substrate; forming dielectric layers on the surfaces of the anode region, the drift ring region and the collecting region; and forming a contact hole penetrating through the dielectric layer along the thickness direction of the semiconductor substrate on the dielectric layer, and filling the contact hole to form a metal lead.
Preferably, the method further comprises the following steps: before forming the first masking layer and the second masking layer, an oxide layer is formed on the front surface and the back surface of the semiconductor substrate.
Preferably, the step of forming the first isolation region comprises: coating photoresist on the surface of the first masking layer; patterning the photoresist to define a first isolation region; removing the first masking layer on the surface of the first isolation region by adopting a dry etching process; removing the photoresist on the surface of the first masking layer; forming a second isolation region comprising: coating photoresist on the surface of the second masking layer; patterning the photoresist to define a second isolation region; removing the second masking layer on the surface of the second isolation region by adopting a dry etching process; and removing the photoresist on the surface of the second masking layer.
Preferably, the step of ion doping the first isolation region to form the first doped isolation region includes: and performing phosphorus ion implantation on the surface of the first isolation region by using the first masking layer as a mask and adopting an ion implantation process to form N-type doping, or performing boron ion implantation to form P-type doping.
Preferably, the step of forming the first and second isolation layers includes: the first isolation layer and the second isolation layer are formed by an oxidation process.
Preferably, the step of removing the first masking layer to form the anode region and the drift ring region and the step of removing the second masking layer to form the collecting region includes: and removing the first masking layer and the second masking layer by adopting a phosphoric acid wet etching process.
Preferably, the anode region is ion-doped, including: and coating photoresist on the surfaces of the anode region, the drift ring region and the first isolation layer, patterning the photoresist to define the anode region, performing phosphorus ion implantation on the anode region by taking the photoresist on the surfaces of the drift ring region and the first isolation layer as a mask to form N-type doping, or performing boron ion implantation to form P-type doping, and removing the photoresist on the surfaces of the drift ring region and the first isolation layer.
Preferably, the drift ring region is ion-doped, including: and coating photoresist on the surfaces of the anode region, the drift ring region and the first isolation layer, patterning the photoresist to define the drift ring region, performing boron ion implantation on the drift ring region by taking the photoresist on the surfaces of the anode region and the first isolation layer as a mask to form P-type doping, or performing phosphorus ion implantation to form N-type doping, and removing the photoresist on the surfaces of the anode region and the first isolation layer.
Preferably, the ion doping of the collection region comprises: and coating photoresist on the surfaces of the collecting region and the second isolating layer, patterning the photoresist to define the collecting region, carrying out boron ion implantation on the collecting region by taking the photoresist on the surface of the second isolating layer as a mask to form P-type doping, or carrying out phosphorus ion implantation to form N-type doping, and removing the photoresist on the surface of the second isolating layer.
Preferably, the annealing process is performed on the semiconductor substrate, and includes: the semiconductor substrate is subjected to an annealing treatment at 700 to 1000 ℃.
Preferably, the step of forming a dielectric layer on the surfaces of the anode region, the drift ring region and the collection region includes: and forming dielectric layers on the surfaces of the anode region, the drift ring region and the collecting region by adopting a chemical vapor deposition process, wherein the thickness of the dielectric layer is 50-200 nanometers.
Preferably, the semiconductor substrate comprises an intrinsic semiconductor substrate or a lightly doped semiconductor substrate, the oxide layer material comprises silicon oxide, and the layer thickness is 3 nanometers to 10 nanometers; the first masking layer and the second masking layer comprise silicon nitride, and the layer thickness is 10 nanometers to 50 nanometers; the materials of the first isolation layer and the second isolation layer comprise silicon oxide, and the layer thickness is 400 nanometers to 600 nanometers; the dielectric layer material comprises silicon oxide or silicon nitride, and the thickness of the layer is 50-200 nm; the metal wire includes any one of titanium, titanium nitride, aluminum, or aluminum nitride, or any one of stacked layers of titanium/titanium nitride, titanium/titanium nitride/aluminum nitride.
The invention also provides a drift detector which is characterized by comprising the drift detector formed by the preparation method.
Compared with the prior art, the invention has the following beneficial effects: in the invention, after a first isolation region and a second isolation region are formed on a semiconductor substrate, the first isolation region is ion-doped to form a first doped isolation region, forming an anode region and a drift ring region in the space of the first doped isolation region, forming a collection region in the space of the second isolation region, and the ion doping type of the anode region is the same as that of the first doping isolation region, while the ion doping types of the drift ring region and the collecting region are opposite to that of the anode region, namely, a first doping isolation region with the doping type opposite to that of the drift ring region is formed below the first isolation layer in the drift ring region interval, so that the accumulation of carriers with the same doping type as that of the drift ring region under the influence of the voltage of an upper metal lead on the semiconductor substrate below the first isolation layer is avoided, therefore, the electric leakage between the drift ring regions is reduced, and the preparation of the silicon drift detector with high breakdown voltage and low dark current is realized.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a drift detector according to an embodiment of the present invention;
fig. 2 to fig. 12 are device structures corresponding to steps in a method for manufacturing a drift detector according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a front structure of a drift detector provided by an embodiment of the invention;
fig. 14 is a schematic structural diagram of a back surface of a drift detector according to an embodiment of the present invention.
Wherein: 1. the semiconductor device comprises a semiconductor substrate, 2 a first masking layer, 3 a second masking layer, 4 a first doped isolation region, 5 a second doped isolation region, 6 a first isolation layer, 7 a second isolation layer, 8 an anode region, 9 a drift ring region, 10 a collection region, 11 a dielectric layer and 12 a metal lead.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
For better understanding of the technical solutions and effects of the present invention, the following detailed description will be made of specific embodiments with reference to fig. 1 to 14.
A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawings, which are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity. The various regions, shapes of layers, and relative sizes and positional relationships between layers shown in the drawings are merely exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
Referring to fig. 1, a method for manufacturing a drift detector according to an embodiment of the present invention includes the following steps:
S101A: providing a semiconductor substrate 1, forming a first masking layer 2 on the front surface of the semiconductor substrate 1, forming a second masking layer 3 on the back surface of the semiconductor substrate 1, selectively removing the first masking layer 2 to form a first isolation region, and selectively removing the second masking layer 3 to form a second isolation region; the first isolation region is subjected to ion doping to form a first doped isolation region 4, a first isolation layer 6 is formed on the surface of the first doped isolation region 4, a second isolation layer 7 is formed on the surface of the second isolation region, the first masking layer 2 is removed, an anode region 8 and a drift ring region 9 are formed in the interval of the first doped isolation region 4, the second masking layer 3 is removed, and a collecting region 10 is formed in the interval of the second isolation region.
First, as shown in fig. 2, a semiconductor substrate 1 is provided. The semiconductor substrate 1 may comprise any suitable semiconductor substrate material, and may specifically be, but not limited to, silicon, germanium, silicon germanium, SOI (semiconductor on insulator), silicon carbide, gallium arsenide, or any group iii-v compound semiconductor, and the like. In the present embodiment, the semiconductor substrate 1 is preferably an intrinsic silicon substrate or an N-type lightly doped silicon substrate.
As shown in fig. 3, a first masking layer 2 is deposited on the front side of the semiconductor substrate 1 and a second masking layer 3 is deposited on the back side of the semiconductor substrate 1. Specifically, silicon nitride is deposited on the front and back surfaces of the semiconductor substrate 1 by LPCVD (Low-Pressure Chemical Vapor Deposition) to form the first and second masking layers 2 and 3, wherein the first and second masking layers 2 and 3 have a thickness of 10nm to 50 nm. Preferably, an oxide layer (not shown) preferably of silicon oxide with a thickness of 3nm to 10nm may be deposited on the front and back sides of the semiconductor substrate 1 before the deposition of the first 2 and second 3 masking layers.
As shown in fig. 4, selectively removing the first masking layer 2 to form a first isolation region, specifically, spin-coating a photoresist on the surface of the first masking layer 2, and patterning the photoresist by using a photolithography process to define the first isolation region, that is, removing the photoresist corresponding to the first isolation region; the first masking layer 2 on the surface of the first isolation region is removed by adopting a dry etching process, and the oxide layer between the first masking layer 2 and the first isolation region can be removed together or notThe removal is not particularly limited herein. Specifically, the first masking layer 2 on the surface of the first isolation region is etched by adopting a plasma dry method or an oxide layer and the first masking layer 2 on the surface of the first isolation region are etched, and carbon tetrafluoride (CF) is adopted as etching gas4) And trifluoromethane (CHF)3) After the dry etching, the front surface of the semiconductor substrate 1 corresponding to the first isolation region is exposed, and then the remaining photoresist on the surface of the first masking layer 2 is removed.
Selectively removing the second masking layer 3 to form a second isolation region, specifically, spin-coating photoresist on the surface of the second masking layer 3; patterning the photoresist by utilizing a photoetching process to define a second isolation region, namely removing the photoresist corresponding to the second isolation region; and removing the second masking layer 3 on the surface of the second isolation region by adopting a dry etching process, wherein the oxide layer between the second masking layer 3 and the second isolation region can be removed together or not, and is not particularly limited herein. Specifically, the second masking layer 3 on the surface of the second isolation region is etched by adopting a plasma dry method or an oxide layer and the second masking layer 3 on the surface of the second isolation region are etched, and carbon tetrafluoride (CF) is adopted as etching gas4) And trifluoromethane (CHF)3) After the dry etching, the back surface of the semiconductor substrate 1 corresponding to the second isolation region is exposed, and then the remaining photoresist on the surface of the second masking layer 3 is removed.
As shown in fig. 5, the first isolation region is ion-doped to form a first doped isolation region 4, specifically, phosphorus ion implantation is performed on the surface of the first isolation region by using the first masking layer 2 as a mask and using an ion implantation process to form N-type doping, or boron ion implantation is performed to form P-type doping, and preferably, N-type doping is performed on the first doped isolation region 4. Optionally, ion doping is performed on the second isolation region to form a second doped isolation region 5, specifically, phosphorus ion implantation is performed on the surface of the second isolation region by using the second masking layer 3 as a mask and adopting an ion implantation process to form N-type doping, or boron ion implantation is performed to form P-type doping, the doping type of the second doped isolation region 5 is the same as that of the first doped isolation region 4, but the second isolation region may not be doped, which is not specifically limited herein.
As shown in fig. 6, a first isolation layer 6 is deposited on the surface of the first doped isolation region 4, a second isolation layer 7 is deposited on the surface of the second doped isolation region 5, the first isolation layer 6 and the second isolation layer 7 are insulating dielectric layers, the material of the insulating dielectric layers may be various insulating dielectric layer materials such as silicon oxide, aluminum oxide, silicon nitride, etc., and the deposition methods may include various methods such as dry oxygen oxidation, wet oxygen oxidation, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), etc., wherein the first isolation layer 6 and the second isolation layer 7 are preferably silicon oxide layers. Specifically, after the semiconductor substrate 1 is conventionally cleaned, hydrofluoric acid (HF) + isopropyl alcohol (IPA) + water (H) is used2O) removing the natural oxidation layer on the front surface and the back surface of the semiconductor substrate 1 by using the solution, forming a silicon oxide isolation layer on the front surface and the back surface of the semiconductor substrate 1 by using the first masking layer 2 and the second masking layer 3 as masking and adopting a wet oxygen oxidation mode, namely forming a first isolation layer 6 and a second isolation layer 7, wherein the thicknesses of the first isolation layer 6 and the second isolation layer 7 are 400nm to 600nm, and oxidizing part of the semiconductor substrate 1 by adopting the oxidation process, so that the first isolation layer 6 and the second isolation layer 7 formed by adopting the oxidation process are arranged above and below the surfaces of the first doped isolation region 4 and the second doped isolation region 5.
As shown in fig. 7, the first masking layer 2 on the front side of the semiconductor substrate 1 in the space of the first doped isolation region 4 is removed, the anode region 8 and the drift ring region 9 are formed in the space of the adjacent first doped isolation region 4, the second masking layer 3 on the back side of the semiconductor substrate 1 in the space of the second doped isolation region 5 is removed, and the collection region 10 is formed in the space of the adjacent second doped isolation region 5 or the adjacent second isolation region. Specifically, the first masking layer 2 and the second masking layer 3 are removed by a phosphoric acid etching wet process, an anode region 8 and a drift ring region 9 are formed on the front surface of the semiconductor substrate 1, and a collecting region 10 is formed on the back surface of the semiconductor substrate 1.
The method for realizing selective removal may be a photolithography method, and of course, other methods may also be adopted as long as the method for realizing such a structure is included in the scope of protection of the present application.
Through the steps, forming a first masking layer 2 on the front surface of the semiconductor substrate 1, forming a second masking layer 3 on the back surface of the semiconductor substrate 1, selectively removing the first masking layer 2 to form a first isolation region, and selectively removing the second masking layer 3 to form a second isolation region; the first isolation region is subjected to ion doping to form a first doped isolation region 4, a first isolation layer 6 is formed on the surface of the first doped isolation region 4, a second isolation layer 7 is formed on the surface of the second isolation region, the first masking layer 2 is removed, an anode region 8 and a drift ring region 9 are formed in the interval of the first doped isolation region 4, the second masking layer 3 is removed, a collection region 10 is formed in the interval of the second isolation region, namely the anode region 8 and the drift ring region 9 are formed on the front side of the semiconductor, and the collection region 10 is formed on the back side of the semiconductor. Alternatively, the anode region 8 and the drift ring region 9 may also be formed on the back surface of the semiconductor substrate 1, and the collection region 10 may also be formed on the front surface of the semiconductor substrate 1, see step S101B, which is not limited herein.
S101B: forming a second masking layer 3 on the front surface of the semiconductor substrate 1, forming a first masking layer 2 on the back surface of the semiconductor substrate 1, selectively removing the second masking layer 3 to form a second isolation region, and selectively removing the first masking layer 2 to form a first isolation region; the first isolation region is subjected to ion doping to form a first doped isolation region 4, a first isolation layer 6 is formed on the surface of the first doped isolation region 4, a second isolation layer 7 is formed on the surface of the second isolation region, the first masking layer 2 is removed, an anode region 8 and a drift ring region 9 are formed in the interval of the first doped isolation region 4, the second masking layer 3 is removed, and a collecting region 10 is formed in the interval of the second isolation region.
The difference between this step and S101A is: an anode region 8 and a drift ring region 9 are formed on the back surface of the semiconductor substrate 1, and a collection region 10 is formed on the front surface of the semiconductor substrate 1. Specifically, a second masking layer 3 is formed on the front surface of a semiconductor substrate 1, a first masking layer 2 is formed on the back surface of the semiconductor substrate 1, the second masking layer 3 is selectively removed to form a second isolation region, and the first masking layer 2 is selectively removed to form a first isolation region; the first isolation region is subjected to ion doping to form a first doped isolation region 4, a first isolation layer 6 is formed on the surface of the first doped isolation region 4, a second isolation layer 7 is formed on the surface of the second isolation region, the first masking layer 2 is removed, an anode region 8 and a drift ring region 9 are formed in the interval of the first doped isolation region 4, the second masking layer 3 is removed, and a collecting region 10 is formed in the interval of the second isolation region. The specific processes, parameters and steps are the same as those of S101A. The method for realizing selective removal may be a photolithography method, and of course, other methods may also be adopted as long as the method for realizing such a structure is included in the scope of protection of the present application.
By adopting the technical scheme of the above S101A, the first and second masking layers 2 and 3 are respectively deposited on the front and back surfaces of the semiconductor substrate 1, and the first and second isolation layers 6 and 7 are formed on the front and back surfaces of the semiconductor substrate 1 by an oxidation process with the first and second masking layers 2 and 3 as masks, so as to effectively protect the anode region 8, the drift ring region 9 and the collection region 10 from the influence of processes such as photolithography corrosion; simultaneously, after a first isolation region and a second isolation region are formed on a semiconductor substrate 1, ion doping is carried out on the first isolation region to form a first doping isolation region 4, an anode region 8 and a drift ring region 9 are formed in the interval of the first doping isolation region 4, a collecting region 10 is formed in the interval of the second isolation region, the ion doping type of the anode region 8 is the same as that of the first doping isolation region 4, the ion doping type of the drift ring region 9 and that of the collecting region 10 are opposite to that of the anode region 8, namely, the first doping isolation region 4 which is opposite to that of the drift ring region 9 is formed below a first isolation layer 6 in the interval of the drift ring region 9, so that the phenomenon that the accumulation of carriers which are the same as that of the drift ring region 9 under the influence of the metal lead voltage above the semiconductor substrate 1 below the first isolation layer 6 is avoided, and the leakage between the drift ring regions 9 is reduced, the preparation of the silicon drift detector with high breakdown voltage and low dark current is realized. The technical solution of S101B has the same technical effects, and will not be described again here.
S102: and respectively carrying out ion doping on the anode region 8, the drift ring region 9 and the collecting region 10, wherein the ion doping type of the anode region 8 is the same as that of the first doping isolation region 4, and the ion doping types of the drift ring region 9 and the collecting region 10 are opposite to that of the anode region 8.
Note that, as shown in fig. 8, the anode region 8 is ion-doped: and spin-coating photoresist on the surfaces of the anode region 8, the drift ring region 10 and the first isolation layer 6, and patterning the photoresist by using a photoetching process to define the anode region 8, namely removing the photoresist on the surface of the anode region 8. And (3) performing phosphorus ion implantation on the anode region 8 by taking the photoresist on the surfaces of the drift ring region 9 and the first isolation layer 6 as a mask to form N-type doping, or performing boron ion implantation to form P-type doping, preferably performing N-type doping on the anode region 8, and then removing the photoresist on the surfaces of the drift ring region 9 and the first isolation layer 6.
As shown in fig. 9, the drift ring region 9 is ion-doped: and spin-coating photoresist on the surfaces of the anode region 8, the drift ring region 9 and the first isolation layer 6, and patterning the photoresist by using a photoetching process to define the drift ring region 9, namely removing the photoresist on the surface of the drift ring region 9. And (3) taking the photoresist on the surfaces of the anode region 8 and the first isolation layer 6 as a mask, carrying out boron ion implantation on the drift ring region 9 to form P-type doping, or carrying out phosphorus ion implantation to form N-type doping, and then removing the photoresist on the surfaces of the anode region 8 and the first isolation layer 6. In particular, the drift ring region 9 has a different doping type than the anode region 8.
As shown in fig. 10, the collection region 10 is ion-doped: and spin-coating photoresist on the surfaces of the collection region 10 and the second isolation layer 7, and patterning the photoresist by using a photolithography process to define the collection region 10, namely removing the photoresist on the surface of the collection region 10. And (3) taking the photoresist on the surface of the second isolation layer 7 as a mask, carrying out boron ion implantation on the collection region 10 to form P-type doping, or carrying out phosphorus ion implantation to form N-type doping, and removing the photoresist on the surface of the second isolation layer 7. In particular, the doping type of the collection region 10 is the same as that of the drift ring region 9.
The doping of the anode region 8, the drift ring region 9 and the collection region 10 is not limited to a specific order. A photolithographic process may be used to pattern the photoresist to define the anode region 8, the drift ring region 9 and the collection region 10, although other methods may be used as long as the method for realizing such a structure is included in the scope of the present application.
S103: the semiconductor substrate 1 is subjected to annealing treatment.
The semiconductor substrate 1 is annealed at 700 to 1000 ℃, preferably, an N-type junction is formed in the anode region 8, a P-type junction is formed in the drift ring region 9 and the collection region 10, and the doping ions in the anode region 8, the drift ring region 9 and the collection region 10 are activated and the depth of the P-type junction or the N-type junction is controlled by the annealing.
S104: a dielectric layer 11 is formed on the surfaces of the anode region 8, the drift ring region 9 and the collection region 10.
As shown in fig. 11, a dielectric layer 11 is formed on the surfaces of the anode region 8, the drift ring region 9 and the collection region 10, and the dielectric layer 11 may be silicon oxide, aluminum oxide, silicon nitride material, preferably silicon oxide. Specifically, silicon oxide is deposited on the surfaces of the anode region 8, the drift ring region 9 and the collection region 10 after ion doping by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) Plasma-Enhanced Chemical Vapor Deposition (PECVD) mode to be used as a dielectric layer 11, and the thickness of the silicon oxide dielectric layer is 50nm to 200 nm.
S105: a contact hole penetrating the dielectric layer 11 in the thickness direction of the semiconductor substrate 1 is formed on the dielectric layer 11, and the contact hole is filled to form a metal lead 12.
As shown in fig. 12, a contact hole penetrating the dielectric layer 11 in the thickness direction of the semiconductor substrate 1 is formed in the dielectric layer 11, and any one of titanium, titanium nitride, aluminum, and aluminum nitride is filled in the contact hole, or any one of a stack of titanium/titanium nitride, titanium/titanium nitride/aluminum, and titanium/titanium nitride/aluminum nitride is sequentially filled, and preferably a stack of titanium/titanium nitride/aluminum nitride is sequentially filled. And a metal lead 12 is formed by patterning and etching through a photoetching process, and the metal lead 12 is mainly used for interconnecting a P-type junction or an N-type junction formed by ion doping in the anode region 8, the drift ring region 9 and the collecting region 10 with an external detection device.
Referring to fig. 13-14, the present invention also provides a drift detector comprising: the drift detector formed by any one of the above preparation methods, comprising: a semiconductor substrate 1; a P-type doped junction formed in the semiconductor substrate 1; an N-type doped junction formed in the semiconductor substrate 1; the metal electrode layer is positioned on the P-type doped junction and the N-type semiconductor junction; and the first isolation layer 6 and the second isolation layer 7 are positioned on the front surface or the back surface of the semiconductor substrate 1 and are used for isolating the P-type doped junction from the N-type doped junction.
The metal electrode layer comprises an anode region 8, a drift ring region 9 and a collecting region 10, wherein the anode region 8 and the drift ring region 9 are located on one surface of the semiconductor substrate 1 and are distributed from the center to the periphery in sequence, and the collecting region 10 is located on the other surface of the semiconductor substrate 1.
The drift ring region 9 and the collection region 10 have opposite doping types to those of the anode region 8.
The drift ring regions 9 are in separate annular structures, the rings are in circular, square, polygonal or irregular shapes to form separate drift rings, the anode region 8 is located in the center of the drift ring of the innermost ring, and the collecting regions 10 are in circular, square, polygonal or irregular shapes.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A preparation method of a drift detector is characterized by comprising the following steps:
providing a semiconductor substrate, forming a first masking layer on the front side of the semiconductor substrate, forming a second masking layer on the back side of the semiconductor substrate, selectively removing the first masking layer to form a first isolation region, and selectively removing the second masking layer to form a second isolation region; carrying out ion doping on the first isolation region to form a first doped isolation region, forming a first isolation layer on the surface of the first doped isolation region, and forming a second isolation layer on the surface of the second isolation region; removing the first masking layer, forming an anode region and a drift ring region in the interval of the first doped isolation region, removing the second masking layer, and forming a collecting region in the interval of the second isolation region;
or forming a second masking layer on the front side of the semiconductor substrate, forming a first masking layer on the back side of the semiconductor substrate, selectively removing the second masking layer to form a second isolation region, and selectively removing the first masking layer to form a first isolation region; carrying out ion doping on the first isolation region to form a first doped isolation region, forming a first isolation layer on the surface of the first doped isolation region, and forming a second isolation layer on the surface of the second isolation region; removing the first masking layer, forming an anode region and a drift ring region in the interval of the first doped isolation region, removing the second masking layer, and forming a collecting region in the interval of the second isolation region;
respectively carrying out ion doping on the anode region, the drift ring region and the collecting region, wherein the ion doping type of the anode region is the same as that of the first doping isolation region, and the ion doping types of the drift ring region and the collecting region are opposite to that of the anode region;
annealing the semiconductor substrate;
forming dielectric layers on the surfaces of the anode region, the drift ring region and the collecting region;
and forming a contact hole penetrating through the dielectric layer along the thickness direction of the semiconductor substrate on the dielectric layer, and filling the contact hole to form a metal lead.
2. The method of manufacturing a drift detector according to claim 1, further comprising:
and forming an oxide layer on the front surface and the back surface of the semiconductor substrate before forming the first masking layer and the second masking layer.
3. The method of claim 1, wherein the drift detector is fabricated by a method comprising,
the step of forming the first isolation region comprises: coating photoresist on the surface of the first masking layer; patterning the photoresist to define the first isolation region; removing the first masking layer on the surface of the first isolation region by adopting a dry etching process; removing the photoresist on the surface of the first masking layer;
the step of forming the second isolation region comprises: coating photoresist on the surface of the second masking layer;
patterning the photoresist to define the second isolation region; removing the second masking layer on the surface of the second isolation region by adopting a dry etching process; and removing the photoresist on the surface of the second masking layer.
4. The method of claim 1, wherein the step of ion doping the first isolation region to form a first doped isolation region comprises:
and performing phosphorus ion implantation on the surface of the first isolation region by using the first masking layer as a mask and adopting an ion implantation process to form N-type doping, or performing boron ion implantation to form P-type doping.
5. The method of fabricating a drift detector according to claim 1, wherein the step of forming said first and second isolation layers comprises:
and forming the first isolation layer and the second isolation layer by adopting an oxidation process.
6. The method of claim 1, wherein the step of removing the first mask layer to form the anode region and the drift ring region and the step of removing the second mask layer to form the collection region comprises:
and removing the first masking layer and the second masking layer by adopting a phosphoric acid wet etching process.
7. The method of claim 1, wherein ion doping the anode region comprises: coating photoresist on the surfaces of the anode region, the drift ring region and the first isolation layer, patterning the photoresist to define the anode region, performing phosphorus ion implantation on the anode region by taking the photoresist on the surfaces of the drift ring region and the first isolation layer as a mask to form N-type doping, or performing boron ion implantation to form P-type doping, and removing the photoresist on the surfaces of the drift ring region and the first isolation layer.
8. The method of claim 1, wherein ion doping the drift ring region comprises: coating photoresist on the surfaces of the anode region, the drift ring region and the first isolation layer, patterning the photoresist to define the drift ring region, performing boron ion implantation on the drift ring region by taking the photoresist on the surfaces of the anode region and the first isolation layer as a mask to form P-type doping, or performing phosphorus ion implantation to form N-type doping, and removing the photoresist on the surfaces of the anode region and the first isolation layer.
9. The method of claim 1, wherein ion doping the collection region comprises: coating photoresist on the surfaces of the collecting region and the second isolation layer, patterning the photoresist to define the collecting region, performing boron ion implantation on the collecting region by taking the photoresist on the surface of the second isolation layer as a mask to form P-type doping, or performing phosphorus ion implantation to form N-type doping, and removing the photoresist on the surface of the second isolation layer.
10. The method of claim 1, wherein annealing the semiconductor substrate comprises:
and carrying out annealing treatment on the semiconductor substrate at 700-1000 ℃.
11. The method for manufacturing the drift detector according to claim 1, wherein the step of forming the dielectric layer on the surfaces of the anode region, the drift ring region and the collection region comprises:
and forming dielectric layers on the surfaces of the anode region, the drift ring region and the collecting region by adopting a chemical vapor deposition process, wherein the thickness of the dielectric layers is 50-200 nanometers.
12. The method of claim 2, wherein the semiconductor substrate comprises an intrinsic semiconductor substrate or a lightly doped semiconductor substrate,
the oxide layer material comprises silicon oxide, and the thickness of the layer is 3-10 nanometers;
the first masking layer and the second masking layer comprise silicon nitride, and the thickness of the layer is 10-50 nanometers;
the materials of the first isolation layer and the second isolation layer comprise silicon oxide, and the layer thickness is 400-600 nanometers;
the dielectric layer material comprises silicon oxide or silicon nitride, and the thickness of the layer is 50-200 nm;
the metal lead comprises any one of titanium, titanium nitride, aluminum or aluminum nitride, or any one of a lamination layer composed of titanium/titanium nitride, titanium/titanium nitride/aluminum nitride.
13. A drift detector comprising the drift detector formed by the manufacturing method of any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911155931.8A CN110854223B (en) | 2019-11-22 | 2019-11-22 | Preparation method of drift detector and drift detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911155931.8A CN110854223B (en) | 2019-11-22 | 2019-11-22 | Preparation method of drift detector and drift detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110854223A true CN110854223A (en) | 2020-02-28 |
| CN110854223B CN110854223B (en) | 2021-04-06 |
Family
ID=69603714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911155931.8A Active CN110854223B (en) | 2019-11-22 | 2019-11-22 | Preparation method of drift detector and drift detector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110854223B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111668323A (en) * | 2020-06-15 | 2020-09-15 | 中国科学院微电子研究所 | Drift detector and processing method thereof |
| CN115020504A (en) * | 2022-04-28 | 2022-09-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing silicon detector |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020139970A1 (en) * | 2001-02-21 | 2002-10-03 | Jan Iwanczyk | Semiconductor radiation detector with internal gain |
| US20050173733A1 (en) * | 2002-03-27 | 2005-08-11 | Lothar Struder | Conductor crossover for a semiconductor detector |
| US20110192984A1 (en) * | 2010-02-09 | 2011-08-11 | Weinberg Medical Physics Llc | Method and equipment for producing drift detectors |
| US20130341520A1 (en) * | 2012-06-20 | 2013-12-26 | Pasi KOSTAMO | Leakage current collection structure and a radiation detector with the same |
| CN207572377U (en) * | 2017-08-22 | 2018-07-03 | 北京世纪金光半导体有限公司 | A kind of ultraviolet snowslide drifting detector of more drift ring structures |
| CN109671799A (en) * | 2018-12-21 | 2019-04-23 | 中国科学院微电子研究所 | Drifting detector and preparation method thereof |
| CN209016068U (en) * | 2018-10-26 | 2019-06-21 | 湘潭大学 | Based on a kind of silicon drifting detector (SDD) for controlling surface field |
-
2019
- 2019-11-22 CN CN201911155931.8A patent/CN110854223B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020139970A1 (en) * | 2001-02-21 | 2002-10-03 | Jan Iwanczyk | Semiconductor radiation detector with internal gain |
| US20050173733A1 (en) * | 2002-03-27 | 2005-08-11 | Lothar Struder | Conductor crossover for a semiconductor detector |
| US20110192984A1 (en) * | 2010-02-09 | 2011-08-11 | Weinberg Medical Physics Llc | Method and equipment for producing drift detectors |
| US20130341520A1 (en) * | 2012-06-20 | 2013-12-26 | Pasi KOSTAMO | Leakage current collection structure and a radiation detector with the same |
| CN103515468A (en) * | 2012-06-20 | 2014-01-15 | 牛津仪器分析公司 | Leakage current collection structure and radiation detector with the same |
| CN207572377U (en) * | 2017-08-22 | 2018-07-03 | 北京世纪金光半导体有限公司 | A kind of ultraviolet snowslide drifting detector of more drift ring structures |
| CN209016068U (en) * | 2018-10-26 | 2019-06-21 | 湘潭大学 | Based on a kind of silicon drifting detector (SDD) for controlling surface field |
| CN109671799A (en) * | 2018-12-21 | 2019-04-23 | 中国科学院微电子研究所 | Drifting detector and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| AUROLA, A ET AL: "Novel silicon drift detector design enabling low dark noise and simple manufacuturing", 《10TH INTERNATIONAL CONFERENCE ON POSITION SENSITIVE DETECTORS》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111668323A (en) * | 2020-06-15 | 2020-09-15 | 中国科学院微电子研究所 | Drift detector and processing method thereof |
| CN115020504A (en) * | 2022-04-28 | 2022-09-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing silicon detector |
| CN115020504B (en) * | 2022-04-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing silicon detector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110854223B (en) | 2021-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200212230A1 (en) | Leakage pathway layer for solar cell | |
| US8912038B2 (en) | Method of forming emitters for a back-contact solar cell | |
| CN110854223B (en) | Preparation method of drift detector and drift detector | |
| CN110854222B (en) | Double-sided preparation method of drift detector and drift detector | |
| JP6363335B2 (en) | Photoelectric device and method for manufacturing photoelectric device | |
| TW201532298A (en) | Solar cell emitter region fabrication using self-aligned implant and cap | |
| CN110176501A (en) | A kind of preparation method of MPS structure process silicon carbide diode | |
| CN114464667A (en) | Shielding gate trench MOSFET structure capable of optimizing terminal electric field and manufacturing method thereof | |
| CN111384154A (en) | Radiation-resistant bipolar device | |
| TWI491055B (en) | Solar cell and its manufacturing method | |
| CN113990547B (en) | Planar Pin type beta irradiation battery with gate electrode surface field and preparation method | |
| CN113871509B (en) | Double-groove type narrow-edge high-voltage-resistant silicon PIN radiation detector and preparation thereof | |
| CN211480035U (en) | Semiconductor device with a plurality of transistors | |
| CN113990548B (en) | Groove Pin type beta irradiation battery with gate electrode surface field and preparation method | |
| US20230253521A1 (en) | Solar cell manufacture | |
| JP2707555B2 (en) | Semiconductor radiation detector | |
| CN117637851A (en) | Single particle radiation resistant SiC UMOSFET device structure and manufacturing thereof | |
| CN107256885B (en) | High-reliability insulated gate bipolar transistor and manufacturing method thereof | |
| CN117012838A (en) | Drift detector and preparation method thereof | |
| CN109962106B (en) | MOSFET device and method of manufacturing the same | |
| CN116741632A (en) | Silicon carbide super junction schottky diode adopting channel injection and manufacturing method | |
| CN115312617A (en) | Ga 2 O 3 -2D metal type van der Waals heterojunction broadband polarization photoelectric detector and preparation method thereof | |
| KR20230050332A (en) | solar cell manufacturing | |
| CN113808924A (en) | Preparation method of semiconductor device | |
| CN113451216A (en) | Complete silicon-based anti-radiation high-voltage CMOS (complementary Metal oxide semiconductor) device integrated structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |