CN113808924A - Preparation method of semiconductor device - Google Patents

Preparation method of semiconductor device Download PDF

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Publication number
CN113808924A
CN113808924A CN202110993761.1A CN202110993761A CN113808924A CN 113808924 A CN113808924 A CN 113808924A CN 202110993761 A CN202110993761 A CN 202110993761A CN 113808924 A CN113808924 A CN 113808924A
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China
Prior art keywords
ion implantation
mask layer
epitaxial wafer
semiconductor device
sic epitaxial
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CN202110993761.1A
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Chinese (zh)
Inventor
万彩萍
田丽欣
桑玲
罗松威
许恒宇
叶甜春
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Institute of Microelectronics of CAS
Global Energy Interconnection Research Institute
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Institute of Microelectronics of CAS
Global Energy Interconnection Research Institute
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Priority to CN202110993761.1A priority Critical patent/CN113808924A/en
Publication of CN113808924A publication Critical patent/CN113808924A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a preparation method of a semiconductor device. A method of making a semiconductor device, comprising: providing a SiC epitaxial wafer with doping; forming a first mask layer on the SiC epitaxial wafer; carrying out graphical processing on the first mask layer to expose a first ion implantation area; performing ion implantation on the first ion implantation area, wherein the implantation type is the same as the doping type of the SiC epitaxial wafer; removing the first mask layer; forming a second mask layer on the SiC epitaxial wafer after removing the first mask layer; carrying out graphical processing on the second mask layer to expose a second ion implantation area; performing ion implantation to the second ion implantation region, wherein the implantation type is determined according to the type of an ion implantation structure in the semiconductor device; removing the second mask layer; activating the ions implanted in the second ion implantation area; and manufacturing other structures of the semiconductor device. The method aims to solve the problem that the charge is accumulated in the second injection edge region to break down in the avalanche breakdown process of the device.

Description

Preparation method of semiconductor device
Technical Field
The invention relates to the field of semiconductor production, in particular to a preparation method of a semiconductor device.
Background
The third-generation semiconductor material SiC has the advantages of larger forbidden band width, higher critical breakdown field strength, high thermal conductivity and the like; compared with silicon power devices under the same conditions, the silicon power device is more suitable for manufacturing high-voltage and high-power semiconductor devices, and is the core of the next generation of high-efficiency power electronic device technology. In addition, SiC can be oxidized by thermal oxidation to form silicon dioxide, which can be replicated or transferred to SiC by conventional silicon MOSFET processes, as opposed to other third generation semiconductors such as GaN. Therefore, SiC is considered as an important development direction of a new generation of high-performance power electronic devices, and has wide application prospects in the fields of new energy automobiles, rail transit, locomotive traction, smart power grids and the like.
However, due to the silicon carbide material itself and the silicon carbide device process, the reliability problem of the silicon carbide device has been troubled by the application manufacturers, and compared with the silicon device, the avalanche tolerance of the silicon carbide device is far less than that of the silicon device, which may cause the charge accumulation on the field plate or the injection edge area of the device during the use process of the device, resulting in the heat accumulation and the device failure.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a semiconductor device, which aims to solve the problem that the charge is accumulated in an injection edge area to cause avalanche breakdown under a high-voltage working environment.
In order to achieve the above object, the present invention provides the following technical solutions.
A method of making a semiconductor device, comprising:
providing a SiC epitaxial wafer with doping;
forming a first mask layer on the SiC epitaxial wafer;
carrying out graphical processing on the first mask layer to expose a first ion implantation area;
performing ion implantation on the first ion implantation area, wherein the implantation type is the same as the doping type of the SiC epitaxial wafer;
removing the first mask layer;
forming a second mask layer on the SiC epitaxial wafer after removing the first mask layer;
carrying out graphical processing on the second mask layer to expose a second ion implantation area;
performing ion implantation on the second ion implantation area, wherein the implantation type is determined according to the type of an ion implantation structure in the semiconductor device;
removing the second mask layer;
activating the ions implanted in the second ion implantation area;
and manufacturing other structures of the semiconductor device.
Compared with the prior art, the invention achieves the following technical effects:
before forming a diode cathode or anode, a triode source or drain plasma injection structure, elements which are consistent with epitaxial doping types are injected into an injection region part and a field plate edge region involved by a semiconductor device (such as a Schottky diode or a metal-oxide semiconductor field effect transistor) so as to form a thin high-concentration injection region below the device injection structure, so that device avalanche breakdown is caused to occur in the epitaxial layer as far as possible, but not in the injection edge regions of a device gate, an active region and the like, and finally the possibility that the device is broken down due to avalanche heat accumulation to cause device failure is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating preferred embodiments and are presented herein as an SBD device, but this is not to be construed as limiting the invention, which is also applicable to devices such as MOSFETs.
FIGS. 1 to 6 are structural topography maps obtained in the steps of manufacturing an SBD device according to the present invention;
fig. 7 is a flowchart of a method for manufacturing an SBD device according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Taking SBD as an example, the substrate is an N-doped or P-doped substrate, which is used as a drift region and is usually formed by an epitaxial process, and then an anode side composed of a field oxide, a P + guard ring region, a schottky contact region, etc. is formed above the substrate, and a cathode side is formed below the substrate. The P + protective ring region above the substrate belongs to an ion implantation structure, and the traditional preparation process is to directly perform ion implantation on the substrate epitaxy, so that the charge accumulation in the region is easily caused, and the reliability of the device is reduced.
In order to solve the problem, the present invention provides a method of manufacturing a semiconductor device having an ion-implanted structure.
Taking SBD as an example, as shown in fig. 7, the specific process includes the following steps.
Step S201: as shown in fig. 1, a SiC substrate 301 and a 4H-SiC material having a higher breakdown field strength and a higher carrier mobility are used as an epitaxial layer 302, which has N-type or P-type doping, exemplified as N-type in the figure. 4H-SiC can be replaced by epitaxial materials typical in the art, such as 3C-SiC or 6H-SiC.
Step S202: repairing epitaxial surface damage by sacrificial oxidation, and cleaning the 4H-SiC epitaxial wafer by a standard RCA cleaning method. The purpose of this step is to optimize the quality of the epitaxial layer and the sacrificial oxide layer may be formed in any manner, such as typical oxide growth. RCA cleaning solutions include, but are not limited to, solutions of SPM, HF, APM, HPM, and the like.
Step S203: and carrying out mask growth on the sample to form a first mask layer. The first mask layer may be a typical material such as silicon oxide, amorphous silicon, etc., which is easily deposited and easily removed. The first mask layer may have a single-layer structure or a multi-layer structure formed by stacking different materials, and the number of stacked layers is not limited, and may be two, three, four, or the like. For example, as shown in fig. 2, the four-layer structure is silicon dioxide/amorphous silicon/silicon dioxide/amorphous silicon from bottom to top, wherein the silicon oxide can be formed by a typical PECVD method, and the thickness of each layer is varied from 20nm to 3 μm. And then, performing a standard photolithography process to form a mask injection pattern 303 to obtain the structure shown in fig. 2, wherein the photolithography process includes HMDS, glue coating, exposure, and development, and the developing solution is acetone or developing solution. The exposed region after the photolithography is the first ion implantation region, which is located in the ion implantation structure regions to be manufactured subsequently, such as the source electrode, the drain electrode, the P + protective ring region, etc., and can be completely overlapped or partially overlapped with the ion implantation structure regions.
Step S204: as shown in fig. 3, an ion implantation process is performed in the first ion implantation region formed in step S203, the ion implantation type is the same as the doping type of the epitaxial layer, and the concentration is slightly higher than the doping concentration of the epitaxial layer, so as to form a doped region 304. The ion implantation of this step belongs to the high-temperature high-energy ion implantation technology, and the implantation depth is usually more than 0.8 μm.
Step S205: the mask implant pattern 303 is stripped and then cleaned. The stripping means includes but is not limited to dry etching and RCA cleaning, and the used equipment is a dry etching machine, a cleaning tank and the like. And then, carrying out ion implantation mask growth again to form a second mask layer. Similar to the first mask layer, the second mask layer may also be a single-layer structure or a multi-layer structure formed by stacking different materials, and the number of stacked layers is not limited, and may be two, three, four, or the like. For example, as shown in fig. 4, the four-layer structure is silicon dioxide/amorphous silicon/silicon dioxide/amorphous silicon from bottom to top, wherein the silicon oxide can be formed by a typical PECVD method, and the thickness of each layer is varied from 20nm to 3 μm. Then, a standard photolithography process is performed to form a mask implantation pattern 305, so as to obtain the topography shown in fig. 4; the implant pattern 305 is the area where the final ion implanted structure (source, drain, P + guard ring, etc.) is located.
Step S206: an ion implantation process is performed in the ion implantation region exposed in the previous step, the implantation element and concentration are determined according to the device structure, the implantation region is partially overlapped with the central region 304 to form an implantation region 306, the profile as shown in fig. 5 is obtained, and the implantation type and depth are also determined by the ion implantation structures of the source, the drain, the P + guard ring region, and the like.
Step S207: and performing other processes such as ion activation, metal electrode 307, field oxide 308 and the like to complete the fabrication of the device SBD, as shown in fig. 6.
The above embodiments of the present invention are illustrated with SBD, but the present invention is not limited to such devices, and devices in which the ion-implanted structure is formed on silicon carbide by using the method are suitable, such as typical MOSFET devices. According to the invention, before the source electrode or drain electrode plasma injection structure is formed, elements with the same type as the epitaxial doping are injected into the injection region part and the field plate edge region related to the semiconductor device, so that a thin high-concentration injection region is formed below the device injection structure, the device avalanche breakdown is caused in the epitaxial layer as far as possible instead of the edge region of the device gate, the active region and the like, the possibility of device failure caused by avalanche heat accumulation and breakdown is finally reduced, and the reliability of the device is improved.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a SiC epitaxial wafer with doping;
forming a first mask layer on the SiC epitaxial wafer;
carrying out graphical processing on the first mask layer to expose a first ion implantation area;
performing ion implantation on the first ion implantation area, wherein the implantation type is the same as the doping type of the SiC epitaxial wafer;
removing the first mask layer;
forming a second mask layer on the SiC epitaxial wafer after removing the first mask layer;
carrying out graphical processing on the second mask layer to expose a second ion implantation area;
performing ion implantation on the second ion implantation area, wherein the implantation type is determined according to the type of an ion implantation structure in the semiconductor device;
removing the second mask layer;
activating the ions implanted in the second ion implantation area;
and manufacturing other structures of the semiconductor device.
2. The preparation method according to claim 1, wherein the material of the SiC epitaxial wafer is N or P type 4H-SiC, 3C-SiC or 6H-SiC.
3. The method of claim 1, further comprising, prior to forming the first mask layer: and forming an oxidation sacrificial layer on the SiC epitaxial wafer, and removing the oxidation sacrificial layer by using an RCA method.
4. The method according to claim 1, wherein the first mask layer is a single layer structure formed of silicon oxide or polysilicon, or a stacked structure formed by alternately stacking silicon oxide and polysilicon.
5. The method according to claim 1, wherein the second mask layer is a single layer structure formed of silicon oxide or polysilicon, or a stacked structure formed by alternately stacking silicon oxide and polysilicon.
6. The production method according to claim 1, wherein, when ion implantation is performed into the first ion implantation region, the concentration of implantation is higher than the doping concentration of the SiC epitaxial wafer.
7. The method of any one of claims 1-6, wherein the semiconductor device is a Schottky diode or a metal-oxide semiconductor field effect transistor.
8. The method of claim 7, wherein the ion-implanted structure is a source or a drain.
9. The production method according to claim 1, wherein the first ion implantation region is ion-implanted to a depth > 0.8 μm.
10. The method of claim 1, wherein patterning the first mask layer comprises: a plurality of spaced apart mask pillars are formed.
CN202110993761.1A 2021-08-27 2021-08-27 Preparation method of semiconductor device Pending CN113808924A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237411A1 (en) * 2009-03-23 2010-09-23 Force Mos Technology Co. Ltd. LDMOS with double LDD and trenched drain
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
CN105990242A (en) * 2015-01-29 2016-10-05 无锡华润上华半导体有限公司 Preparation method of flat cell read only memory (ROM)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237411A1 (en) * 2009-03-23 2010-09-23 Force Mos Technology Co. Ltd. LDMOS with double LDD and trenched drain
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
CN105990242A (en) * 2015-01-29 2016-10-05 无锡华润上华半导体有限公司 Preparation method of flat cell read only memory (ROM)

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