CN110797267A - Bottom filling method with interconnection structure in flip chip packaging - Google Patents
Bottom filling method with interconnection structure in flip chip packaging Download PDFInfo
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- CN110797267A CN110797267A CN201911105268.0A CN201911105268A CN110797267A CN 110797267 A CN110797267 A CN 110797267A CN 201911105268 A CN201911105268 A CN 201911105268A CN 110797267 A CN110797267 A CN 110797267A
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- underfill
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
Abstract
The invention provides an underfill method with an interconnection structure in flip chip packaging, which comprises the steps of firstly placing underfill in a mold, baking and curing, and obtaining an underfill template after demolding; etching a through hole on the surface of the obtained bottom filler template to obtain a bottom filler prefabricated plate; depositing metal copper in the through hole of the bottom filler prefabricated plate to form the bottom filler prefabricated plate with the micro-convex points; and stacking the substrate, the bottom filler prefabricated plate with the micro-convex points and the chip in the sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding. The underfill method of the interconnection structure solves the problem of difficult underfill in high-density micro-bump packaging, namely solves the problem that underfill glue is difficult to fill gaps among micro-bumps of the whole chip in the traditional underfill technology, meets the development trend of taking high-density bump interconnection as a core in the three-dimensional integrated packaging technology, and has high reliability of the packaging structure.
Description
Technical Field
The invention relates to the field of packaging, in particular to an underfill method with an interconnection structure in flip chip packaging.
Background
The integrated circuit industry is an important industry of the country, and the integrated circuit products fully cover aspects of industrial production, research and development and daily life. With the rapid development of integrated circuits, products thereof tend to be more integrated, miniaturized, and highly densified. Under such circumstances, the development of three-dimensional integrated packaging technology with high-density bump interconnection as a core has become a necessary trend in the future packaging industry. The bumps play roles of mechanical support, electric signal paths and the like in three-dimensional integration and are one of important support technologies of the three-dimensional integration, but the size of the bumps is smaller and the pitch is smaller due to the sharp increase of the interconnection density. According to the international technical route organization prediction, the size of the three-dimensional integrated packaging interconnection structure micro salient point is reduced to one tenth of the existing size, and the technology has the advantages of high density, multiple functions, small size and the like. At present, the method is mainly applied to 2.5-dimensional and 3-dimensional packaging, such as high-performance graphics cards, multi-layer stacked storages, and the like.
The conventional underfill process includes applying a layer of flux to the substrate, aligning the solder bumps to the substrate pads, heating for reflow, removing the flux, injecting underfill along the chip edges, drawing in and flowing the underfill toward the center of the chip substrate by capillary action of the liquid, and heating to cure the underfill after it is filled. However, as the bump density of flip chips increases, it becomes more and more difficult for the underfill to fill the gap between the entire bumps, and the reliability of the chip becomes a serious challenge. Based on the above research on the conventional flip chip underfill and interconnect technology, it becomes critical to optimize the flip chip packaging process, especially the underfill technology under high density bumps.
Disclosure of Invention
The invention provides an underfill method with an interconnection structure in flip chip packaging, and aims to solve the problem of difficult underfill in high-density micro bump packaging and realize higher-density packaging.
In order to achieve the purpose, the invention provides the following technical scheme:
an underfill method with an interconnect structure in a flip chip package, comprising the steps of:
(1) preparation of prefabricated plate with bottom filler
Placing the underfill in a mold, baking and curing, demolding to obtain an underfill template, and etching through holes on the surface of the underfill template to obtain an underfill prefabricated plate;
(2) depositing micro-bumps
Depositing metal copper in the through hole of the prefabricated bottom filler plate obtained in the step (1) to form the prefabricated bottom filler plate with the micro-convex points;
(3) combined package
And (3) stacking the substrate, the prefabricated plate with the micro-convex points and the chip obtained in the step (2) in sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding.
Preferably, the diameter of the through holes in the step (1) is 15-30 μm, and the pitch of the through holes is 20-40 μm.
Preferably, the deposition method in step (2) includes physical vapor deposition, chemical vapor deposition, thermal evaporation deposition, electron beam evaporation deposition, electroplating deposition or electroless plating deposition.
Preferably, in the step (3), a bonding pad is arranged on the inner side of the chip and the inner side of the substrate, and the chip and the substrate are electrically connected with the micro bump through the bonding pad.
More preferably, the bonding pads are made of alloy materials, and the pitch of the bonding pads is 20-40 mu m.
More preferably, the ultrasonic thermocompression bonding in step (3) is to apply pressure, heat and ultrasonic energy to the chip, so that the upper end of the micro-bump of the underfill precast slab is embedded with the bonding pad on the inner side of the chip, and the lower end of the micro-bump is embedded with the bonding pad on the inner side of the substrate.
More preferably, the ultrasonic power of the ultrasonic hot-press welding is 2-5W, and the ultrasonic time is 100-300 ms.
Preferably, the temperature of the ultrasonic hot-press welding is 150-300 ℃, and the pressure is 5-10N.
Due to the small pitch and high density of the micro-bumps, the underfill is difficult to fill the whole lower chip, and the small pitch causes the residual air to be difficult to remove, which further causes the underfill to be difficult to fill the gaps between the micro-bumps, and leads to the reduction of the packaging reliability of the chip. Therefore, the invention provides a prefabricated solidified bottom filler substrate with holes, metal is deposited in the holes to form the interconnected micro-bumps, the interconnection positions of the interconnected micro-bumps are precisely aligned with a chip and a welding plate on the substrate, and the three-layer structure realizes the electrical connection between the chip and the substrate through ultrasonic hot-pressing welding to form a final packaging structure.
The scheme of the invention has the following beneficial effects:
(1) according to the underfill method of the interconnection structure, provided by the invention, the micro bumps are manufactured on the prefabricated underfill plate through a metal deposition process, so that the density of the micro bumps can be increased in turn, and higher-density packaging is realized.
(2) The underfill method of the interconnection structure provided by the invention is a technology without a flow filling process, and can greatly reduce the waste of underfill.
(3) The underfill method of the interconnection structure provided by the invention reduces the baking and curing process in the traditional underfill process, and avoids the influence of thermal stress generated in the process on the reliability of chip packaging.
(4) The underfill method of the interconnection structure can solve the problem of difficult underfill in high-density micro bump packaging, namely the problem that the underfill in the traditional underfill technology is difficult to fill the whole chip, and meets the development trend of taking high-density bump interconnection as a core in the three-dimensional integrated packaging technology.
Drawings
FIG. 1 is a top view of an underfill preform plate in accordance with the present invention;
FIG. 2 is a top view of a pre-cast sheet of micro-bumped underfill in accordance with the present invention;
FIG. 3 is a stacking sequence diagram of the "build-up packaging" process of the present invention;
fig. 4 is a diagram of a package structure of the present invention.
Description of the drawings: 1. prefabricating a slab; 2. a through hole; 3. micro-bumps; 4. a chip; 5. a pad; 6. a substrate.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description is given with reference to specific embodiments.
Example 1
The method can realize the flip chip underfill and interconnection under different bump pitches and sizes. For the convenience of measurement, the present embodiment will dispose daisy chain circuit on the substrate, and it is confirmed that the circuit interconnection between the chip and the substrate is realized, and the parameters selected in the present embodiment are bump diameter of 15 μm and pitch of 20 μm.
The filling manufacturing method comprises the following steps:
the first step is as follows: prefabricating a perforated baked and cured underfill substrate;
placing the bottom filler in a mold, baking and curing, demolding to obtain a bottom filler template, and etching through holes on the surface of the obtained bottom filler template to obtain a prefabricated plate with the diameter of 15 micrometers and the pitch of 20 micrometers; wherein, the bottom filling material template is determined according to the chip scale so as to enhance the packaging reliability.
The second step is that: depositing metal to form an interconnection micro bump;
and (3) depositing metal copper in the through hole of the prefabricated plate of the bottom filler obtained in the step (1) by using a chemical vapor deposition method to form the prefabricated plate of the bottom filler with the micro convex points.
The third step: combined package
And (3) stacking the substrate, the prefabricated plate with the micro-convex points and the chip obtained in the step (2) in sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding. Pads are arranged on the inner sides of the chip and the substrate, the pitch of the pads is 20 microns, and the pads are made of alloy materials capable of being subjected to eutectic welding in a eutectic welding mode, specifically in an evaporation mode; applying pressure, heat and ultrasonic energy to the chip by ultrasonic hot-press welding to enable the upper end of the micro-convex point of the underfill precast slab to be embedded with the bonding pad on the inner side of the chip and the lower end to be embedded with the bonding pad on the inner side of the substrate, and simultaneously destroying an oxide layer on a pressure welding interface, so that the attractive force generated among atoms achieves bonding, and the electrical connection between the chip and the substrate is realized; the ultrasonic thermal compression welding adopts the ultrasonic power of 3W, the ultrasonic time of 200ms, the temperature of 200 ℃ and the pressure of 7N.
Example 2
The method can realize the flip chip underfill and interconnection under different bump pitches and sizes. For the convenience of measurement, the present embodiment will dispose daisy chain circuit on the substrate, and it is confirmed that the circuit interconnection between the chip and the substrate is realized, and the parameters selected in the present embodiment are bump diameter of 20 μm and pitch of 30 μm.
The filling manufacturing method comprises the following steps:
the first step is as follows: prefabricating a perforated baked and cured underfill substrate;
placing the bottom filler in a mold, baking and curing, demolding to obtain a bottom filler template, and etching through holes on the surface of the obtained bottom filler template to obtain a prefabricated plate with the diameter of 20 micrometers and the pitch of 30 micrometers; wherein, the bottom filling material template is determined according to the chip scale so as to enhance the packaging reliability.
The second step is that: depositing metal to form an interconnection micro bump;
and (3) depositing metal copper in the through hole of the bottom filler precast slab obtained in the step (1) by using a thermal evaporation method to form the bottom filler precast slab with the micro convex points.
The third step: combined package
And (3) stacking the substrate, the prefabricated plate with the micro-convex points and the chip obtained in the step (2) in sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding. And pads are arranged on the inner sides of the chip and the substrate, and the pitch of the pads is 30 micrometers. The bonding pad is prepared from an alloy material capable of being subjected to eutectic welding in a mode of eutectic welding, particularly a magnetron sputtering mode; applying pressure, heat and ultrasonic energy to the chip by ultrasonic hot-press welding to enable the upper end of the micro-convex point of the underfill precast slab to be embedded with the bonding pad on the inner side of the chip and the lower end to be embedded with the bonding pad on the inner side of the substrate, and simultaneously destroying an oxide layer on a pressure welding interface, so that the attractive force generated among atoms achieves bonding, and the electrical connection between the chip and the substrate is realized; the ultrasonic hot-press welding adopts the ultrasonic power of 5W, the ultrasonic time of 100ms, the temperature of 150 ℃ and the pressure of 10N.
Example 3
The method can realize the flip chip underfill and interconnection under different bump pitches and sizes. For the convenience of measurement, the present embodiment will dispose daisy chain circuit on the substrate, and it is confirmed that the circuit interconnection between the chip and the substrate is realized, and the parameters selected in the present embodiment are bump diameter of 30 μm and pitch of 40 μm.
The filling manufacturing method comprises the following steps:
the first step is as follows: prefabricating a perforated baked and cured underfill substrate;
placing the bottom filler in a mold, baking and curing, demolding to obtain a bottom filler template, and etching through holes on the surface of the obtained bottom filler template to obtain a prefabricated plate with the diameter of 30 micrometers and the pitch of 40 micrometers; (ii) a Wherein, the bottom filling material template is determined according to the chip scale so as to enhance the packaging reliability.
The second step is that: depositing metal to form an interconnection micro bump;
and (3) depositing metal copper in the through hole of the bottom filler precast slab obtained in the step (1) by using a thermal evaporation method to form the bottom filler precast slab with the micro convex points.
The third step: combined package
And (3) stacking the substrate, the prefabricated plate with the micro-convex points and the chip obtained in the step (2) in sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding. Pads are arranged on the inner sides of the chip and the substrate, the pitch of the pads is 40 mu m, and the pads are prepared from alloy materials capable of being subjected to eutectic welding in a eutectic welding mode, specifically an electroplating mode; and applying pressure, heat and ultrasonic energy to the chip by ultrasonic thermocompression welding to enable the upper end of the micro-convex point of the underfill precast slab to be embedded with the bonding pad on the inner side of the chip and the lower end to be embedded with the bonding pad on the inner side of the substrate, and simultaneously destroying an oxide layer on a pressure welding interface, so that the attractive force generated among atoms achieves bonding, and the electrical connection between the chip and the substrate is realized. The ultrasonic thermal compression welding adopts 2W of ultrasonic power, 300ms of ultrasonic time, 300 ℃ of temperature and 5N of pressure.
The packaging structures obtained by the three embodiments are confirmed to be connected with the circuit between the substrate by using an ammeter, and the filling effect of the underfill after polishing and grinding is good through electron microscope observation.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. An underfill method with an interconnect structure in a flip chip package, comprising the steps of:
(1) preparation of prefabricated plate with bottom filler
Placing the underfill in a mold, baking and curing, demolding to obtain an underfill template, and etching through holes on the surface of the underfill template to obtain an underfill prefabricated plate;
(2) depositing micro-bumps
Depositing metal copper in the through hole of the prefabricated bottom filler plate obtained in the step (1) to form the prefabricated bottom filler plate with the micro-convex points;
(3) combined package
And (3) stacking the substrate, the prefabricated plate with the micro-convex points and the chip obtained in the step (2) in sequence from bottom to top, and realizing the electrical connection between the chip and the substrate by ultrasonic hot-press welding.
2. The method according to claim 1, wherein the diameter of the through holes in step (1) is 15 to 30 μm, and the pitch of the through holes is 20 to 40 μm.
3. The method of claim 1, wherein the deposition method in step (2) comprises physical vapor deposition, chemical vapor deposition, thermal evaporation deposition, electron beam evaporation deposition, electroplating deposition, or electroless deposition.
4. The method of claim 1, wherein in step (3), the chip and the substrate are provided with bonding pads on the inner sides thereof, and the chip and the substrate are electrically connected with the micro bumps through the bonding pads.
5. The chip package underfill method with an interconnect structure according to claim 4, wherein the pads are made of an alloy material, and a pad pitch is 20-40 μm.
6. The method as claimed in claim 4 or 5, wherein the step (3) of ultrasonic thermocompression bonding is implemented by applying pressure, heat and ultrasonic energy to the chip, so that the upper ends of the micro-bumps of the underfill precast slab are embedded with the bonding pads on the inner side of the chip, and the lower ends of the micro-bumps are embedded with the bonding pads on the inner side of the substrate.
7. The method according to claim 6, wherein the ultrasonic thermocompression bonding is performed at an ultrasonic power of 2-5W for an ultrasonic time of 100-300 ms.
8. The method according to claim 6, wherein the ultrasonic thermocompression bonding is performed at a temperature of 150 to 300 ℃ and a pressure of 5 to 10N.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911105268.0A CN110797267A (en) | 2019-11-12 | 2019-11-12 | Bottom filling method with interconnection structure in flip chip packaging |
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| CN201911105268.0A CN110797267A (en) | 2019-11-12 | 2019-11-12 | Bottom filling method with interconnection structure in flip chip packaging |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113495189A (en) * | 2021-09-08 | 2021-10-12 | 深圳荣耀智能机器有限公司 | Test method for evaluating reliability of electronic assembly material |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1487579A (en) * | 2002-08-20 | 2004-04-07 | 印芬龙科技股份有限公司 | Microelectronic technology and structure |
| CN2829091Y (en) * | 2005-04-25 | 2006-10-18 | 威盛电子股份有限公司 | Flip-chip package structure |
| US20110237030A1 (en) * | 2010-03-25 | 2011-09-29 | International Business Machines Corporation | Die level integrated interconnect decal manufacturing method and apparatus |
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- 2019-11-12 CN CN201911105268.0A patent/CN110797267A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1487579A (en) * | 2002-08-20 | 2004-04-07 | 印芬龙科技股份有限公司 | Microelectronic technology and structure |
| CN2829091Y (en) * | 2005-04-25 | 2006-10-18 | 威盛电子股份有限公司 | Flip-chip package structure |
| US20110237030A1 (en) * | 2010-03-25 | 2011-09-29 | International Business Machines Corporation | Die level integrated interconnect decal manufacturing method and apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113495189A (en) * | 2021-09-08 | 2021-10-12 | 深圳荣耀智能机器有限公司 | Test method for evaluating reliability of electronic assembly material |
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Application publication date: 20200214 |