CN111446177A - System-level packaging method and structure of heterogeneous integrated chip - Google Patents

System-level packaging method and structure of heterogeneous integrated chip Download PDF

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Publication number
CN111446177A
CN111446177A CN202010284339.4A CN202010284339A CN111446177A CN 111446177 A CN111446177 A CN 111446177A CN 202010284339 A CN202010284339 A CN 202010284339A CN 111446177 A CN111446177 A CN 111446177A
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layer
chip
heterogeneous
integrated
chips
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徐成
曹立强
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Priority to CN202010284339.4A priority Critical patent/CN111446177A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a system-level packaging method and a system-level packaging structure of a heterogeneous integrated chip, which comprise the following steps: adhering the bottom surfaces of the substrate chips to the chip carrier to form a first integrated adapter plate; forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic package layer form a first plastic package body; carrying out mechanical or chemical polishing process on the top of the first plastic package body to expose the electric leading-out parts of the substrate chips; manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the substrate chips, wherein the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips; interconnecting a plurality of said heterogeneous chips to said first integrated interposer to form a second integrated interposer; performing a mechanical or chemical polishing process on the top of the second integrated interposer to make the absolute heights of the heterogeneous chips the same; and removing the first plastic package body from the slide sheet.

Description

System-level packaging method and structure of heterogeneous integrated chip
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a system-level packaging method and a system-level packaging structure of a heterogeneous integrated chip.
Background
With the various new application fields of semiconductors such as 5G, Artificial Intelligence (AI), automotive electronics, internet of things (IoT) and High Performance Computing (HPC), the advanced manufacturing processes of wafers are moving to 7, 5 and 3nm, but as moore's law gradually approaches physical limits, one of the good parties for prolonging the life of moore's law is the advanced packaging technology, including fan-out wafer level packaging (FOW L P) and 2.5D/3DIC packaging, and further entering 3D wafer stack packaging capable of heterogeneous integration.
The Through Silicon Via (TSV) technology realizes vertical interconnection between the die and the die, and through holes are formed in the Si for interconnection between the chips, so that wire bonding is not needed, the length of an interconnection wire is effectively shortened, signal transmission delay and loss are reduced, the signal speed and bandwidth are improved, the power consumption and the packaging volume are reduced, and the multi-functional, high-performance, high-reliability, lighter, thinner and smaller chip system-level packaging is realized. Because the 3D TSV packaging process is not mature in design, volume production, testing, and supply chain, and the process cost is high, the current industry adopts a 2.5D connection layer packaging form before 2D and 3D, and the input/output (I/O) signal density of the package is greatly improved by adding a connection layer between the die and the substrate.
Under the condition that the size of a welding spot gradually becomes 3-5 mu m, the system-level integrated packaging of heterogeneous chips including chips with different functions, different generations, different packaging forms and the like becomes an effective solution for the application problem of the emerging semiconductor industry. The traditional integration mode can not unify chips with various heterogeneous concepts in the same packaging body, different functions or combined application of chips are often realized through a PCB, the approach has obvious limiting effect on space occupation and integration level improvement of the packaging body, and various factors influencing chip performance such as parasitic capacitance, inductance and the like are easily generated in packaging, so that signal transmission is not facilitated. In summary, the prior art has not been able to realize heterogeneous integration of chips in all package formats.
Disclosure of Invention
The invention aims to provide a system-in-package method and a system-in-package structure of a heterogeneous integrated chip, which aim to solve the problem that the existing heterogeneous chip cannot be integrated and packaged.
In order to solve the above technical problem, the present invention provides a system-in-package method for a heterogeneous integrated chip, including:
adhering the bottom surfaces of the substrate chips to the chip carrier to form a first integrated adapter plate;
forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic package layer form a first plastic package body;
carrying out mechanical or chemical polishing process on the top of the first plastic package body to expose the electric leading-out parts of the substrate chips;
manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the substrate chips, wherein the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;
interconnecting a plurality of said heterogeneous chips to said first integrated interposer to form a second integrated interposer;
performing a mechanical or chemical polishing process on the top of the second integrated interposer to make the absolute heights of the heterogeneous chips the same;
and removing the first plastic package body from the slide sheet.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the step of performing a mechanical polishing process on the top of the second integrated interposer includes:
forming a second plastic package layer on the second integrated adapter plate, wherein the heterogeneous chip and the second plastic package layer form a second plastic package body;
and carrying out mechanical or chemical polishing process on the top of the second plastic package body so as to enable the top of the second plastic package body to be flat and smooth.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the forming the first molding compound layer or the second molding compound layer includes:
forming the first plastic packaging layer or the second plastic packaging layer by adopting a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process or a spin coating process;
the first plastic packaging layer or the second plastic packaging layer is made of one of polyimide, silica gel and epoxy resin.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the fabricating the metal interconnection layer and the dielectric layer on the top of the plurality of substrate chips includes:
depositing a deposition layer on the top surface of the substrate chip by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the deposition layer to form a patterned dielectric layer;
forming a metal interconnection layer on the surface of the dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal interconnection layer for patterning;
and leading the electrical property of the electrical lead-out part of the substrate chip out to the pins of the heterogeneous chip by the metal interconnection layer.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the metal interconnection layer includes a wiring layer or a metal conductive bump which is rearranged on a front surface, the electrical lead-out portion is electrically connected to the heterogeneous chip, and the heterogeneous chip is disposed on the metal conductive bump by flip-chip bonding.
Optionally, in the system-in-package method for a heterogeneous integrated chip, the substrate chip further includes:
the conductive through hole is arranged in the substrate chip and electrically connected with the electric leading-out part;
the back metal layer is electrically connected with the conductive through hole to realize the electrical connection with the electrical lead-out part;
and the external solder balls are arranged on the external bonding pads of the back metal layer.
Optionally, in the system-in-package method for the heterogeneous integrated chip, an underfill layer is formed between the heterogeneous chip and the substrate chip.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the carrier sheet has an adhesive film, and the adhesive film is made of a bonding film.
Optionally, in the system-in-package method for the heterogeneous integrated chip, the thickness of the first integrated interposer is 50 to 200 microns, and the thickness of the second integrated interposer is 100 to 300 microns.
The invention also provides a system-in-package structure of the heterogeneous integrated chip, which comprises the following components:
a plurality of substrate chips;
the first plastic packaging layer covers the top of the substrate chip and the top of the slide glass;
a plurality of electrical leads of the substrate chips exposed on top of the first molding layer;
the metal interconnection layer and the dielectric layer are positioned at the top of the first plastic package layer, and the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;
and the heterogeneous chips are positioned on the tops of the metal interconnection layer and the dielectric layer and are electrically connected with the metal interconnection layer and the dielectric layer, and the absolute heights of the heterogeneous chips are the same.
In the system-in-package method and the system-in-package structure of the heterogeneous integrated chips, the plurality of heterogeneous chips are welded on the first integrated adapter plate and polished, so that the absolute heights of the plurality of heterogeneous chips are the same, the integration requirements of the heterogeneous chips are met, and the problem that the subsequent assembly is influenced due to the inconsistent thickness of the heterogeneous chips is solved.
Furthermore, a plurality of silicon substrate chips are adhered to the wafer to form a first integrated adapter plate, and a first plastic packaging layer is formed on the first integrated adapter plate and polished, so that the silicon substrate with good test performance is used for packaging, and the cost is reduced.
Furthermore, the wafer plastic package is carried out on the first integrated adapter plate to form a reconstructed wafer, so that subsequent chip mounting, holding and chip thinning are facilitated, and the production efficiency is improved; in addition, interconnection of different systems is realized based on different adapter plates, transmission efficiency is improved, and performance is improved.
The wafer plastic packaging process and the wafer tape-out process are separated, the influence of the warping of the plastic packaged wafer on the packaging previous process is avoided, the temporary bonding and bonding detaching processes are not needed, the process difficulty is reduced, and the process cost is reduced.
Drawings
FIGS. 1-10 are schematic diagrams illustrating a system-in-package method of a heterogeneous integrated chip according to an embodiment of the invention;
shown in the figure: 10-silicon substrate chip; 11-an electrical lead-out; 12-conductive through-silicon vias; 13-external connection of a solder ball; 20-carrying a sheet; 21-glue film; 30-a first plastic packaging layer; 40-metal interconnection layer and dielectric layer; 50-heterogeneous chip; 51-bottom glue filling layer; 52-small micro-bumps; 60-a second plastic packaging layer; 101-a first integrated interposer; 102-a first plastic package body; 103-a second integrated interposer; 104-second plastic package body.
Detailed Description
The system-level packaging method and structure of the heterogeneous integrated chip proposed by the present invention are further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is to provide a system-in-package method and structure of a heterogeneous integrated chip, so as to solve the problem that the existing heterogeneous chip can not be integrated and packaged.
In order to realize the idea, the invention provides a system-in-package method and a structure of a heterogeneous integrated chip, wherein the system-in-package method of the heterogeneous integrated chip comprises the following steps: adhering the bottom surfaces of a plurality of substrate chips to the slide to form a first integrated adapter plate; forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic package layer form a first plastic package body; carrying out mechanical or chemical polishing process on the top of the first plastic package body to expose the electric leading-out parts of the substrate chips; manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the substrate chips, wherein the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips; interconnecting a plurality of the heterogeneous chips to the first integrated interposer to form a second integrated interposer; performing a mechanical or chemical polishing process on the top of the second integrated interposer to make the absolute heights of the heterogeneous chips the same; and removing the first plastic package body from the slide sheet.
< example one >
The present embodiment provides a system-in-package method for a heterogeneous integrated chip, as shown in fig. 1 to 10, the system-in-package method for the heterogeneous integrated chip includes: manufacturing a plurality of silicon substrate chips 10; a plurality of silicon substrate chips 10 are back to a carrier 20 and are centrally adhered to the carrier 20 to form a first integrated adapter plate 101; as shown in fig. 2, a first plastic package layer 30 is formed on the first integrated interposer 101, and the silicon substrate chip 10 and the first plastic package layer 30 form a first plastic package body 102; as shown in fig. 3, a mechanical or chemical polishing process is performed on the top of the first molding compound 102 to expose a plurality of electrical leads 11 of the silicon substrate chip 10; as shown in fig. 4, a metal interconnection layer and a dielectric layer 40 are formed on top of the silicon substrate chips 10, and the metal interconnection layer is electrically connected to the electrical lead-out portions 11 of the silicon substrate chips 10; as shown in fig. 5, a plurality of heterogeneous chips 50 are provided; interconnecting a plurality of said foreign chips 50 to said first integrated interposer 101, forming a second integrated interposer 103; as shown in fig. 6, a mechanical or chemical polishing process is performed on the top of the second integrated interposer 103 to make the absolute heights of the plurality of heterogeneous chips 50 the same; as shown in fig. 7, the first molding compound 102 is removed from the slide 20.
In an embodiment of the present invention, as shown in fig. 8 to 9, in the system-in-package method for a heterogeneous integrated chip, the mechanical polishing process performed on the top of the second integrated interposer 103 includes: forming a second plastic package layer 60 on the second integrated interposer 103, wherein the heterogeneous chip 50 and the second plastic package layer 60 form a second plastic package body 104; performing a mechanical or chemical polishing process on the top of the second plastic package body 104 to make the top of the second plastic package body 104 flat and smooth, wherein the purpose of the process is to achieve the same absolute height of the heterogeneous chips 50; after the first plastic package body 102 is removed from the carrier sheet 20, the system-in-package structure of the heterogeneous integrated chip is shown in fig. 10.
In another embodiment of the present invention, in the system-in-package method of the hetero-integrated chip, the forming the first molding compound layer 30 or the second molding compound layer 60 includes: forming the first molding layer 30 or the second molding layer 60 using a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process, or a spin coating process; the material of the first molding compound layer 30 or the second molding compound layer 60 includes one of polyimide, silicone, epoxy resin, and the like.
In an embodiment of the present invention, in the system-in-package method of the hetero-integrated chip, the fabricating the metal interconnection layer and the dielectric layer 40 on top of the silicon substrate chips 10 includes: depositing a deposition layer on the top surface of the silicon substrate chip 10 by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the deposition layer to form a patterned dielectric layer; forming a metal interconnection layer on the surface of the dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal interconnection layer for patterning; the metal interconnection layer leads the electrical property of the electrical lead-out portion 11 of the silicon substrate chip 10 to the lead of the foreign chip 50.
In other embodiments of the present invention, in the system-in-package method of the heterogeneous integrated chip, the metal interconnection layer includes a front-side redistribution wiring layer or a metal conductive bump, the electrical lead-out portion 11 electrically connects the heterogeneous chip 50, and the heterogeneous chip 50 is disposed on the metal conductive bump by flip-chip bonding. In the system-in-package method for the heterogeneous integrated chip, the silicon substrate chip 10 further includes: a conductive through-silicon via 12, the conductive through-silicon via 12 being disposed through the silicon substrate chip 10, the conductive through-silicon via 12 being electrically connected to the electrical lead-out 11; the back metal layer is electrically connected with the conductive silicon through hole 12 to realize the electrical connection with the electrical lead-out part 11; and the external solder balls 13 are arranged on the external bonding pads of the back metal layer, and the external solder balls 13 are arranged on the external bonding pads of the back metal layer. In the above embodiments, the silicon substrate chip 10 is used for illustration, but it will be understood by those skilled in the art that the substrate chip 10 may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate chip 10 may also be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.
In addition, in the system-in-package method of the hetero-integrated chip, an underfill layer 51 is formed between the hetero-chip 50 and the silicon substrate chip 10. In the system-in-package method of the heterogeneous integrated chip, the carrier 20 has an adhesive film 21 thereon, and the adhesive film 21 may be a bonding film. In the system-in-package method of the heterogeneous integrated chip, the thickness of the first integrated interposer 101 is 50 to 200 microns, and the thickness of the second integrated interposer 103 is 100 to 300 microns.
In the system-in-package method and structure of the heterogeneous integrated chip provided by the invention, the plurality of heterogeneous chips 50 are welded on the first integrated interposer 101 and polished, so that the absolute heights of the plurality of heterogeneous chips 50 are the same, the integration requirement of the heterogeneous chips 50 is met, and the problem that the thickness of the heterogeneous chips 50 is inconsistent and the subsequent assembly is influenced is solved.
Further, the silicon substrate with good test performance is used for packaging and the cost is reduced by adhering the silicon substrate chips 10 to the carrier 20 to form the first integrated adapter plate 101, and forming the first plastic package layer 30 on the first integrated adapter plate 101 and polishing.
Furthermore, the wafer plastic package is carried out on the first integrated adapter plate 101 to form a reconstructed wafer, so that subsequent chip mounting, holding and chip thinning are facilitated, and the production efficiency is improved; in addition, interconnection of different systems is realized based on different adapter plates, transmission efficiency is improved, and performance is improved.
The wafer plastic packaging process and the wafer tape-out process are separated, the influence of the warping of the plastic packaged wafer on the packaging previous process is avoided, the temporary bonding and bonding detaching processes are not needed, the process difficulty is reduced, and the process cost is reduced.
In summary, the embodiments described above describe in detail different schemes of the system-in-package method for the heterogeneous integrated chip, and it is understood that the present invention includes but is not limited to the configurations listed in the above embodiments, and any modifications based on the configurations provided by the above embodiments are within the scope of the present invention. One skilled in the art can take the contents of the above embodiments to take a counter-measure.
< example two >
The present embodiment further provides a system-in-package structure of a heterogeneous integrated chip, as shown in fig. 7, including: a plurality of silicon substrate chips 10; the first plastic package layer 30, the first plastic package layer 30 covers the tops of the silicon substrate chip 10 and the slide glass 20; a plurality of electrical lead-out portions 11 of the silicon substrate chip 10 exposed to the top of the first molding compound layer 30; a metal interconnection layer and dielectric layer 40 located on top of the first plastic package layer 30, the metal interconnection layer being electrically connected to the electrical leads 11 of the plurality of silicon substrate chips 10; and the heterogeneous chips 50 are positioned at the tops of the metal interconnection layers and the dielectric layers 40 and are electrically connected with the metal interconnection layers and the dielectric layers 40, and the absolute heights of the heterogeneous chips 50 are the same. In another embodiment of the present invention, as shown in fig. 10, the system-in-package structure of the heterogeneous integrated chip may further include a second package layer 60.
The embodiment of the invention provides a system-in-package structure of a heterogeneous integrated chip, which comprises the following components: the chip comprises a silicon substrate chip 10, wherein a plurality of conductive through silicon vias 12 are formed in the silicon substrate chip 10, and a plurality of external solder balls 13 are arranged at the bottom of the silicon substrate chip 10; the heterogeneous chip 50 is provided with a plurality of small micro-bumps 52 at the bottom of the heterogeneous chip 50, the heterogeneous chip 50 is fixedly mounted on the silicon substrate chip 10 through the small micro-bumps 52, and the heterogeneous chip 50 is electrically connected with the silicon substrate chip 10 through the small micro-bumps 52; the heterogeneous chip 50 may include a 3D-IC chip, the 3D-IC chip is flip-chip bonded to the silicon substrate chip 10 through the micro bumps and the conductive through silicon vias 12, and the 3D-IC chip is electrically connected to the silicon substrate chip 10 through the micro bumps and the conductive through silicon vias 12.
In the system-in-package structure of the heterogeneous integrated chip according to the embodiment of the present invention, the silicon substrate chip 10 is used for carrying various chips, and the conductive circuit is disposed on the silicon substrate chip 10 to electrically connect the heterogeneous chips with each other; the silicon substrate chip 10 is mounted on the carrier plate 20 through the external solder balls 13 in an adhering manner, a plurality of the conductive through silicon vias 12 are disposed on the silicon substrate chip 10, the conductive through silicon vias 12 penetrate from the upper surface to the lower surface of the silicon substrate chip 10, and the conductive through silicon vias 12 can conduct electricity, so that the heterogeneous chip 50 mounted on the silicon substrate chip 10 in a flip-chip manner by using the small micro bumps 52 can be electrically connected with the silicon substrate chip 10 through the conductivity of the small micro bumps 52 and the conductive through silicon vias 12, and meanwhile, the heterogeneous chip 50 is a more advanced bump chip with a diameter of 3-5 μm; the 3D-IC chip is electrically and mechanically connected with the silicon substrate chip 10 through the micro-bumps and the conductive through silicon vias 12; this section can be considered a COWOS package, with the difference that the 3D-IC chip inside is co-packaged with the 3-5 μm hetero-chip 50, which is next generation more advanced, onto the silicon substrate chip 10.
The silicon substrate chip can be further provided with a lead bonding chip, the bottom of the lead bonding chip 9 is coated with a TIM material, and the lead bonding chip is bonded and mounted with the silicon substrate chip through the TIM material.
And a lead bonding wire is arranged on the lead bonding chip, and the lead bonding chip is electrically connected with the silicon substrate chip through the lead bonding wire.
In the system-in-package structure of the hetero-integrated chip according to the embodiment of the present invention, the bottom of the wire bonding chip is bonded to the silicon substrate chip through the TIM material, and the wire bonding wire connects the wire bonding chip and the silicon substrate chip, so that the wire bonding chip can be electrically connected to the silicon substrate chip; meanwhile, the TIM material is arranged at the bottom of the wire bonding chip, so that the bottom of the wire bonding chip has better heat dissipation performance.
The silicon substrate chip can be further provided with a flip chip, the flip chip is mounted on the silicon substrate chip in a flip bonding mode through the micro bumps, and the flip chip is electrically connected with the silicon substrate chip through the micro bumps.
In the system-in-package structure of the heterogeneous integrated chip according to the embodiment of the present invention, the silicon substrate chip 10 may further include the flip chip, where the flip chip is a lower-generation chip such as MEMS, RFIC, and the like; the flip chip is electrically connected with the silicon substrate chip through the micro bumps, so that the flip chip can be electrically connected with other chips through the micro bumps and the silicon substrate chip.
And a passive device is mounted on the silicon substrate chip and electrically connected with the silicon substrate chip 10.
In the system-in-package structure of the heterogeneous integrated chip according to the embodiment of the present invention, the passive device may be further mounted on the silicon substrate chip, so that effective integration of various components is realized on the silicon substrate chip, and the functional integration level is improved.
In the system-in-package structure of the hetero-integrated chip according to the embodiment of the present invention, the bottom of the silicon substrate chip is welded and fixed to the PCB board through the external solder balls, and the PCB board is used for bearing the whole package structure.
In the system-in-package structure of the heterogeneous integrated chip according to the embodiment of the present invention, the external solder balls 13, the micro bumps, the small micro bumps 52, the conductive through-silicon vias 12, and the silicon substrate chip 10 are used to implement unified packaging of chips with different functions, chips with different generations, chips with different packaging types, and chips with different dimensions, and the other passive devices 13 are further mounted on the silicon substrate chip, so that the integration level of functions is effectively improved, the occupied space of the chips on the PCB is reduced, and the unified packaging of different chips is beneficial to saving of processing procedures, so that the packaging efficiency is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications and variations of the present invention will be made by those skilled in the art in light of the above disclosure and fall within the scope of the appended claims.

Claims (10)

1. A system-in-package method of a heterogeneous integrated chip is characterized by comprising the following steps:
adhering the bottom surfaces of the substrate chips to the chip carrier to form a first integrated adapter plate;
forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic package layer form a first plastic package body;
carrying out mechanical or chemical polishing process on the top of the first plastic package body to expose the electric leading-out parts of the substrate chips;
manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the substrate chips, wherein the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;
interconnecting a plurality of said heterogeneous chips to said first integrated interposer to form a second integrated interposer;
performing a mechanical or chemical polishing process on the top of the second integrated interposer to make the absolute heights of the heterogeneous chips the same;
and removing the first plastic package body from the slide sheet.
2. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein the mechanical polishing process on the top of the second integrated interposer comprises:
forming a second plastic package layer on the second integrated adapter plate, wherein the heterogeneous chip and the second plastic package layer form a second plastic package body;
and carrying out mechanical or chemical polishing process on the top of the second plastic package body so as to enable the top of the second plastic package body to be flat and smooth.
3. The system-in-package method of a heterogeneous integrated chip according to claim 2, wherein forming the first molding compound layer or the second molding compound layer comprises:
forming the first plastic packaging layer or the second plastic packaging layer by adopting a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process or a spin coating process;
the first plastic package layer or the second plastic package layer is made of one of polyimide, silica gel and epoxy resin.
4. The system-in-package method of a hetero-integrated chip according to claim 1, wherein the fabricating of the metal interconnection layer and the dielectric layer on top of the plurality of substrate chips comprises:
depositing a deposition layer on the top surface of the substrate chip by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the deposition layer to form a patterned dielectric layer;
forming a metal interconnection layer on the surface of the dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal interconnection layer for patterning;
and leading the electrical property of the electrical lead-out part of the substrate chip out to the pins of the heterogeneous chip by the metal interconnection layer.
5. The system-in-package method of a hetero-integrated chip according to claim 4, wherein the metal interconnection layer comprises a front-side redistribution wiring layer or a metal conductive bump, the electrical lead-out portion electrically connects the hetero-chip, and the hetero-chip is disposed on the metal conductive bump by flip-chip bonding.
6. The system-in-package method of a heterogeneous integrated chip according to claim 5, wherein the substrate chip further comprises:
the conductive through hole is arranged in the substrate chip and electrically connected with the electric leading-out part;
the back metal layer is electrically connected with the conductive through hole to realize the electrical connection with the electrical lead-out part;
and the external solder balls are arranged on the external bonding pads of the back metal layer.
7. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein an underfill layer is formed between the heterogeneous chip and the substrate chip.
8. The system-in-package method of a hetero-integrated chip according to claim 1, wherein the carrier has an adhesive film thereon, and the adhesive film is made of a bonding film.
9. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein the thickness of the first integrated interposer is 50 to 200 microns, and the thickness of the second integrated interposer is 100 to 300 microns.
10. A system-in-package structure of a heterogeneous integrated chip, comprising:
a plurality of substrate chips;
the first plastic packaging layer covers the top of the substrate chip and the top of the slide glass;
a plurality of electrical leads of the substrate chips exposed on top of the first molding layer;
the metal interconnection layer and the dielectric layer are positioned at the top of the first plastic package layer, and the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;
and the heterogeneous chips are positioned on the tops of the metal interconnection layer and the dielectric layer and are electrically connected with the metal interconnection layer and the dielectric layer, and the absolute heights of the heterogeneous chips are the same.
CN202010284339.4A 2020-04-13 2020-04-13 System-level packaging method and structure of heterogeneous integrated chip Pending CN111446177A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111900095A (en) * 2020-08-12 2020-11-06 上海先方半导体有限公司 Multi-chip integrated packaging method and packaging structure
CN112908947A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 Plastic package structure and manufacturing method thereof
CN116779496A (en) * 2023-08-21 2023-09-19 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
CN103346097A (en) * 2013-06-25 2013-10-09 华进半导体封装先导技术研发中心有限公司 Method and structure for three-dimensional packaging based on TSV
US20140077381A1 (en) * 2011-01-21 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
KR20140147588A (en) * 2013-06-20 2014-12-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
CN105428260A (en) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 Manufacturing method of carrier-based fan-out 2.5D/3D package structure
CN108538732A (en) * 2017-03-01 2018-09-14 半导体元件工业有限责任公司 Semiconductor devices and the method for manufacturing semiconductor devices
CN109148394A (en) * 2017-06-28 2019-01-04 英特尔公司 The structure for forming the method for multi-chip package framework and being consequently formed

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7776649B1 (en) * 2009-05-01 2010-08-17 Powertech Technology Inc. Method for fabricating wafer level chip scale packages
US20140077381A1 (en) * 2011-01-21 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
KR20140147588A (en) * 2013-06-20 2014-12-30 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
CN103346097A (en) * 2013-06-25 2013-10-09 华进半导体封装先导技术研发中心有限公司 Method and structure for three-dimensional packaging based on TSV
CN105428260A (en) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 Manufacturing method of carrier-based fan-out 2.5D/3D package structure
CN108538732A (en) * 2017-03-01 2018-09-14 半导体元件工业有限责任公司 Semiconductor devices and the method for manufacturing semiconductor devices
US10121765B2 (en) * 2017-03-01 2018-11-06 Semiconductor Components Industries, Llc Semiconductor device and method of forming WLCSP
CN109148394A (en) * 2017-06-28 2019-01-04 英特尔公司 The structure for forming the method for multi-chip package framework and being consequently formed

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111900095A (en) * 2020-08-12 2020-11-06 上海先方半导体有限公司 Multi-chip integrated packaging method and packaging structure
CN112908947A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 Plastic package structure and manufacturing method thereof
CN116779496A (en) * 2023-08-21 2023-09-19 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips
CN116779496B (en) * 2023-08-21 2023-12-26 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips

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Application publication date: 20200724