CN110783316B - 具磁性屏蔽的装置及其制造方法 - Google Patents

具磁性屏蔽的装置及其制造方法 Download PDF

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CN110783316B
CN110783316B CN201910692836.5A CN201910692836A CN110783316B CN 110783316 B CN110783316 B CN 110783316B CN 201910692836 A CN201910692836 A CN 201910692836A CN 110783316 B CN110783316 B CN 110783316B
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magnetic
ferromagnetic particles
mixture
package
conductive
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CN110783316A (zh
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吕宗兴
曹佩华
朱立寰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种具磁性屏蔽的装置及其制造方法。提供一种非导电磁屏蔽材料作为半导体封装的磁性屏蔽层使用。通过将铁磁性颗粒结合到高分子基质中使所述材料磁性化,以及通过在铁磁性颗粒上提供绝缘涂覆物使所述材料不导电。

Description

具磁性屏蔽的装置及其制造方法
技术领域
本揭露涉及半导体装置及其制造方法,特别是关于具磁性屏蔽的半导体装置及其制造方法。
背景技术
许多电子元件在正常操作时由设计、非预期或甚至不受欢迎的副产品产生电磁辐射(electromagnetic radiation,EMR)。另一方面,许多电子元件对磁性或电磁辐射敏感,在足够的强度干扰下操作可以损坏数据存储或实际造成损坏。在一些情况下,为了电路的正常运行,较佳或甚至必须将产生EMR的装置设置在对EMR敏感的装置附近。在其他情况下,对EMR敏感的电子元件是电路或产品的一部分,可能需要在可能存在显著EMR强度的环境中操作。根据具体情况,任何层级的磁性屏蔽是可能需要的,包括产品层级、在电路板上电路之间或电路板之间的电路间层级(inter-circuit level)、电路板上晶片之间的晶片间层级、保护封装中的一个或多个集成电路的封装层级、以及甚至单个IC晶片上的电路之间的电路间层级。
具有高磁导率的铁磁金属及其合金能有效屏蔽静电和低频EMR,可包括例如铁(Fe)、μ-金属和高导磁合金(permalloy)等元素。
发明内容
本揭露的一实施方式提供一种具磁性屏蔽的装置,包含:磁性屏蔽层,包含混合物具有:多个铁磁性颗粒;绝缘涂覆物,封装各铁磁性颗粒;以及基质,含有涂覆的这些铁磁性颗粒。
本揭露的一实施方式另提供具磁性屏蔽的装置,包含:半导体晶粒,具有多个晶粒端;封装输入/输出界面,具有多个封装输入端和多个封装输出端;磁性屏蔽层,定位以屏蔽半导体晶粒免受磁场影响,磁性屏蔽层包含非导电磁屏蔽元件;以及多个电性接点,将各晶粒端电性耦接至对应这些封装输入端,各电性接点延伸通过非导电磁屏蔽元件,并与非导电磁屏蔽元件物理性接触。
本揭露的一实施方式另提供制备具磁性屏蔽的装置的方法,包含:形成磁性屏蔽层,通过:形成具有多个铁磁性颗粒以及基质材料的混合物,各铁磁性颗粒具有绝缘涂覆物,在这些铁磁性颗粒与混合物的体积比下赋予混合物选定的磁导率;以及混合物位于多个电性接点周围和之间,这些电性接点将半导体晶粒的多个接触端与输入/输出界面的多个接触端电性耦合。
附图说明
当结合附图阅读以下详细描述时,本揭露的一些实施方式的各种态样将最易于理解。应注意的是,根据行业标准操作规程,各种特征结构可能并非按比例绘制。事实上,为了论述的清晰性,可以任意地增大或减小各种特征结构的尺寸。
图1是具有封装层级磁性屏蔽的打线接合型(wire-bond-type)集成电路封装的示意性侧剖面图;
图2A是根据一实施方式中具有封装层级磁性屏蔽的打线接合型集成电路封装的示意性侧剖面图;
图2B是图2A的封装中2B部分的放大视图;
图3-14显示根据各个实施方式采用非导电磁屏蔽材料的各种类型的半导体封装的实施例;
图15是根据一实施方式用于磁性屏蔽半导体的封装280的方法流程图。
【符号说明】
100 封装
102 晶粒
103 接触端
104 封装基材
106 屏蔽板
108 屏蔽板
110 环氧树脂层
112 磁性环氧树脂
114 打线接合窗口
116 接合线
117 端子
118 模制化合物
120 球栅阵列
122 磁性屏蔽层
130 封装
131 磁性屏蔽层
132 模制化合物
134 非导电磁性填充材料
136 铁磁性颗粒
138 绝缘涂覆物
140 基质
150、160、170、180、190、200、210、220、230、240、250、260、280 封装
152 引线框架叶片
154、172 指部
155、166、174、184、198 封装主体
156 非导电磁性模制化合物
158、168、186、199、206 磁性屏蔽层
162、182、202、226、246 散热件
164、192 封装基材
194 凸块阵列
196 底部填充层
204 热传导润滑脂
212、222、242 封装壳
214、216、224、244 屏蔽板
282、284、286 步骤
具体实施方式
以下揭露内容提供了用于实现本揭露的一些实施方式的不同特征的许多不同实施例或示例。以下描述元件和布置的具体示例以简化本揭露的一些实施方式。当然,这些仅仅是示例,而不是限制性的。例如,在随后的描述中在第二特征上方或之上形成第一特征可以包含其中第一特征和第二特征以直接接触形成的实施例,并且还可以包含其中可以在第一特征和第二特征中形成附加特征使得第一特征和第二特征可以不直接接触的实施例。另外,本揭露的一些实施方式可以在各种示例中重复参考符号和/或文字。此重复是为了简单和清楚的目的,并且其本身并不表示所讨论的各种实施例和/或配置之间的关系。
此外,这里可以使用空间相对术语,例如“在...下面”、“下面的”、“低于”、“在...上面”、“高于”等,以便于描述如图所示的一个元件或特征与另一个元件或特征的关系。除了图中所示的取向之外,空间相对术语旨在包含使用或操作中的装置的不同取向。装置可以以其他方式定向(旋转90度或在其他方向上),并且同样可以相应地解释这里使用的空间相对描述符号。例如,在本文中做为参考,具体地是用于导电性。
图1是具有封装层级磁性屏蔽的打线接合型集成电路封装的示意性侧剖视图。封装100包括具有接触端103的集成电路的晶粒102,与上方和下方磁性的屏蔽板106、108一起设于封装基材104。环氧树脂层110将晶粒102结合到下方的屏蔽板108,并将下方的屏蔽板108结合到封装基板104。一层磁性环氧树脂112将上方的屏蔽板106结合到晶粒102与下方的屏蔽板108。打线接合窗口114延伸穿过下方的屏蔽板108和封装基材104,并且接合线(bond wire)116将晶粒102的接触端103电性耦接到封装基材104的端子117。“顶部点胶(glob-top)”填充剂或模制化合物(Mold compound)118封装并保护接合线116免于受损坏。球栅阵列(ball grid array)120位于封装基材104的底部,并且配置为将封装100电性耦接到电路板或类似基材上的对应触点阵列(contact array)。磁性屏蔽层122包括并由上方的屏蔽板106、下方的屏蔽板108以及磁性环氧树脂112所形成。
在根据本揭露的一实施方式中,磁性环氧树脂112是包含铁磁性颗粒的环氧树脂材料的基质。磁性环氧树脂112特别是在将上方的屏蔽板106结合到下方的屏蔽板108的区域中,完成屏蔽外壳(shield enclosure)的磁性“电路”,屏蔽外壳是由上方的屏蔽板106和下方的屏蔽板108所形成,否则将会沿整个周边开放。
随着磁场强度的增加,磁屏蔽将趋向饱和时,屏蔽的有效性将会下降。较高磁导率材料在较高磁场强度下饱和,这意味着在其他因素相同的情况下,具有较高磁导率的屏蔽将比较低磁导率的屏蔽更能防范高磁场强度的影响。因此,磁性的屏蔽板106、108和磁性环氧树脂112的铁磁性颗粒通常由具有高磁导率的材料制成,例如μ-金属、高导磁合金、元素铁(elemental iron)、软铁合金(soft iron alloy)等。然而,本揭露的一实施方式,不限于表现出在特定范围内磁导率的材料,在给定的情况下,适当的磁导率将取决于要保护的装置能免于受磁场伤害、以及设备运行的环境。因此,实施方式想象在相对低的磁导率是可接受的,而其它实施方式中在非常高磁导率是合适的。根据本揭露的其他实施方式,不被认为具有高磁导率的铁磁性颗粒与具有不同磁导率(例如,更高磁导率)的铁磁性颗粒结合存在于磁性屏蔽层中。本揭露的一实施方式不限于上述特定的铁磁材料。具有铁磁性质和更高或更低磁导率的其他材料可以用在根据本揭露的一实施方式的磁性屏蔽层中。
在本文中所用的术语诸如导电(conductive)和非导电(non-conductive)及其相似用语,具体地是导电率(electrical conductivity)。
使用如图1所示结构进行的测试中,发现通常所述结构有效地衰减垂直于封装基材104施加的磁场,即平行于Z轴。然而,在直接位于打线接合窗口114上方的晶粒102的区域中,磁场的衰减并未显著。例如,位于晶粒区域中的磁场强度增加大约400%至600%。
发明人已经认知到,如果顶部点胶的填充材料或模制化合物118用铁磁性颗粒配制,类似于磁性环氧树脂112,这将消除磁性屏蔽层对于晶粒102保护不足的弱点。然而,发明人还认知到这是不切实际的,因为高颗粒负载会使填充材料导电,并使接合线116短路。
因此,大多数磁性屏蔽半导体封装设计都具有易损区域,特别是使用电性接点作为将半导体晶粒电性耦合到封装元件的情况下,例如在本实施例中的封装基材104提供输入和输出连接至封装的外部。
环氧树脂(epoxy)本身通常不导电,也不具有在此特别有关的任何磁性。通过添加悬浮在环氧树脂基质中的铁磁性颗粒,使磁性环氧树脂112具有磁导性,但这些颗粒也倾向于增加环氧树脂/颗粒混合物的导电性。如上所述,在需要磁性屏蔽的应用中,颗粒优选是具高磁导性的。然而,磁性环氧树脂112的磁导性不仅取决于颗粒的磁导性,还取决于混合物中颗粒的密度。随着颗粒与总体积(即,环氧树脂基质+颗粒)的体积比的增加,混合物的有效磁导性增加。因此,较高的颗粒体积:混合物体积比(下文称为PMR)对于有效的磁性屏蔽是优选的。然而,在阈值PMR以上时,则混合物成为具导电性质。提供任何显著磁性屏蔽的磁性材料通常具有高于材料导电阈值体积比(conduction threshold volume ratio,下文称为CTR)的PMR,此时的PMR会让材料变为具有导电性。
图2A是根据一实施方式中具有封装层级磁性屏蔽的打线接合型集成电路封装的示意性侧剖视图。图2B是图2A的封装中2B部分的放大视图。封装130在多数方面类似于图1的封装100,除了包括包含形成有非导电磁性填充材料134的顶部点胶封闭物或模制化合物132的磁性屏蔽层131之外,非导电磁性填充材料134有助于磁性屏蔽层131中其他元件提供的封装磁性屏蔽,即,上方与下方的屏蔽板106、108以及磁性环氧树脂112。在图2A的实施方式中,接合线116延伸穿过非导电磁性填充材料134,非导电磁性填充材料134封装并使接合线116绝缘。根据所揭示的实施方式,PMR落在约10%至约80%的范围内。在其他实施方式中,PMR落在约30%至约60%的范围内。本揭露的一实施方式不限制PMR落在上述范围内。在根据本揭露的其他实施方式中,PMR可能落在上述范围下限值之下或者在上述范围的上限值之上。
图2B显示打线接合窗口114和顶部点胶封闭物或模制化合物132的放大部分,特别显示出非导电磁性填充材料134的细节。非导电磁性填充材料134包括高百分比的铁磁性颗粒136,每个铁磁性颗粒136具有绝缘涂覆物138。涂覆的铁磁性颗粒136悬浮在非导电材料的基质140中。绝缘涂覆物138使铁磁性颗粒136彼此电绝缘,使得混合物在比磁性环氧树脂112更高的PMR下不导电,同时提供足够层级的磁性屏蔽。这部分是可能的,因为绝缘涂覆物138在混合物中的相邻铁磁性颗粒136之间施加了最小绝缘体厚度,如下面更详细地解释。
再次参考图1的磁性环氧树脂112,铁磁性颗粒悬浮在非导电环氧树脂材料的基质内,基本上呈随机分布在基质中,使得这些颗粒间的空间比其他颗粒间的空间大许多倍。即使在相对较低的PMR,在没有绝缘材料将它们分开下也可能存在许多彼此物理接触的颗粒,而其他颗粒将比整体平均颗粒间距离多出许多倍。PMR主要定义混合物中颗粒的平均间距,而不是单个间距,但单个间距则是影响CTR的关键因素。
随着铁磁性颗粒被添加到非导电环氧树脂的基质中与PMR的增加,越来越多的铁磁性颗粒靠近在一起。最终,达到CTR颗粒密度时,几乎可以肯定在非导电环氧树脂和铁磁性颗粒的聚集将存在一条或多条路径。从铁磁性颗粒通过非导电环氧树脂的基质延伸到铁磁性颗粒,其中路径中的每对相邻铁磁性颗粒彼此非常紧密但间隔开,使得路径上绝缘材料的总厚度小到足以使施加的电压产生介电质击穿(dielectric breakdown),并且在基质中铁磁性颗粒的路径将变成具导电性。然而,在该PMR时,沿着导电路径的铁磁性颗粒间距,远小于在非导电环氧树脂和铁磁性颗粒中聚集的铁磁性颗粒的总平均间距。相反,如果在非导电环氧树脂的基质中每个铁磁性颗粒间的间距受到约束,则没有两个铁磁性颗粒可以定位在比某些最小距离更近的位置,即最小PMR出现在铁磁性颗粒的混合物和非导电环氧树脂开始导电时,此时CTR将会更高。
现在参阅图2B的非导电磁性填充材料134,在非导电磁性基质中的铁磁性颗粒136是随机分布,就像在磁性环氧树脂112中一样(图2A)。然而,在这种情况下,当两个铁磁性颗粒136彼此碰撞时,它们仍然通过各自绝缘涂覆物138的厚度而分离。任何两个铁磁性颗粒136之间可能的最近间距等于每个铁磁性颗粒上的绝缘涂覆物138的厚度之和。当每个铁磁性颗粒136上的绝缘涂覆物138的厚度相等时,任何两个铁磁性颗粒136之间可能的最近间距等于绝缘涂覆物138厚度的两倍。这是通过施加绝缘涂覆物138在铁磁性颗粒136上的最小绝缘体厚度。
因此,假设具有相同尺寸和组成的铁磁性颗粒,图1中的磁性环氧树脂112与图2A、图2B中的非导电磁性填充材料134在相同的PMR下将具有相同的磁导率。然而,在其他因素相同的情况下,非导电磁性填充材料134的CTR将高于磁性环氧树脂112的CTR。应当注意的是,为了确定非导电磁性填充材料134颗粒:混合物的比率,铁磁性颗粒136上的绝缘涂覆物138与基质140和颗粒一起包括在混合物中。
根据各种实施方式,铁磁性颗粒136的尺寸可以是各种变化,但是平均直径通常落在约0.1微米至约100微米的范围之间。根据一个实施方式,铁磁性颗粒的平均直径介于约1至30微米之间。根据本揭露的一实施方式,铁磁性颗粒的平均直径不限于落在上述范围内。根据其他实施方式,用于非导电磁性填充材料的铁磁性颗粒具有平均直径小于0.1微米或大于100微米。在一些实施方案中,常规的,即非铁磁性填充剂/颗粒也可以与包含铁磁性的填充剂一起添加到模制化合物或底部填充剂中。添加在模制化合物中的铁磁性填充剂/颗粒的粒径大小可能与底部填充剂(Underfill)中添加的大小不同。例如,模制化合物中的粒径大小将更大,并且底部填充剂中的粒径大小可能由于其功能性而更小。在一些实施方式中,对于底部填充剂而言,粒径大小将会是约个位数微米;而对于模制化合物而言,粒径大小将会是约两位数微米大小。
铁磁性颗粒136上的绝缘涂覆物138,可以是与非导电磁填充材料134的非导电基质的材料相容的任何合适的绝缘体/介电材料。例如,根据一实施方式,绝缘涂覆物138是通过物理或化学过程/反应沉积的非导电高分子(polymer)材料。可作为绝缘涂覆物138的高分子材料的实施例,包括聚乙烯(polyethylene)、苯乙烯-丙烯酸(styrene-acrylic)、和羧基苯乙烯-丁二烯(carboxylated styrene-butadiene)。根据另一实施方式,绝缘涂覆物138是无机化合物,例如介电氧化物、二氧化硅,或其他陶瓷材料。基质的材料可以是用于特定应用的任何合适的材料,包括例如硅酮(silicon)、环氧树脂、和其他高分子等。
控制最小绝缘体厚度的绝缘涂覆物138,其厚度是根据铁磁性颗粒尺寸、涂层材料的介电常数、和混合物所需的介电强度而变化。应当理解的是,如果铁磁性颗粒136相对较大,则在两个点之间形成导电路径所需铁磁性颗粒的数量将少于铁磁性颗粒相对较小的数量。由于路径中的铁磁性颗粒较少,并假设沿着防止导电所需路径的绝缘体厚度的总值是恒定,则对于路径中每对相邻铁磁性颗粒之间的平均绝缘体厚度而言,较大的铁磁性颗粒比较小的铁磁性颗粒更厚。类似地,大颗粒的最小绝缘体厚度也是大于小颗粒。因此,绝缘涂覆物的最小厚度和粒径直接相关。影响绝缘涂覆物138所需厚度的另一个因素是绝缘涂覆物138材料的介电常数。高k介电质具有更高的耐击穿电压,因此可以承受给定厚度的更高电压。所以对于给定电压,高k介电质材料的涂层可以比低k介电质材料更薄。因此,涂层材料的最小绝缘涂覆物厚度和介电常数是相反关系的。根据本揭露的一实施方式,绝缘涂覆物138具有范围从约0.01微米到约3微米的厚度。在其他实施方式中,绝缘涂覆物138的厚度落在约0.05微米至约2微米的范围内。在其他实施方式中,绝缘涂覆物138的厚度小于上述范围的下限值或者大于上述范围的上限值。
绝缘涂覆的铁磁性颗粒:非导电磁性填充材料134混合物的体积比是选择为低于预期应用中混合物的CTR,并且具有足以提供所需程度的磁性屏蔽的磁导率。应该注意的是,装置的设计参数包括接合线116的间距、施加在任两根导线上的最大电压差等,将施加混合物所需的最小介电强度,以避免在装置运行期间发生介电质击穿。反过来说,这将施加最大PMR值,所以混合物的磁导率可能受到装置的介电强度要求而限制。在设计阶段可以多种方式修改这些强加的数值。例如,可以修改接合线的间隔、可以将施加最高电压差的电路分配给阵列中距离最远的导线、可以选择铁磁性粒子上绝缘涂覆物的材料具有更高的k值、以及可以选择环氧基树脂基质的材料具有更高耐击穿电压。
再次参考图2A,根据另一实施方式,上方的屏蔽板106通过非导电的环氧树脂层110结合到晶粒102和下方的屏蔽板108,环氧树脂层110包括各自具有绝缘涂覆物的铁磁性颗粒,如非导电磁性填充材料134所描述。
参考上面图2A、图2B描述的封装130,提供可以受益于根据本揭露的一实施方式的非导电磁性屏蔽的装置的一实施例。预期其他的封装配置,也可以有类似的优点。图3-14显示根据本揭露的各个实施方式的具有封装层级磁性屏蔽的多种半导体封装的侧剖面图。
图3显示根据一实施方式的表面贴装引线框架(surface-mount lead-framepackage)的封装150,其中半导体晶粒102通过环氧树脂层110结合到引线框架叶片152(lead frame paddle)。晶粒102引线接合到引线框架的指部154,并且晶粒102、接合线116和引线框架叶片152被封装在非导电磁性模制化合物156的封装主体155中。非导电磁性模制化合物156包括具有绝缘涂覆物的铁磁性颗粒,基本上参考如图2B所述。非导电磁性模制化合物156作为磁性屏蔽层158,以保护晶粒102免受磁干扰。
图4显示根据一个实施方式的打线接合球栅阵列的封装160。晶粒102通过环氧树脂层110结合到磁性的散热件162。晶粒102上的接点经由接合线116电性耦合到封装基材164,并且从那里经由形成在封装基材164中的导电线路到达球栅阵列120。非导电磁性模制化合物156的封装主体166将晶粒102、散热件162和封装基材164上的接合线116封装在一起,并且与磁性的散热件一起形成磁性屏蔽层168。
图5显示根据一实施方式的打线接合引线框架的封装170,其中晶粒102通过粘合剂(环氧树脂层110)接合于框架的指部172。接合线116将晶粒102的电性接点电性耦合到相应框架的指部172,且晶粒102、接合线116和指部172被封装在非导电磁性模制化合物156的封装主体174中作为磁性屏蔽层158。
图6显示根据一个实施方式的打线接合球栅阵列的封装180,其中晶粒102接合到散热件182,散热件182又通过环氧树脂层110接合到封装基材104。接合线116经由形成在散热件182和封装基材104中的打线接合窗口将晶粒102电性耦合到封装基材104。球栅阵列120位于封装基材104的底面上。非导电磁性模制化合物156的封装主体184将晶粒102和散热件182封装在封装基材104上。根据一实施方式,形成有非导电磁性填充材料134的顶部点胶封闭物或模制化合物132(其与上述图2A和图2B所描述的非导电磁性模制化合物156基本相似)以保护接合线116。磁性屏蔽层186包括封装主体184、散热件182、和顶部点胶封闭物或模制化合物132。
图7显示根据一个实施方式的覆晶球栅阵列的封装190,其中晶粒102经由微球或凸块阵列194耦合到封装基材192。球栅阵列120位于封装基材192的底面上。非导电磁性的底部填充层196位于晶粒102和封装基材192之间,并且非导电磁性模制化合物156的封装主体198将晶粒102封装在封装基材192上。非导电磁性的底部填充层196包括具有绝缘涂覆物的铁磁性颗粒,基本上参考如上图2B所述。提供磁性屏蔽层199,其包括封装主体198和底部填充层196。
根据本揭露的替代实施方式,在图7中省略了底部填充层196。在封装时,非导电磁性模制化合物156填充晶粒102的下侧与封装基材192之间的间隙,并形成磁性屏蔽层199的一部分。
在一些情况下,除了由例如根据上述实施方式中磁性模制化合物的封装主体所提供的屏蔽之外,还可以进一步采用磁性屏蔽。图8-14的实施方式中,提供了采用屏蔽板和类似结构的半导体封装的实施例,屏蔽板由高磁导性材料形成,并与参照图1和图2A描述屏蔽板106、108的结构相似。
图8显示根据一实施方式的覆晶球栅阵列的封装200,其中晶粒102经由微球或凸块阵列194耦合到封装基材192。散热件202经由热传导润滑脂204(thermally conductivegrease)耦合到晶粒102的上表面。由于散热件202由具有高磁导率的材料形成,所以也作为包括底部填充层196的磁性屏蔽层206的一部分。
图9显示根据一实施方式的半导体的封装210。封装210在大多数方面类似于图3的封装150但还包括封装壳212,封装壳212包括上方与下方磁性的屏蔽板214、216。
图10显示根据一实施方式的半导体的封装220。封装220在大多数方面类似于图4的封装160但还包括封装壳222,封装壳222包括上方磁性的屏蔽板224。散热件226提供在晶粒102下方。散热件226由具有高磁导率的材料制成,并且作为下方磁性的屏蔽板。
图11显示根据一实施方式的半导体的封装230。封装230在大多数方面类似于图5的封装170但还包括封装壳212,封装壳212包括上方与下方磁性的屏蔽板214、216。
图12显示根据一实施方式的半导体的封装240。封装240在大多数方面类似于图6的封装180但还包括封装壳242,封装壳242包括上方磁性的屏蔽板244。散热件246设置在晶粒102下方并且由具有高磁导率的材料制成。散热件246作为下方磁性的屏蔽板。上方的屏蔽板244的左侧和右侧围绕延伸至下方的屏蔽板/散热件。
图13显示根据一实施方式的半导体的封装250。封装250在大多数方面类似于图7的封装190但还包括封装壳222,封装壳222包括上方的屏蔽板224。
图14显示根据一实施方式的半导体的封装260。封装260在大多数方面类似于图8的封装200,除了底部填充层196之外还包括非导电磁性模制化合物156以填充封装260。
图15是根据本揭露的一实施方式的用于磁性屏蔽半导体的封装280的方法的流程图。在步骤282,通过结合多个各自具有绝缘涂覆物的铁磁性颗粒与基质材料形成非导电磁性混合物,且在一体积比下赋予混合物选定的磁导率。
在步骤284,混合物位于多个电性接点周围和之间,这些电性接点将半导体晶粒的接触端与半导体封装的输入/输出界面的接触端电性耦合,并且在步骤286固化(cure)混合物。
根据一实施方式,混合物是顶部点胶填充材料或模制化合物,且位于封装的打线接合窗口内,并且保护将半导体晶粒的接触端与封装基材的接触端耦合的接合线。根据另一实施方式,混合物是底部填充材料或模制化合物,围绕并保护多个凸块,这些凸块将半导体晶粒电性耦合到封装基材。根据另一实施方式,混合物是封装半导体晶粒与电性接点的模制化合物,电性接点将晶粒耦合到引线框架、封装基材等。
上述非导电磁屏蔽材料提供了比不能用于与电导体接触的其他磁性材料更佳的显著优点。非导电材料可以用在半导体封装内的电性接点之间和周围,使电性接点绝缘,同时磁性地屏蔽封装内的半导体晶粒。这与其它已知不能用于与电性接点接触的封装屏蔽材料形成对比,且因此其它已知的封装屏蔽材料,不能用在封装的半导体晶粒和输入/输出界面元件之间所形成电性连接的区域中提供磁性屏蔽。
结合各种类型半导体封装的非导电磁性材料的实施例如上所述,这些材料包括环氧树脂、模制化合物、顶部点胶填充剂、底部填充剂等。这些材料通过将铁磁性颗粒结合到高分子基质中而制成磁性,并且通过在铁磁性颗粒上提供绝缘涂覆物而使其不导电。这些材料的非导电特性,能使这些材料在半导体封装中作为与电导体物理接触的磁屏蔽材料,不仅提供磁性屏蔽,而且还提供电绝缘。
根据一实施方式,一种装置包括磁性屏蔽,磁性屏蔽包括封装在基质中的多个铁磁性颗粒,其中各铁磁性颗粒被绝缘涂覆物所封装。
根据另一实施方式,一种装置包括具有多个晶粒端的半导体晶粒和具有多个封装输入端和多个封装输出端的封装输入/输出界面。磁性屏蔽设置以屏蔽半导体晶粒免受磁场影响,且磁性屏蔽包括非导电磁屏蔽元件。装置包括多个电性接点,将相对应的晶粒端耦合到相对应的封装输入端。电性接点延伸经由非导电磁屏蔽元件并与非导电磁屏蔽元件物理接触。
根据另一实施方式,提供了一种用于形成磁性屏蔽的方法。方法包括形成具有绝缘涂覆物的铁磁性颗粒和基质材料的混合物,在这些铁磁性颗粒与混合物的体积比下赋予混合物选定的磁导率。根据所述方法,混合物位于多个电性接点周围和之间,电性接点将半导体晶粒的接触端与输入/输出界面的接触端电性耦合。
本揭露的一实施方式提供一种具磁性屏蔽的装置,包含:磁性屏蔽层,包含混合物具有:多个铁磁性颗粒;绝缘涂覆物,封装各铁磁性颗粒;以及基质,含有涂覆的这些铁磁性颗粒。
在一些实施方式中,这些铁磁性颗粒是具有高磁导率的材料。
在一些实施方式中,这些铁磁性颗粒与混合物的体积比是选择以赋予混合物至少一目标磁导率。
在一些实施方式中,绝缘涂覆物的厚度是选择以赋予磁性屏蔽层至少一目标介电强度。
在一些实施方式中,基质包含高分子材料。
在一些实施方式中,基质包含顶部点胶填充剂。
在一些实施方式中,基质包含晶粒底部填充剂。
在一些实施方式中,基质包含半导体封装模制化合物
在一些实施方式中,绝缘涂覆物包含高分子材料。
在一些实施方式中,绝缘涂覆物包含介电氧化物。
本揭露的一实施方式另提供具磁性屏蔽的装置,包含:半导体晶粒,具有多个晶粒端;封装输入/输出界面,具有多个封装输入端和多个封装输出端;磁性屏蔽层,定位以屏蔽半导体晶粒免受磁场影响,磁性屏蔽层包含非导电磁屏蔽元件;以及多个电性接点,将各晶粒端电性耦接至对应这些封装输入端,各电性接点延伸通过非导电磁屏蔽元件,并与非导电磁屏蔽元件物理性接触。
在一些实施方式中,非导电磁屏蔽元件包含混合物,混合物包含:多个铁磁性颗粒;绝缘涂覆物,封装各铁磁性颗粒;以及基质,含有涂覆的这些铁磁性颗粒。
在一些实施方式中,非导电磁屏蔽元件具有这些铁磁性颗粒与混合物的体积比,以赋予非导电磁屏蔽元件高磁导率。
在一些实施方式中,绝缘涂覆物的厚度赋予非导电磁屏蔽元件选定的介电强度。
在一些实施方式中,绝缘涂覆物是陶瓷材料。
在一些实施方式中,绝缘涂覆物是高分子材料。
本揭露的一实施方式另提供制备具磁性屏蔽的装置的方法,包含:形成磁性屏蔽层,通过:形成具有多个铁磁性颗粒以及基质材料的混合物,各铁磁性颗粒具有绝缘涂覆物,在这些铁磁性颗粒与混合物的体积比下赋予混合物选定的磁导率;以及混合物位于多个电性接点周围和之间,这些电性接点将半导体晶粒的多个接触端与输入/输出界面的多个接触端电性耦合。
在一些实施方式中,混合物选定的磁导率是基于半导体晶粒的设计参数所决定。
在一些实施方式中,绝缘涂覆物的厚度是选择以赋予混合物选定的介电强度。
在一些实施方式中,混合物选定的介电强度是基于半导体晶粒的设计参数。
上文概述若干实施方式的特征,使得熟悉此项技术者可更好地理解本揭露的一些实施方式的态样。熟悉此项技术者应了解,可轻易使用本揭露的一些实施方式作为设计或修改其他制程及结构的基础,以便实施本文所介绍的实施方式的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到,此类等效结构并未脱离本揭露的一些实施方式的精神及范畴,且可在不脱离本揭露的一些实施方式的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (20)

1.一种具磁性屏蔽的装置,其特征在于,包含:
一半导体晶粒;
一磁性屏蔽层,包含一混合物覆盖该半导体晶粒的一第一部分,该混合物具有:
多个第一铁磁性颗粒;
一绝缘涂覆物,封装各该第一铁磁性颗粒;以及
一基质,含有涂覆的所述多个第一铁磁性颗粒;
一非导电的环氧树脂层;以及
一屏蔽外壳,包含:
一下方的磁性屏蔽板,该半导体晶粒通过该非导电的环氧树脂层结合到该下方的磁性屏蔽板;
一磁性环氧树脂,覆盖该半导体晶粒的一第二部分与该下方的磁性屏蔽板,并具有多个第二铁磁性颗粒彼此电性相连;以及
一上方的磁性屏蔽板,覆盖于该磁性环氧树脂上,且该上方的磁性屏蔽板通过该磁性环氧树脂结合到该半导体晶粒与该下方的磁性屏蔽板。
2.根据权利要求1所述的装置,其特征在于,所述多个第一铁磁性颗粒是具有高磁导率的材料。
3.根据权利要求1所述的装置,其特征在于,所述多个第一铁磁性颗粒与该混合物的一体积比是选择以赋予该混合物至少一目标磁导率。
4.根据权利要求1所述的装置,其特征在于,该绝缘涂覆物的一厚度是选择以赋予该磁性屏蔽层至少一目标介电强度。
5.根据权利要求1所述的装置,其特征在于,该基质包含一高分子材料。
6.根据权利要求1所述的装置,其特征在于,该基质包含一顶部点胶填充剂。
7.根据权利要求1所述的装置,其特征在于,该基质包含一晶粒底部填充剂。
8.根据权利要求1所述的装置,其特征在于,该基质包含一半导体封装模制化合物。
9.根据权利要求1所述的装置,其特征在于,该绝缘涂覆物包含一高分子材料。
10.根据权利要求1所述的装置,其特征在于,该绝缘涂覆物包含一介电氧化物。
11.一种具磁性屏蔽的装置,其特征在于,包含:
一半导体晶粒,具有多个晶粒端;
一封装输入/输出界面,具有多个封装输入端和多个封装输出端;
一非导电磁屏蔽元件,屏蔽该半导体晶粒的一第一部分;
一非导电的环氧树脂层;
一屏蔽外壳,包含:
一下方的磁性屏蔽板,该下方的磁性屏蔽板设置于该封装输入/输出界面的上方,该半导体晶粒通过该非导电的环氧树脂层结合到该下方的磁性屏蔽板,
一磁性环氧树脂屏蔽该半导体晶粒的一第二部分,且该磁性环氧树脂具导电性;以及
一上方的磁性屏蔽板,覆盖于该磁性环氧树脂上,且该上方的磁性屏蔽板通过该磁性环氧树脂结合到该半导体晶粒与该下方的磁性屏蔽板;以及
多个电性接点,将各该晶粒端电性耦接至对应所述多个封装输入端,各该电性接点延伸通过该非导电磁屏蔽元件,并与该非导电磁屏蔽元件物理性接触。
12.根据权利要求11所述的装置,其特征在于,该非导电磁屏蔽元件包含一混合物,该混合物包含:
多个铁磁性颗粒;
一绝缘涂覆物,封装各该铁磁性颗粒;以及
一基质,含有涂覆的所述多个铁磁性颗粒。
13.根据权利要求12所述的装置,其特征在于,该非导电磁屏蔽元件具有所述多个铁磁性颗粒与该混合物的一体积比,以赋予该非导电磁屏蔽元件一高磁导率。
14.根据权利要求12所述的装置,其特征在于,该绝缘涂覆物的一厚度赋予该非导电磁屏蔽元件选定的一介电强度。
15.根据权利要求12所述的装置,其特征在于,该绝缘涂覆物是一陶瓷材料。
16.根据权利要求12所述的装置,其特征在于,该绝缘涂覆物是一高分子材料。
17.一种制备具磁性屏蔽的装置的方法,其特征在于,包含:
形成一磁性屏蔽层,通过:
形成具有多个第一铁磁性颗粒以及一基质材料的一混合物,各该第一铁磁性颗粒具有一绝缘涂覆物,在所述多个第一铁磁性颗粒与该混合物的一体积比下赋予该混合物选定的一磁导率;
该混合物位于多个电性接点周围和之间,所述多个电性接点将一半导体晶粒的多个接触端与一输入/输出界面的多个接触端电性耦合;以及
形成一屏蔽外壳,包含:
定位在该半导体晶粒上的一磁性环氧树脂,该磁性环氧树脂包括多个第二铁磁性颗粒在该半导体晶粒上,其中基于所述多个第二铁磁性颗粒之间的传导,该磁性环氧树脂比该混合物具有更高的导电率;
形成一上方的磁性屏蔽板,覆盖于该磁性环氧树脂上,且该上方的磁性屏蔽板通过该磁性环氧树脂结合到该半导体晶粒与下方的磁性屏蔽板;
形成一非导电的环氧树脂层;以及
形成一下方的磁性屏蔽板,该下方的磁性屏蔽板设置于该输入/输出界面的上方,该半导体晶粒通过该非导电的环氧树脂层结合到该下方的磁性屏蔽板。
18.根据权利要求17所述的方法,其特征在于,该混合物选定的该磁导率是基于该半导体晶粒的设计参数所决定。
19.根据权利要求17所述的方法,其特征在于,该绝缘涂覆物的一厚度是选择以赋予该混合物选定的一介电强度。
20.根据权利要求19所述的方法,其特征在于,该混合物选定的该介电强度是基于该半导体晶粒的设计参数。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10892230B2 (en) 2018-07-30 2021-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding material with insulator-coated ferromagnetic particles
US11258356B2 (en) * 2019-07-31 2022-02-22 Analog Devices International Unlimited Company Magnetic barrier for power module
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2653693Y (zh) * 2003-03-14 2004-11-03 威盛电子股份有限公司 芯片封装结构
CN101188230A (zh) * 2007-03-28 2008-05-28 日月光半导体制造股份有限公司 封装结构及其制造方法
CN102574934A (zh) * 2009-10-15 2012-07-11 东丽株式会社 核壳颗粒的制造方法、核壳颗粒和使用该核壳颗粒的糊料组合物以及片材组合物
CN105518850A (zh) * 2013-09-04 2016-04-20 株式会社东芝 半导体装置及其制造方法
CN105556659A (zh) * 2013-10-15 2016-05-04 英特尔公司 磁屏蔽的集成电路封装

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118351A (en) * 1997-06-10 2000-09-12 Lucent Technologies Inc. Micromagnetic device for power processing applications and method of manufacture therefor
CA2245413C (en) * 1997-09-16 2001-09-18 Thomas & Betts International, Inc. Conductive elastomer for grafting to an elastic substrate
KR100533097B1 (ko) * 2000-04-27 2005-12-02 티디케이가부시기가이샤 복합자성재료와 이것을 이용한 자성성형재료, 압분 자성분말성형재료, 자성도료, 복합 유전체재료와 이것을이용한 성형재료, 압분성형 분말재료, 도료, 프리프레그및 기판, 전자부품
US20050206015A1 (en) 2004-03-16 2005-09-22 Texas Instruments Incorporated System and method for attenuating electromagnetic interference
CN1808702A (zh) * 2005-01-20 2006-07-26 矽品精密工业股份有限公司 半导体封装结构及其制法
JP5974803B2 (ja) * 2011-12-16 2016-08-23 Tdk株式会社 軟磁性合金粉末、圧粉体、圧粉磁芯および磁性素子
CN102568733B (zh) 2012-03-02 2015-02-25 杭州电子科技大学 一种薄膜复合宽频抗电磁干扰磁粉的制备方法
JP6443269B2 (ja) 2015-09-01 2018-12-26 株式会社村田製作所 磁心及びその製造方法
US9972579B1 (en) * 2016-11-16 2018-05-15 Tdk Corporation Composite magnetic sealing material and electronic circuit package using the same
WO2017166284A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Mold compound with coated beads
US10431732B2 (en) * 2017-05-31 2019-10-01 Globalfoundries Singapore Pte. Ltd. Shielded magnetoresistive random access memory devices and methods for fabricating the same
US10892230B2 (en) * 2018-07-30 2021-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding material with insulator-coated ferromagnetic particles

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2653693Y (zh) * 2003-03-14 2004-11-03 威盛电子股份有限公司 芯片封装结构
CN101188230A (zh) * 2007-03-28 2008-05-28 日月光半导体制造股份有限公司 封装结构及其制造方法
CN102574934A (zh) * 2009-10-15 2012-07-11 东丽株式会社 核壳颗粒的制造方法、核壳颗粒和使用该核壳颗粒的糊料组合物以及片材组合物
CN105518850A (zh) * 2013-09-04 2016-04-20 株式会社东芝 半导体装置及其制造方法
CN105556659A (zh) * 2013-10-15 2016-05-04 英特尔公司 磁屏蔽的集成电路封装

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