CN110767644A - 电子元器件封装件 - Google Patents

电子元器件封装件 Download PDF

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Publication number
CN110767644A
CN110767644A CN201910427721.3A CN201910427721A CN110767644A CN 110767644 A CN110767644 A CN 110767644A CN 201910427721 A CN201910427721 A CN 201910427721A CN 110767644 A CN110767644 A CN 110767644A
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China
Prior art keywords
electronic component
plating layer
sensor
component chip
package according
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CN201910427721.3A
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English (en)
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蔡永福
宫崎州平
山胁和真
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TDK Corp
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TDK Corp
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Publication of CN110767644A publication Critical patent/CN110767644A/zh
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Abstract

本发明的电子元器件封装件具备电子元器件模块，该电子元器件模块具有：基底部，包括第一面和第二面；第一镀层，覆盖第一面；第一电子元器件芯片，夹着第一绝缘层设在该第一镀层上；第二镀层，覆盖第二面；以及第二电子元器件芯片，夹着第二绝缘层设在该第二镀层上。此处，第一镀层和第二镀层含有第一金属材料，该第一金属材料比Ag(银)难以发生离子迁移现象。

Description

电子元器件封装件
技术领域
本发明涉及一种在一个引线框上设有两个以上电子元器件芯片的电子元器件封装件。
背景技术
近年来，已经有人提出一种技术，在安装在电子设备等中的传感器装置等的电子元器件封装件中谋求工作系统冗余化(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2017-191093号公报
发明内容
然而，对于这样的电子元器件封装件，还需要进一步提高工作可靠性。
因此，期望提供一种工作可靠性更加优异的电子元器件封装件。
作为本发明的一种实施方式的电子元器件封装件，具备：基底部，包括第一面和第二面；第一镀层，覆盖第一面；第一电子元器件芯片，夹着第一绝缘层设在该第一镀层上；第二镀层，覆盖第二面；以及第二电子元器件芯片，夹着第二绝缘层设在该第二镀层上。第一镀层和第二镀层含有第一金属材料，该第一金属材料比Ag(银)难以发生离子迁移现象。
附图说明
图1是剖视图，示出本发明的一种实施方式的传感器封装件的整体结构例。
图2是方框图，示出图1所示的传感器模块的结构例。
图3是剖视图，示出本发明的第一变形例的传感器封装件的整体结构。
图4是剖视图，示出本发明的第二变形例的传感器封装件的整体结构。
图5是剖视图，示出本发明的第三变形例的传感器封装件的整体结构。
图6是剖视图，示出本发明的第四变形例的传感器封装件的整体结构。
符号说明
1、1A～1D 传感器封装件
2 传感器模块
3、4 引线
3A、4A 芯
3B、4B 包层
5、6 线
7、7A 模制部
7V 空隙
11 基底部
12 镀层
13、14、19 绝缘层
15、16 ASIC
17、18 传感器元件
C1、C2 电子元器件芯片
P1、P2 焊盘
具体实施方式
下面参照附图对用于实施本发明的实施方式进行详细说明。以下说明的实施方式全都表示本发明所优选的一个具体例子。因此，在以下的实施方式中所示的数值、形状、材料、构成要素、构成要素的配置位置以及连接形态等，仅仅是一个例子，并不旨在限定本发明。因此，对以下的实施方式的构成要素中的、在表示本发明的最上位概念的独立权利要求中没有记载的构成要素，作为任意的构成要素进行说明。再有，各个附图仅是示意图，图示并不一定严密。另外，在各个附图中，对实质上同一的结构附加同一的符号，并且省略或简化重复的说明。再有，说明按以下的顺序进行。
1.一种实施方式
举出传感器封装件的一例，其具备传感器模块，在该传感器模块中，在被一体的镀层覆盖的基底部的两面上，分别夹着绝缘层设有一对传感器芯片。
2.变形例
2.1举出传感器封装件的一例，其具备传感器模块，在该传感器模块中，在基底部的两面上，分别夹着镀层和绝缘层设有一对传感器芯片。
2.2举出传感器封装件的一例，其具备传感器模块，在该传感器模块中，在被镀层覆盖的基底部的一面上，夹着共用的绝缘层设有一对传感器芯片。
2.3举出传感器封装件的一例，其具备传感器模块，在该传感器模块中，在未被镀层覆盖的基底部的两面上，分别夹着绝缘层设有一对传感器芯片。
2.4举出传感器封装件的一例，其在模制部的内侧设置有空隙，并在该空隙中配置有传感器等。
3.其他变形例
<1.一种实施方式>
[传感器封装件1的结构]
首先，参照图1，说明本发明的一种实施方式的传感器封装件1的结构。图1是剖面示意图，示出传感器封装件1的整体结构例。该传感器封装件1例如是用于检测磁场变化的磁传感器，是对应于本发明的“电子元器件封装件”的一具体例。
如图1所示，传感器封装件1具备：埋设在模制部7中的传感器模块2，引线3、4，以及线5、6。其中，引线3、4各自的一端埋设在模制部7中，各自的另一端被引到模制部7的外部。模制部7例如由绝缘性树脂构成。作为绝缘性树脂，例如可以列举在基体树脂中分散填充材料而得到的热固性树脂，其中，该基体树脂是环氧树脂，该填充材料主要是二氧化硅填料。另外，模制部7是对应于本发明的“保护膜”的一具体例。作为本发明的“保护膜”的构成材料，除了上述绝缘性树脂以外，也可以采用陶瓷、玻璃。
[传感器模块2的结构]
如图1所示，传感器模块2具有基底部11、镀层12、绝缘层13、绝缘层14、电子元器件芯片C1和电子元器件芯片C2。图2的方框图示出传感器模块2的结构例。
(基底部11)
基底部11例如是由铜等导电性材料构成的板部件或箔部件，且包括位于相反侧的面11A和面11B。
(镀层12)
镀层12是由金属材料构成的被膜，一体地覆盖包括面11A和面11B的基底部11的表面。
镀层12含有比Ag(银)难以发生离子迁移现象的金属材料即可，具体而言，含有包括Au(金)、Pd(钯)和Ni(镍)中的至少一种的金属材料即可。镀层12既可以具有由上述金属材料构成的单层结构，也可以具有多层层叠而成的多层结构。作为多层结构，优选例如Ni/Au双层结构、NiP/Au双层结构或Ni/Pd/Au三层结构等。再有，镀层12对应于本发明的“第一镀层”与“第二镀层”形成为一体的一具体例。
另外，例如能够通过被称作HAST(Highly Accelerated Temperature HumidityStress Test：高度加速老化试验)的不饱和加压蒸气试验对镀层12做出离子迁移评价。具体试验条件例如由IEC(国际电工委员会)的标准No.60068-2-66-60749规定。本实施方式中所说的“比Ag(银)难以发生离子迁移现象的金属材料”是指以下金属材料，与Ag(银)相比，采用该金属材料时，在110±2℃的温度范围内且85±5％RH的湿度范围内实施HAST达192小时的情况下，或在130±2℃ ℃的温度范围内且85±5％RH的湿度范围内实施HAST达96小时的情况下，从开始试验到出现故障为止的时间较长或从开始试验到结束试验为止未出现故障。
(绝缘层13和绝缘层14)
绝缘层13设在镀层12中的覆盖基底部11的面11A的部分上。而绝缘层14设在镀层12中的覆盖基底部11的面11B的部分上。绝缘层13和绝缘层14例如均为绝缘性粘合膜(DAF：Die Attach Film)。因此，绝缘层13和绝缘层14分别将电子元器件芯片C1和电子元器件芯片C2粘接并固定在被镀层12覆盖的基底部11上。电子元器件芯片C1和电子元器件芯片C2由于绝缘层13、绝缘层14和用于包封传感器模块2整体的模制部7的存在而彼此电分离。
(电子元器件芯片C1和电子元器件芯片C2)
如图1所示，电子元器件芯片C1夹着绝缘层13设在镀层12上。如图1和图2所示，电子元器件芯片C1包括特定用途集成电路(ASIC：application specific integratedcircuit)15、传感器元件17和焊盘P1。再有，虽未图示，但传感器元件17与ASIC15电连接。另外，如图1所示，电子元器件芯片C2夹着绝缘层14设在镀层12上。如图1和图2所示，电子元器件芯片C2包括ASIC16、传感器元件18和焊盘P2。再有，虽未图示，但传感器元件18与ASIC16电连接。传感器元件18与ASIC16例如利用导电线、镀膜等导电薄膜等实现电连接。这些导电线和导电薄膜例如含有Au(金)、Al(铝)、Cu(铜)等金属。而且，如图2所示，在传感器封装件1中，电子元器件芯片C1连接有对其供电的电源Vcc1，电子元器件芯片C2连接有对其供电的电源Vcc2。电源Vcc1分别与电子元器件芯片C1的ASIC15和传感器元件17相连。电源Vcc2分别与电子元器件芯片C2的ASIC16和传感器元件18相连。
电子元器件芯片C1、ASIC15和传感器元件17分别是对应于本发明的“第一电子元器件芯片”、“第一特定用途集成电路”和“第一传感器”的一具体例。同样，电子元器件芯片C2、ASIC16和传感器元件18分别是对应于本发明的“第二电子元器件芯片”、“第二特定用途集成电路”和“第二传感器”的一具体例。
(传感器元件17和传感器元件18)
传感器元件17和传感器元件18例如是对随磁性体位移而产生的外部磁场变化进行检测的磁传感器，例如包括霍尔元件、各向异性磁电阻效应(AMR：Anisotropic Magneto-Resistive effect)元件、巨磁电阻效应(GMR：Giant Magneto-Resistive effect)元件或隧道磁电阻效应(TMR：Tunnel Magneto-Resistance effect)元件等。传感器元件17和传感器元件18分别将随外部磁场变化而检测出的检测信号发送给ASIC15和ASIC16。
(ASIC15和ASIC16)
如图2所示，ASIC15例如具有A/D转换部151、运算部152和通信部153。A/D转换部151将来自传感器元件17的检测信号转换成数字信号，并输出给运算部152。运算部152根据来自传感器元件17且被转换为数字信号的检测信号，计算并求出例如磁性体的位移量，将该计算结果输出给通信部153。通信部153生成与来自运算部152的计算结果相关的输出信号，并经由焊盘P1输出到外部。同样，ASIC16例如具有A/D转换部161、运算部162和通信部163。A/D转换部161将来自传感器元件18的检测信号转换成数字信号，并输出给运算部162。运算部162根据来自传感器元件18且被转换为数字信号的检测信号，计算并求出例如磁性体的位移量，将该计算结果输出给通信部163。通信部163生成与来自运算部162的计算结果相关的输出信号，并经由焊盘P2输出到外部。
引线3是用于将来自电子元器件芯片C1的输出信号引到外部的导电性部件，例如具有由Cu(铜)等高导电性材料构成的芯3A和以包覆芯3A的方式形成的包层3B。包层3B例如是结构与镀层12相同的镀层。埋设在模制部7中的引线3的一端通过线5与焊盘P1相连。
引线4是用于将来自电子元器件芯片C2的输出信号引到外部的导电性部件，例如具有由Cu(铜)等高导电性材料构成的芯4A和以包覆芯4A的方式形成的包层4B。包层4B例如是结构与镀层12相同的镀层。埋设在模制部7中的引线4的一端通过线6与焊盘P2相连。
[传感器封装件1的效果]
在该传感器封装件1中，在一个基底部11上，设有彼此电气绝缘的电子元器件芯片C1和电子元器件芯片C2。而且，由不同的电源Vcc1和电源Vcc2分别对电子元器件芯片C1和电子元器件芯片C2供电。因此，能够利用电子元器件芯片C1和电子元器件芯片C2互相独立地检测外部磁场的变化，该外部磁场的变化例如是随磁性体位移而产生的会作用于传感器封装件1的变化。因此，在该传感器封装件1中能够实现工作系统的冗余化。即，在传感器封装件1中，例如能够在通常情况下仅让电子元器件芯片C1工作，并让电子元器件芯片C2待机备用。在传感器封装件1中，在怀疑电子元器件芯片C1出现故障等情况下，能够让备用的电子元器件芯片C2工作。
在传感器封装件1中，用镀层12覆盖基底部11的表面即面11A和面11B，镀层12含有比Ag(银)难以发生离子迁移现象的金属材料。此处，如果电子元器件芯片C1的使用电压与电子元器件芯片C2的使用电压不同，则电子元器件芯片C1的ASIC15的电位与电子元器件芯片C2的ASIC16的电位之间就会产生电位差。在此情况下，例如当镀层12由含有Ag(银)的金属材料形成时，在某些温度条件和湿度条件下，可能发生离子迁移现象。即，镀层12中含有的Ag(银)可能穿过绝缘层13或绝缘层14向ASIC15或ASIC16移动。一旦发生这样的离子迁移，绝缘层13和绝缘层14的电气绝缘性就会遭到破坏而产生漏电流，因此电子元器件芯片C1和电子元器件芯片C2将无望正常工作。对此，与镀层12由Ag(银)形成的情况相比，在本实施方式的传感器封装件1中，构成镀层12的上述金属材料难以向绝缘层13和绝缘层14渗透而破坏绝缘层13和绝缘层14的绝缘性。因此，即使电子元器件芯片C1的使用电压与电子元器件芯片C2的使用电压不同，电子元器件芯片C1和电子元器件芯片C2也会保持正常工作。所以，传感器封装件1的工作可靠性更优异。
<2.变形例>
(2.1第一变形例)
[传感器封装件1A的结构]
图3是剖视图，示出本发明的第一变形例的传感器封装件1A的整体结构例。上述实施方式的传感器封装件1具备将基底部11一体地包覆起来的镀层12。对此，在本变形例的传感器封装件1A的传感器模块2A中，设有例如覆盖基底部11的正面即面11A的镀层12A和覆盖基底部11的背面即面11B的镀层12B，且镀层12A和镀层12B彼此分离。除了这一点以外，传感器封装件1A与传感器封装件1实质上具有相同的结构。
[传感器封装件1A的作用和效果]
本变形例的传感器封装件1A也能够发挥与上述实施方式的传感器封装件1相同的效果。而且，因为在本变形例的传感器封装件1A中，设有彼此分离的镀层12A和镀层12B，所以能够使镀层12A的构成材料与镀层12B的构成材料不同。也能够通过不同的工序形成镀层12A和镀层12B。
(2.2第二变形例)
[传感器封装件1B的结构]
图4是剖视图，示出本发明的第二变形例的传感器封装件1B的整体结构例。在上述实施方式的传感器封装件1中，在基底部11的一面11A上设置电子元器件芯片C1，在基底部11的另一面11B上设置电子元器件芯片C2。对此，在本变形例的传感器封装件1B的传感器模块2B中，在面11A上夹着一个绝缘层19设置电子元器件芯片C1和电子元器件芯片C2双方。除了这一点以外，传感器封装件1B与传感器封装件1实质上具有相同的结构。
[传感器封装件1B的作用和效果]
本变形例的传感器封装件1B也能够发挥与上述实施方式的传感器封装件1相同的效果。另外，根据传感器封装件1B，还能够使其厚度比传感器封装件1的厚度薄。
(2.3第三变形例)
[传感器封装件1C的结构]
图5是剖视图，示出本发明的第三变形例的传感器封装件1C的整体结构例。在上述实施方式的传感器封装件1中，以覆盖基底部11的方式设置镀层12，并在该镀层12上设置电子元器件芯片C1和电子元器件芯片C2。对此，在本变形例的传感器封装件1C的传感器模块2C中，在面11A上夹着绝缘层13设置电子元器件芯片C1，并在面11B上夹着绝缘层14设置电子元器件芯片C2。除了这一点以外，传感器封装件1C与传感器封装件1实质上具有相同的结构。
[传感器封装件1C的作用和效果]
本变形例的传感器封装件1C也能够发挥与传感器封装件1相同的效果。即，在该传感器封装件1C中，在一个基底部11上，设有彼此电气绝缘的电子元器件芯片C1和电子元器件芯片C2。而且，由不同的电源Vcc1和电源Vcc2分别对电子元器件芯片C1和电子元器件芯片C2供电。因此，能够利用电子元器件芯片C1和电子元器件芯片C2互相独立地检测外部磁场的变化，该外部磁场的变化例如是随磁性体位移而产生的会作用于传感器封装件1C的变化。因此，在该传感器封装件1C中能够实现工作系统的冗余化。即，在传感器封装件1C中，例如能够在通常情况下仅让电子元器件芯片C1工作，并让电子元器件芯片C2待机备用。在传感器封装件1C中，在怀疑电子元器件芯片C1出现故障等情况下，能够让备用的电子元器件芯片C2工作。
并且，在本变形例的传感器封装件1C中，在没有用镀层覆盖基底部11的表面即面11A和面11B的情况下，设置绝缘层13、14。因此，能避免因构成镀层的金属的离子迁移现象而引起基底部11、电子元器件芯片C1和电子元器件芯片C2彼此之间短路。
(2.4第四变形例)
[传感器封装件1D的结构]
图6是剖视图，示出本发明的第四变形例的传感器封装件1D的整体结构例。在上述实施方式的传感器封装件1中，用模制部7紧密覆盖传感器模块2等。对此，在本变形例的传感器封装件1D中，在模制部7A的内部设置空隙7V，并在该空隙7V中设置传感器模块2和线5、6。除了这一点以外，传感器封装件1D与传感器封装件1实质上具有相同的结构。再有，模制部7A是对应于本发明的“保护膜”的一具体例。
[传感器封装件1D的作用和效果]
本变形例的传感器封装件1D也能够发挥与传感器封装件1相同的效果。而且，根据传感器封装件1D，因为在模制部7A的内部的空隙7V中设置传感器模块2D和线5、6，所以能够使传感器模块2和线5、6与模制部7A分开。因此，例如在模制部7A随环境温度变化而发生热胀冷缩时，也能避免赋予传感器元件17、18应力。在传感器元件17、18与模制部7A接触的情况下，由于热膨胀系数不同而会赋予传感器元件17、18应力，在一定大小的应力下传感器元件17、18的检测精度可能下降。然而，像本变形例的传感器封装件1D那样，通过至少使传感器元件17、18与模制部7A分开，就能够避免因模制部7A而赋予传感器元件17、18应力。
再有，在图6所示的传感器封装件1D中，虽然将传感器模块2与线5、6全都收纳在空隙7V中，但是本公开不限于此。具体而言，至少传感器元件17、18在不与模制部7A接触的情况下收纳在空隙7V中即可。而且，更优选的是，ASIC15、16在不与模制部7A接触的情况下收纳在空隙7V中。如果模制部7A与ASIC15、16接触，则由于模制部7A的热膨胀系数与ASIC15、16的热膨胀系数不同，ASIC15、16会产生应变，可能间接地赋予传感器元件17、18应力。但是，只要ASIC15、16是与模制部7A分开的，就能够避免传感器元件17、18被赋予这种间接的应力。而且，出于同样的理由，进一步优选的是，除了传感器元件17、18和ASIC15、16以外，线5、6也在不与模制部7A接触的情况下收纳在空隙7V中。
<3.其他变形例>
以上举出多个实施方式和变形例对本发明进行了说明，但本发明不限于这些实施方式等，能够进行各种变形。例如，在上述实施方式等中，举出TMR元件作为传感器元件的例子，说明了对随磁性体位移而产生的外部磁场变化进行检测的传感器封装件，但本发明的电子元器件封装件不限于此。本发明的电子元器件封装件还可以是对其他物理量进行检测的传感装置，例如电流感测装置、旋转感测装置、相对位置感测装置、磁罗盘或磁开关等。本发明的电子元器件封装件除了包括半导体存储器等电子元器件以外，还可以包括电容器、电感器或电阻器等无源元件。
此外，图1等所示的传感器封装件的各构成要素的形状、尺寸和布置位置等仅为示例，并不限于此。并且，图1等所示的传感器封装件的各构成要素不必全部具备，也可以具备未图示的其他构成要素。
此外，在上述实施方式等中，举出设置两个电子元器件芯片的情况为例，但还可以具备三个以上电子元器件芯片。
在本发明的一种实施方式的电子元器件封装件中，第一镀层和第二镀层均含有比Ag(银)难以发生离子迁移现象的金属材料。因此，不易发生该金属材料向覆盖第一镀层和第二镀层的第一绝缘层和第二绝缘层渗透而破坏第一绝缘层和第二绝缘层的绝缘性的现象。
根据本发明的一种实施方式的电子元器件封装件，工作可靠性更优异。
再有，本技术也能够采用以下结构。
(1)
一种电子元器件封装件，具备：
基底部，包括第一面和第二面；
第一镀层，覆盖所述第一面；
第一电子元器件芯片，夹着第一绝缘层设在所述第一镀层上；
第二镀层，覆盖所述第二面；以及
第二电子元器件芯片，夹着第二绝缘层设在所述第二镀层上，
所述第一镀层和所述第二镀层含有第一金属材料，所述第一金属材料比银难以发生离子迁移现象。
(2)
所述(1)所述的电子元器件封装件，其中，
所述第一金属材料包括金、钯和镍中的至少一种。
(3)
所述(1)或所述(2)所述的电子元器件封装件，其中，
所述第一镀层与所述第二镀层形成为一体。
(4)
一种电子元器件封装件，具备：
基底部，包括第一面和第二面；
第一电子元器件芯片，夹着第一绝缘层设在所述第一面上；以及
第二电子元器件芯片，夹着第二绝缘层设在所述第二面上。
(5)
所述(1)至所述(4)中的任一项所述的电子元器件封装件，其中，
所述第一电子元器件芯片包括第一特定用途集成电路和第一传感器。
(6)
所述(1)至所述(5)中的任一项所述的电子元器件封装件，其中，
所述第二电子元器件芯片包括第二特定用途集成电路和第二传感器。
(7)
所述(1)至所述(6)中的任一项所述的电子元器件封装件，其中，
所述第一绝缘层和所述第二绝缘层均为绝缘性粘合膜。
(8)
所述(1)至所述(7)中的任一项所述的电子元器件封装件，其中，
所述第一面和所述第二面位于所述基底部上的相反侧。
(9)
所述(1)至所述(8)中的任一项所述的电子元器件封装件，其中，
进一步具备：
第一引线，设在与所述基底部分开的位置；
第三镀层，覆盖所述第一引线的表面；以及
第一导线，连接所述第三镀层与所述第一电子元器件芯片的第一端子。
(10)
所述(9)所述的电子元器件封装件，其中，
进一步具备：
第二引线，设在与所述基底部和所述第一引线分开的位置；
第四镀层，覆盖所述第二引线的表面；以及
第二导线，连接所述第四镀层与所述第二电子元器件芯片的第二端子。
(11)
所述(10)所述的电子元器件封装件，其中，
进一步具备保护膜，
所述保护膜覆盖所述第一电子元器件芯片、所述第二电子元器件芯片、所述第一引线的一部分、所述第三镀层的一部分、所述第一导线、所述第二引线的一部分、所述第四镀层的一部分和所述第二导线。
(12)
所述(11)所述的电子元器件封装件，其中，
所述保护膜的内部具有空隙，
所述第一电子元器件芯片包括第一特定用途集成电路和第一传感器，
所述第二电子元器件芯片包括第二特定用途集成电路和第二传感器，
至少所述第一传感器和所述第二传感器设在所述空隙中。
(13)
所述(10)至所述(12)中的任一项所述的电子元器件封装件，其中，所述第三镀层和所述第四镀层含有第二金属材料，所述第二金属材料比银难以发生离子迁移现象。
本公开含有涉及在2018年7月27日在日本专利局提交的日本优先权专利申请JP2018-141111中公开的主旨，其全部内容包含在此，以供参考。
本领域的技术人员应该理解，虽然根据设计要求和其他因素可能出现各种修改，组合，子组合和可替换项，但是它们均包含在附加的权利要求或它的等同物的范围内。

Claims (13)

1.一种电子元器件封装件，具备：
基底部，包括第一面和第二面；
第一镀层，覆盖所述第一面；
第一电子元器件芯片，夹着第一绝缘层设在所述第一镀层上；
第二镀层，覆盖所述第二面；以及
第二电子元器件芯片，夹着第二绝缘层设在所述第二镀层上，
所述第一镀层和所述第二镀层含有第一金属材料，所述第一金属材料比银难以发生离子迁移现象。
2.根据权利要求1所述的电子元器件封装件，其中，
所述第一金属材料包括金、钯和镍中的至少一种。
3.根据权利要求1或权利要求2所述的电子元器件封装件，其中，
所述第一镀层与所述第二镀层形成为一体。
4.一种电子元器件封装件，具备：
基底部，包括第一面和第二面；
第一电子元器件芯片，夹着第一绝缘层设在所述第一面上；以及
第二电子元器件芯片，夹着第二绝缘层设在所述第二面上。
5.根据权利要求1至权利要求4中的任一项所述的电子元器件封装件，其中，
所述第一电子元器件芯片包括第一特定用途集成电路和第一传感器。
6.根据权利要求1至权利要求5中的任一项所述的电子元器件封装件，其中，
所述第二电子元器件芯片包括第二特定用途集成电路和第二传感器。
7.根据权利要求1至权利要求6中的任一项所述的电子元器件封装件，其中，
所述第一绝缘层和所述第二绝缘层均为绝缘性粘合膜。
8.根据权利要求1至权利要求7中的任一项所述的电子元器件封装件，其中，
所述第一面和所述第二面位于所述基底部上的相反侧。
9.根据权利要求1至权利要求8中的任一项所述的电子元器件封装件，其中，
进一步具备：
第一引线，设在与所述基底部分开的位置；
第三镀层，覆盖所述第一引线的表面；以及
第一导线，连接所述第三镀层与所述第一电子元器件芯片的第一端子。
10.根据权利要求9所述的电子元器件封装件，其中，
进一步具备：
第二引线，设在与所述基底部和所述第一引线分开的位置；
第四镀层，覆盖所述第二引线的表面；以及
第二导线，连接所述第四镀层与所述第二电子元器件芯片的第二端子。
11.根据权利要求10所述的电子元器件封装件，其中，
进一步具备保护膜，
所述保护膜覆盖所述第一电子元器件芯片、所述第二电子元器件芯片、所述第一引线的一部分、所述第三镀层的一部分、所述第一导线、所述第二引线的一部分、所述第四镀层的一部分和所述第二导线。
12.根据权利要求11所述的电子元器件封装件，其中，
所述保护膜的内部具有空隙，
所述第一电子元器件芯片包括第一特定用途集成电路和第一传感器，
所述第二电子元器件芯片包括第二特定用途集成电路和第二传感器，
至少所述第一传感器和所述第二传感器设在所述空隙中。
13.根据权利要求10至权利要求12中的任一项所述的电子元器件封装件，其中，
所述第三镀层和所述第四镀层含有第二金属材料，所述第二金属材料比银难以发生离子迁移现象。
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