CN110687431A - Monitoring assembly, system and method based on system-in-package device running state - Google Patents
Monitoring assembly, system and method based on system-in-package device running state Download PDFInfo
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- CN110687431A CN110687431A CN201910952154.3A CN201910952154A CN110687431A CN 110687431 A CN110687431 A CN 110687431A CN 201910952154 A CN201910952154 A CN 201910952154A CN 110687431 A CN110687431 A CN 110687431A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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Abstract
The invention discloses a monitoring component, a system and a method based on the operation state of a system-in-package device, which comprises a test board for installing the system-in-package device, a main control board and a PC, wherein the test board is in signal connection with the main control board, the main control board provides a power supply, a clock signal and a reset signal for the test board and controls the test process of the test board on the system-in-package device, the main control board is in signal connection with the PC, and the PC acquires the test result of test data generated in the test process of the test board on the system-in-package device. The defects of the SiP device can be captured in real time, and the testing accuracy of the SiP device is further improved.
Description
Technical Field
The invention relates to the technical field of component reliability, in particular to a monitoring assembly, a system and a method based on the operation state of a system-in-package device.
Background
The SiP (System In a Package) device is a component of a multifunctional substrate integrated chip, is lighter and has high reliability, and is more and more popular In the market.
The traditional function monitoring method is mainly used for carrying out test work on the SiP device in the process of each strengthening test project at regular time and judging whether the function of a tested sample is abnormal or not, but partial defects can be recovered to a normal state after losing a strengthening test environment, for example, the defects are excited by applying stress, the defects cannot be captured in real time by the traditional method, and further the result of monitoring the function operation of the SiP device is inaccurate.
Disclosure of Invention
In view of the above, the present invention provides a monitoring assembly, a system and a method based on the operation status of a system-in-package device to improve the accuracy of the monitoring result.
Based on the above purpose, a monitoring assembly based on the operation state of a system-in-package device is provided, which includes: the test board, the main control board and the PC are used for mounting the system-in-package device; wherein,
the test board is in signal connection with the main control board, the main control board provides a power supply, a clock signal and a reset signal for the test board and controls the test process of the test board on the system-in-package device, the main control board is in signal connection with the PC, and the PC obtains the test result of test data generated in the test process of the test board on the system-in-package device.
Optionally, the main control board includes an ARM processor, a dc power supply, a clock signal source and a reset signal source, the ARM processor is in signal connection with the test board, and the dc power supply, the clock signal source and the reset signal source are in signal connection with the test board.
Optionally, the main control board further includes an audible and visual alarm, and the audible and visual alarm gives an alarm to an abnormal condition in the test process.
Optionally, the test board includes multilayer PCB board and special plug connector, and system level package device is installed through point dress and some point processing on the multilayer PCB board, the multilayer PCB board passes through special plug connector with main control board signal connection.
Optionally, a display and control program is installed on the PC, and the display and control program displays a test result of the test board on the system-in-package device in real time and generates a monitoring log.
A monitoring system based on the operation state of a system-in-package device comprises the system-in-package device and a monitoring component,
the system-in-package device comprises a DSP module and an FPGA module, wherein the DSP module and the FPGA module both comprise a plurality of test items;
the main control board in the monitoring assembly is used for determining a current test item to be tested, sending a test instruction to the current test item, controlling the current test item to execute the test instruction, obtaining a test result fed back by the current test item and sending the test result to the PC;
and the PC is used for receiving and displaying the test result.
Optionally, the controlling the current test item to execute the test instruction includes any one or more of the following steps: performing the said I2The function test of a C bus, the execution of the McBSP interface test, the execution of the external interrupt function test, the execution of the read-write test of the SRAM memory, the execution of the read-write test of the FLASH memory, the execution of the communication test of the DSP module and the FPGA module, the execution of the FDC module test, the execution of the level conversion transceiver test and the execution of the RS-422 transceiver test.
Optionally, the number of the McBSP interfaces is 2, the McBSP0 interfaces and the McBSP1 interfaces are provided, and the number of the RS-422 transceivers is 7.
A monitoring method is applied to a monitoring system, and comprises the following steps:
the main control board determines a current test item to be tested;
the main control board sends a test instruction to the current test item;
the main control board controls the current test item to execute a test instruction;
the main control board obtains the test result fed back by the current test item and sends the test result to the PC;
and the PC receives and displays the test result.
Optionally, the PC further generates a monitoring log.
From the above, the monitoring assembly, the system and the method based on the operation state of the system-in-package device provided by the invention are used for researching the operation state monitoring method aiming at the SiP device, the function monitoring circuit design of the SiP device is completed through the arrangement of the test board, the main control board controls the work of the test board, the test result of the SiP device in the reinforced test is obtained in real time, the defect of the SiP device can be captured in real time, and the test accuracy of the SiP device is further improved.
Drawings
FIG. 1 is a schematic view of a monitoring assembly of an embodiment of the present invention;
FIG. 2 is a flow chart of a monitoring method of an embodiment of the present invention;
FIG. 3 shows an embodiment of the present invention2C, a flow chart of the test of the bus;
FIG. 4 is a flow chart of the testing of an FDC module of an embodiment of the present invention;
fig. 5 is a flow chart of a test of a level shifting transceiver according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
In an embodiment of the invention, as shown In fig. 1, the monitoring component includes a test board 1 for mounting a System In Package device 4, a main control board 2 and a PC (Personal Computer) 3, the test board 1 is In signal connection with the main control board 2, the main control board 2 provides a power supply, a clock signal and a reset signal for the test board 1 and controls a test process of the test board 1 on the System In Package device 4, the main control board 2 is In signal connection with the PC3, and the PC3 obtains a test result of the test board 1 on the System In Package device 4. According to the invention, the operation state monitoring method is researched for the system-in-package device 4, the function monitoring circuit design of the system-in-package device 4 is completed through the arrangement of the test board 1, the main control board controls the work of the test board, the test result of the SiP device in the reinforced test is obtained in real time, the defect of the SiP device can be captured in real time, and the test accuracy of the SiP device is further improved.
In one embodiment, the main control board 2 includes an ARM processor 21, a dc power supply 22, a clock signal source 23 and a reset signal source 24, the ARM processor 21 is in signal connection with the test board 1, and the dc power supply 22, the clock signal source 23 and the reset signal source 24 are in signal connection with the test board 1.
In one embodiment, the test board 1 includes a multi-layer PCB 11 and a dedicated connector 12, the SiP device 4 is mounted on the multi-layer PCB 11 by spot-mounting and spot-gluing, and the multi-layer PCB 11 is connected to the main control board 2 through the dedicated connector 12. Wherein, the multilayer PCB board 11 is arranged on the aluminum block through the reinforcing ribs to increase the stability of the test board 1 during the test, the traditional system-in-package device 4 test is to directly weld and arrange the system-in-package device 4 on the circuit board, apply test environments such as vibration, temperature change, impact and the like to the system-in-package device 4, then disassemble the system-in-package device 4, test each pin of the system-in-package device 4, the repeated disassembly and assembly can damage the pin of the system-in-package device 4, thereby causing the failure of assembly and connection, the invention installs the system-in-package device 4 on the multilayer PCB board 11 through point-mounting and point-gluing treatment, and communicates the point of the system-in-package device 4 to be tested with the main control board 2 through the special plug 12, directly apply the test environment to the test board 1 during the test, the main control board 2 collects the test data of the system-in-package device, the system-in-package device 4 is monitored in real time, and the system-in-package device 4 does not need to be detached for offline testing, so that repeated disassembly and assembly of the SiP device 4 are reduced, and the stability of a test result is improved.
In one embodiment, the main control board 2 further comprises an audible and visual alarm 25, and the audible and visual alarm 25 alarms abnormal conditions in the test process. The audible and visual alarm 25 comprises a buzzer, a breathing lamp and an LED lamp, the breathing lamp monitors the running state of the system-in-package device 4, and the DSP module and the FPGA module are observed whether running or not through flickering the LED lamp.
In one embodiment, the PC3 has a display and control program installed thereon, and the display and control program displays the test results of the SiP devices 4 on the test board 1 in real time and generates a monitoring log. The content of the monitoring log comprises a test item and a time point which are abnormal, so that the problem can be traced conveniently, and when the abnormal occurs, the time when the abnormal occurs and the corresponding abnormal test item information are written into a log file (the time format is year, month, day, hour, minute and second); when the test item is normal, the related information when returning to the normal state is written into the log file.
The embodiment of the invention also provides a system for monitoring the functional running state of the SiP device, which comprises a system-in-package device and a monitoring component,
the SiP device 4 comprises a DSP (Digital Signal Processing) module and an FPGA (Field-Programmable Gate Array) module, wherein the DSP module and the FPGA module both comprise a plurality of test items; the main control board 2 in the monitoring assembly is used for determining a current test item to be tested, sending a test instruction to the current test item, controlling the current test item to execute the test instruction, obtaining a test result fed back by the current test item, and sending the test result to the PC 3; the PC3 is used for receiving and displaying the test results. The DSP module and the FPGA module are core devices for realizing the functions of the SiP device 4, and the function test of the SiP device 4 is mainly performed around the DSP module and the FPGA module.
In one embodiment, the test item includes I2C bus function test, McBSP interface test, external interrupt function test, SRAM memory read-write test, FLASH memory read-write test, DSP module and FPGA module communication test, FDC module test, level conversion transceiver test and RS-422 transceiver function test, wherein I2C bus, McBSP interface, SRAM storageThe FLASH memory and the FLASH memory are connected with the DSP module, the FDC module, the level conversion transceiver and the RS-422 transceiver are connected with the FPGA module, the number of McBSP interfaces is 2, the McBSP0 interfaces and the McBSP1 interfaces are respectively arranged, and the number of the RS-422 transceivers is 7.
As shown in fig. 2, an embodiment of the present invention further provides a monitoring method for a system-in-package device function operation state monitoring system, including:
s101: the main control board 2 determines a current test item to be tested;
s102: the main control board 2 sends a test instruction to the current test item;
s103, the main control board 2 controls the current test item to execute a test instruction;
s104, the main control board 2 acquires the test result fed back by the current test item and sends the test result to the PC 3;
and S105, receiving and displaying the test result by the PC 3.
Optionally, the PC further generates a monitoring log.
In one embodiment, as shown in fig. 3, S103 may include:
performing the said I2C, testing of the bus: the main control board 2 sends a test signal to the FPGA module, and the FPGA module is used as a slave device and the I2The bus C is communicated, if the FPGA module does not receive or receives wrong data, the fault of the test item is represented, and a display control program displays the fault information;
performing a test of the McBSP interface: the number of the McBSP interfaces is two, the McBSP0 Interface and the McBSP1 Interface are respectively used as the McBSP0 Interface and the McBSP1 Interface for executing SPI communication, the McBSP0 Interface is in an SPI (Serial peripheral Interface) master mode, the McBSP1 Interface is in an SPI slave mode, the McBSP0 Interface provides a displacement clock signal and a slave equipment enabling signal and communicates with the McBSP1 Interface, if the FPGA module does not receive or receives wrong data, the test item is indicated to be faulty, and a display control program displays the fault information;
executing the external interrupt function test: the main control board 2 provides 4 external interrupt signals to the DSP module, and if the interrupt does not respond, a fault is indicated;
executing the SRAM memory read-write test: the main control board 2 writes a plurality of test data into the SRAM memory every a plurality of seconds, then reads the test data, if the read data is consistent with the written data, the SRAM memory is normal, otherwise, the SRAM memory is in failure;
and executing the FLASH memory read-write test: the main control board 2 writes a plurality of test data into the FLASH memory every a plurality of seconds, then reads the test data, if the read data is consistent with the written data, the FLASH memory is indicated to be normal, otherwise, the FLASH memory is indicated to be in fault;
executing the communication test between the DSP module and the FPGA module: configuring the DSP module and the FPGA module, instantiating the FPGA module as a peripheral of the DSP module, accessing the FPGA module by the DSP module through an EMIF (External memory interface) bus, and indicating a fault if no error data is received or wrong data is received;
as shown in fig. 4, the testing of the FDC module is performed: the main control board 2 applies a set frequency square wave to the FDC module, the FDC module shapes and inverts the set frequency square wave and outputs the shaped and inverted set frequency square wave to the FPGA module, the FPGA module captures the set frequency square wave and feeds the set frequency square wave back to the main control board 2, if the pulse width and the frequency of a read set frequency square wave signal are the same as those of the applied set frequency square wave, the FDC module is normal, otherwise, a fault is indicated;
as shown in fig. 5, the testing of the level shifting transceiver is performed: the main control board 2 controls the FPGA module to output a level conversion input signal, the level conversion transceiver converts the level conversion input signal and feeds the converted signal back to the main control board 2, if the converted signal is consistent with a set signal, the level conversion transceiver is normal, otherwise, a fault is indicated;
performing a test of the RS-422 transceiver: the number of the RS-422 transceivers is 7, the main control board 2 sends data to the FPGA module through one RS-422 transceiver, the FPGA module receives the data, transmits the data through the other 6 RS-422 transceivers in sequence and sends the data to the main control board 2, if the read data is consistent with the written data, the RS-422 transceivers are normal, otherwise, the fault is indicated.
According to the monitoring assembly, the monitoring system and the monitoring method for the functional running state of the SiP device, the research of the running state monitoring method is carried out for the SiP device, the functional monitoring circuit design of the SiP device is completed through the arrangement of the test board, the main control board controls the work of the test board, the test result of the SiP device during the reinforced test is obtained in real time, the defects of the SiP device can be captured in real time, and the testing accuracy of the SiP device is further improved.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.
The embodiments of the invention are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A monitoring assembly based on the operation state of a system-in-package device is characterized by comprising: the test board, the main control board and the PC are used for mounting the system-in-package device; wherein,
the test board is in signal connection with the main control board, the main control board provides a power supply, a clock signal and a reset signal for the test board and controls the test process of the test board on the system-in-package device, the main control board is in signal connection with the PC, and the PC obtains the test result of test data generated in the test process of the test board on the system-in-package device.
2. The monitoring assembly of claim 1, wherein the main control board comprises an ARM processor, a dc power source, a clock signal source and a reset signal source, the ARM processor is in signal connection with the test board, and the dc power source, the clock signal source and the reset signal source are in signal connection with the test board.
3. The monitoring assembly of claim 2, wherein the main control board further comprises an audible and visual alarm that alerts of an abnormal condition during the testing process.
4. The monitoring assembly according to claim 1, wherein the test board comprises a multi-layer PCB board and a dedicated connector, the system-in-package device is mounted on the multi-layer PCB board through a point-mounting and point-dispensing process, and the multi-layer PCB board is in signal connection with the main control board through the dedicated connector.
5. The monitoring assembly according to claim 1, wherein a display and control program is installed on the PC, and the display and control program displays the test result of the system-in-package device from the test board in real time and generates a monitoring log.
6. A system-in-package device operation status-based monitoring system, comprising a system-in-package device and the monitoring component of any one of claims 1-5,
the system-in-package device comprises a DSP module and an FPGA module, wherein the DSP module and the FPGA module both comprise a plurality of test items;
the main control board in the monitoring assembly is used for determining a current test item to be tested, sending a test instruction to the current test item, controlling the current test item to execute the test instruction, obtaining a test result fed back by the current test item and sending the test result to the PC;
and the PC is used for receiving and displaying the test result.
7. The monitoring system of claim 6, wherein the controlling the current test item to execute test instructions comprises any one or more of: performing the said I2The function test of a C bus, the execution of the McBSP interface test, the execution of the external interrupt function test, the execution of the read-write test of the SRAM memory, the execution of the read-write test of the FLASH memory, the execution of the communication test of the DSP module and the FPGA module, the execution of the FDC module test, the execution of the level conversion transceiver test and the execution of the RS-422 transceiver test.
8. The monitoring system of claim 7, wherein the number of McBSP interfaces is 2, the McBSP0 interfaces and the McBSP1 interfaces, respectively, and the number of RS-422 transceivers is 7.
9. A method for monitoring an operation state of a system-in-package device, the method being applied to the monitoring system of any one of claims 6 to 8, the method comprising:
the main control board determines a current test item to be tested;
the main control board sends a test instruction to the current test item;
the main control board controls the current test item to execute a test instruction;
the main control board obtains the test result fed back by the current test item and sends the test result to the PC;
and the PC receives and displays the test result.
10. The monitoring method of claim 9, wherein the PC further generates a monitoring log.
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