CN110683856B - 导电性多孔陶瓷基板及其制造方法 - Google Patents

导电性多孔陶瓷基板及其制造方法 Download PDF

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CN110683856B
CN110683856B CN201910598815.7A CN201910598815A CN110683856B CN 110683856 B CN110683856 B CN 110683856B CN 201910598815 A CN201910598815 A CN 201910598815A CN 110683856 B CN110683856 B CN 110683856B
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powder
ceramic substrate
tio
porous ceramic
mnco
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CN110683856A (zh
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金炳学
白承佑
崔準凡
金仁雄
郑宗烈
李春茂
金圭夏
愼仁范
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Trypan Co ltd
Mai Technology Co ltd
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Mai Technology Co ltd
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Abstract

本发明涉及一种导电性多孔陶瓷基板及其制造方法，更具体而言，涉及一种为了不使用作以真空吸附固定较薄的半导体晶片基板或显示基板的吸盘或载台等的多孔陶瓷基板产生静电而附加有抗静电功能的导电性多孔陶瓷基板及其制造方法。

Description

导电性多孔陶瓷基板及其制造方法
技术领域
本发明涉及一种导电性多孔陶瓷基板及其制造方法，更具体而言，涉及一种为了不使用作以真空吸附固定较薄的半导体晶片基板或显示基板的吸盘或载台等的多孔陶瓷基板产生静电而附加有抗静电功能的导电性多孔陶瓷基板及其制造方法。
背景技术
多孔陶瓷基板在制造半导体的多个制程中主要用作安装、固定半导体晶片或玻璃面板等显示基板的吸盘(根据制造公司而称为“吸盘”或“载台”)，除此之外，作为使用于作为水处理用气泡产生装置的通气管、热交换器、水处理用分离膜、气体分离膜及各种支撑体等的基板，在以各种陶瓷原材料粉末作为主原料而成形为吸盘或载台形状后，在高温下烧结而制造。在这种多孔陶瓷基板的主体形成有无数个供空气通过的微小孔隙或可供水通过的程度的孔隙，从而可利用真空来吸附固定安装到上部的被加工物，或者用作使水等液体通过的分离膜。
另一方面，在多孔陶瓷基板用作半导体晶片固定用吸盘的情况下，吸附固定在作为绝缘体的多孔陶瓷基板上的半导体晶片分离而产生少量的摩擦静电，以往，半导体晶片的厚度厚至几乎不受这种静电的影响的程度而几乎不发生因静电引起的不良，因此未产生较大问题。
然而，最近因智能手机、智能电视(Television，TV)等电子产品逐渐轻量化、纤薄化的趋势而使用于这些电子产品的半导体晶片与各种显示基板的厚度也逐渐变薄且尺寸也逐渐大面积化，印刷到这些电子产品上的图案微小化，因此频繁地产生在将半导体晶片及显示基板安装到多孔陶瓷基板上或从所述多孔陶瓷基板分离的过程中产生的静电使集成在半导体晶片与显示基板上的半导体元件等电子零件带电而导致发生印刷图案短路等不良，或者在从吸盘分离晶片与显示基板的过程中因静电而晶片产生龟裂等问题，因此实情为需要一种具有抗静电功能的多孔陶瓷基板。
如上所述，为了解决因以往在半导体加工装置中的吸盘或载台产生的静电引起的问题，在韩国公开专利第10-2010-0109098号(以下，称为“现有发明1”)及韩国公开专利第10-2010-0121895号(以下，称为“现有发明2”)中开发出一种具有抗静电功能的吸盘或载台。
现有发明1的目的在于提供一种作业载台，将在载台的与基板接触的面产生的静电最小化，并且制造费用减少，可适当地调节面电阻，摩擦系数较低且耐磨耗性提高。为此，现有发明1的特征在于：如图1所示，在金属材料的载台上具备碳纳米管涂覆膜25。
然而，在现有发明1中，主体本身包括铝等金属材料而并非多孔陶瓷，经由另外的涂覆制程对主体表面涂布带有导电性的碳纳米管涂覆膜来实现抗静电。因此，现有发明1产生如下问题：制作制程复杂，需要较多的制作费用，如果涂覆在载台主体上的碳纳米管涂覆膜受损，则需更换整个载台。进而，在载台主体的上部表面形成密闭的涂覆膜，因此存在无法利用真空吸附大面积的薄晶片或显示基板的问题。
另一方面，现有发明2的特征在于：如图2所示，包括：基底层11，包含玻璃原材料；以及抗静电层12，在所述基底层上对掺杂有杂质的二氧化钛(TiO2)进行结晶化热处理而使所述基底层具有抗静电功能。
与现有发明1的作业载台相似，在现有发明2中基底主体为玻璃原材料，现有发明2也需经由另外的沉积及热处理制程在玻璃原材料基底层形成抗静电层，因此存在制作制程复杂、需要较多的制作时间及制作费用的问题、以及在抗静电层受损的情况下需更换整个基板的问题，还存在无法进行真空吸附的结构性问题。
日本公开专利公报特开2000-256074号(以下，称为“现有发明3”)的内容如下：为了将多孔陶瓷原材料的热膨胀系数值调节到9×10-6ppm/℃(约20℃至800℃)以下，相对于包括以氧化铝、碳化硅、氧化锆、锆成分为主体的组合物的一种或复合体的组成100wt％，在1wt％至15wt％的范围内添加SiO2、TiO2、CaO、MgO、Li2O、Al2O3、K2O、Na2O、CuO、Cr2O3、CeO2、MnO2、NiO成分中的一种或两种以上作为添加物后在1300℃至1550℃的温度下进行煅烧。
然而，现有发明3的目的在于调节多孔陶瓷的热膨胀系数，而并非调节导电度来赋予抗静电功能。另外，现有发明3的主原料中的氧化铝、氧化锆或锆具有较宽的带隙，故而存在难以通过掺杂添加物来降低导电度的问题。另外，碳化硅存在如下缺点：原料单价昂贵，在制造方法方面而言，也需像真空炉烧结等一样保持非氧化环境，因此制造单价昂贵。
[现有技术文献]
[专利文献]
韩国公开专利公报公开专利第10-2010-0109098号
韩国公开专利公报公开专利第10-2010-0121895号
日本公开专利公报公开编号特开2000-256074号
发明内容
[发明要解决的问题]
本发明是为了解决上述以往技术的问题而提出，本发明的目的在于提供一种通过对作为主原料的陶瓷原材料即氧化钛(TiO2)掺杂添加剂而进行半导体化，由此同时具有导电性及多孔性而在抗静电的同时可实现真空吸附的导电性多孔陶瓷基板及其制造方法。
[解决问题的手段]
为了达成本发明的这种目的，本发明的导电性多孔陶瓷基板的制造方法包括：混合粉末制备步骤，在氧化钛(TiO2)粉末中添加MnCO3粉末、Cr2O3粉末及石墨粉末而进行混合后，进行干燥而制备混合粉末；加压成形步骤，将所述MnCO3、Cr2O3、TiO2及石墨混合粉末放入到模具而施加压力来形成成形体；以及烧结步骤，在大气中的空气环境下以1000℃以上且1300℃以下的温度对在所述加压成形步骤中成形的成形体进行烧结；且所述混合粉末制备步骤在作为主原料的所述TiO2粉末中添加所述MnCO3及Cr2O3粉末，以9∶1的摩尔比混合所述MnCO3与Cr2O3粉末，相对于所述TiO2粉末以5％以上且15％以下的摩尔比混合所混合的所述MnCO3及Cr2O3粉末。
另外，所述导电性多孔陶瓷基板的制造方法：相对于所述MnCO3、Cr2O3及TiO2混合粉末的总量，以5重量％以上且15重量％以下添加所述石墨粉末。
另一方面，为了达成本发明的目的，本发明的导电性多孔陶瓷基板：其微结构的表面为掺杂有Mn、Cr的TiO2－x粒子与(Mn、Cr)TiO3粒子彼此邻接而形成孔隙，其体积电阻(volume resistance)为106Ω·cm以上至109Ω·cm以下的范围。
另外，所述导电性多孔陶瓷基板：所述基板的孔隙率为20％以上且50％以下。
[发明效果]
如上所述的本发明的导电性多孔陶瓷基板具有如下效果：同时具有实现真空吸附的多孔性及实现抗静电的导电性，因此在用作半导体晶片或显示基板的吸盘(或载台)的情况下，不仅可利用真空稳定地吸附大面积的薄半导体晶片或显示基板，而且在安装、分离晶片与显示基板时不产生静电，从而不对印刷在半导体晶片、显示基板的集成电路产生电性影响。
并且，本发明的导电性多孔陶瓷基板也具有如下效果：基板整体具有相同的多孔性及导电性，故而即便在基板上部表面产生刮痕、瑕疵等也无需更换整个基板，仅研磨基板的上部表面即可获得崭新的平坦度，因此寿命长于以往的形成有抗静电涂覆层的吸盘。
另外，根据本发明的导电性多孔陶瓷基板的制造方法，不在特殊气体环境下以2,100℃以上的高温进行烧结，而是可在大气中的空气环境下以1,200℃至1,300℃的低温对陶瓷粉末进行烧结来获得导电性多孔陶瓷基板，因此也可获得可大幅节省烧结所需的能量及烧结时间的环保且经济的效果。
附图说明
图1、图2是表示现有技术的图。
图3是表示本发明的优选实施例的导电性多孔陶瓷基板的微结构的图。
图4(a)和图4(b)是表示n-型半导体及p-型半导体的图。
图5(a)是表示TiO2的结晶结构的图，图5(b)是表示在经掺杂的TiO2中，掺杂物的存在位置的图。
图6是本发明的优选实施例的导电性多孔陶瓷基板的制造方法的顺序图。
图7是表示通过本发明的优选实施例的实验例1的制程制造的陶瓷基板的与烧结温度对应的密度、体积电阻的结果的图。
图8是通过本发明的优选实施例的实验例2的制程制造的陶瓷基板的与MnCO3的添加量对应的体积电阻的曲线图。
图9(a)、图9(b)和图9(c)是表示通过本发明的优选实施例的实验例3的制程制造的陶瓷基板的与烧结温度对应的密度、体积电阻的结果的图。
图10(a)、图10(b)、图10(c)、图10(d)和图10(e)是表示通过本发明的优选实施例的实验例4的制程制造的陶瓷基板的与烧结温度对应的密度、体积电阻的结果的图。
图11是通过本发明的优选实施例的实验例5的制程制造的各陶瓷基板的与MnCO3、Cr2O3混合粉末(按照9∶1混合)的添加量对应的体积电阻的曲线图。
图12是通过本发明的优选实施例的实验例6的制程制造的各陶瓷基板的与石墨粉末的含量对应的孔隙率的曲线图。
图13是表示通过本发明的优选实施例的实验例6的制程制造的各陶瓷基板的微结构的图。
图14是表示通过本发明的优选实施例的实验例7的制程制造的各陶瓷基板的微小结构的图。
具体实施方式
以下内容仅例示发明的原理。因此，虽未在本说明书中明确地进行说明或图示，但本领域技术人员可实现发明的原理而发明包括在发明的概念与范围内的各种装置。另外，应理解，本说明书中所列举的所有附有条件的术语及实施例在原则上仅明确地用于理解发明的概念，并不限制于像这样特别列举的实施例及状态。
上述目的、特征及优点根据与附图相关的以下的详细说明而变得更明确，因此发明所属的技术领域内的普通技术人员可容易地实施发明的技术思想。
以下，参照附图所示的实施例而详细地对本发明的优选实施例的导电性多孔陶瓷基板及其制造方法进行说明。
在进行具体说明前，阐明如下内容：本发明的导电性多孔陶瓷基板主要呈长方体基板形状，用于吸附、固定薄板状的被吸附物的用途，即在半导体设备中称为真空吸盘或载台等，但只要相同地保持组织结构，则其形状及用途可根据用途实现各种变形而使用。
本发明的优选实施例的导电性多孔陶瓷基板作为具有基本上难以利用肉眼确认的微小孔隙的多孔陶瓷基板，与通常的多孔陶瓷基板不同，最大的特征在于具有实现抗静电的导电性而并非为绝缘体。
本发明的优选实施例的导电性多孔陶瓷基板的微结构的表面为掺杂有Mn、Cr的TiO2－x粒子与(Mn、Cr)TiO3粒子彼此邻接而形成孔隙(pore)，其体积电阻为106Ω·cm以上至109Ω·cm以下的范围。
图3是概略性地表示具有导电性的本发明的优选实施例的导电性多孔陶瓷基板的微结构结构的图。如图3所示，呈形成有掺杂有Mn、Cr的TiO2－x及(Mn、Cr)TiO3粒子、空隙即孔隙的结构。
可通过对陶瓷掺杂异种元素进行半导体化，有n-型半导体、p-型半导体两种类型。其为在陶瓷的能带隙之间形成新的能量状态(energy state)的方法。参照图4(a)和图4(b)，通过供体掺杂实现的n-型半导体化在导带(CB，conduction band)正下方形成供体能带Ed，从而存在于供体能带Ed的电子可容易地跳跃到导带CB。另一方面，通过受体掺杂实现的p-型半导体化在价带(Valence band，VB)正上方形成受体能带Ea，从而价带的空穴(Hole)可容易地跳跃到受体能带Ea。如上所述，通过在能带隙之间形成可存在新的电子或空穴的能带，可使电荷载子容易地越过带隙。
像氧化铝(8.7eV)、氧化锆(5.0eV)、锆(5.0eV)、SiO2(9.0eV)一样能带隙非常宽的陶瓷即便通过掺杂形成新的能带，也因带隙本身非常宽而电荷移动非常困难，如上所述的物质成为绝缘体。
因此，需选择具有可通过掺杂使电荷移动的程度的带隙的陶瓷原材料，SiC、TiO2、ZnO、CeO2、SnO2等陶瓷原材料为具有3eV左右的能带隙的代表性的原材料。其中，碳化硅(SiC)的强度、硬度等物理物性非常优异，但存在如下缺点：原料价格昂贵，因其为非氧化物而无法在空气中进行制造制程，为了不氧化而需在非氧化环境下制造。氧化铈(CeO2)与氧化锡(SnO2)的原料价格超高，因此无法大量用于制造多孔陶瓷。另一方面，氧化铈(CeO2)与氧化锌(ZnO)的强度较弱而难以应用于大面积化。
因此，本发明的优选实施例的陶瓷基板采用通过掺杂添加剂进行半导体化而同时具有导电性及多孔性，并且可实现大面积化的氧化钛(TiO2)陶瓷。
参照图5(a)和图5(b)，氧化钛(TiO2)呈共有对钛(Ti)配位有6个氧(O)的扭曲的八面体边角的结构，有锐钛矿(Anatase)、金红石(Rutile)、板钛矿(brookite)3种同质多形体(polymorphs)。氧化钛(TiO2)在本质上具有氧空位(Oxygen vacancy)、填隙型Ti(TiInterstitial)的本征缺陷(Intrinsic defects)，因此其为以TiO2－x的缺陷化学式表示的非化学计量(Non-stoichiometric)化合物。另外，能带隙为3.2eV左右，可根据通过还原环境下的热处理实现的还原程度，或者通过掺杂N实现的还原来减小带隙，由此可调节电阻。然而，如上所述的还原方法需进行还原环境下的热处理，此时必需如使用真空炉等的高价设备及费用较高的制程。
本发明的优选实施例的导电性多孔陶瓷基板为如下基板：不进行还原热处理，通过掺杂添加剂进行半导体化来调节电阻。可通过掺杂原子价数高于Ti4+的Nb5+、V5+、Cr5+或Cr6+的供体(doner)而实现n型半导体化。另外，可通过掺杂原子价数低于Ti4+的Mn2+或Mn3+、Fe2+或Fe3+的受体(acceptor)实现p型半导体化。通过如上所述的掺杂，氧化钛(TiO2)中氧空位(O vacancy)或填隙型Ti3+(Ti3+Interstitial)的浓度增加，如上所述的缺陷作为电荷移动载子发挥作用而导电度增加。
本发明的优选实施例的导电性多孔陶瓷基板的孔隙率优选为20％至50％。其原因在于：如果孔隙率小于20％，则基板的吸入力变小，如果孔隙率为50％以上，则基板的强度变弱。
以下，对具有如上所述的微结构结构及特性的本发明的优选实施例的导电性多孔陶瓷基板的制造方法进行说明。
本发明的优选实施例的导电性多孔陶瓷基板的制造方法包括：混合粉末制备步骤S1，在氧化钛(TiO2)粉末中添加MnCO3粉末、Cr2O3粉末及石墨粉末而进行混合后，进行干燥而制备混合粉末；加压成形步骤S2，将所述MnCO3、Cr2O3、TiO2及石墨混合粉末放入到模具而施加压力来形成成形体；以及烧结步骤S3，在空气环境下以1000℃以上且1300℃以下的温度对在所述加压成形步骤中成形的成形体进行烧结。
此处，所述混合粉末制备步骤S1为如下步骤：在作为主原料的所述TiO2粉末中添加所述MnCO3及Cr2O3粉末，以9∶1的摩尔比混合所述MnCO3与Cr2O3粉末，相对于所述TiO2粉末以5％以上且15％以下的摩尔比混合所混合的所述MnCO3及Cr2O3粉末。
混合粉末制备步骤S1是在TiO2粉末中添加MnCO3粉末、Cr2O3粉末及石墨粉末，利用球磨机进行混合后通过喷雾干燥机进行干燥来制备混合粉末的步骤，优选为在以9∶1的摩尔比混合添加到作为主原料的TiO2粉末的MnCO3粉末、Cr2O3粉末后，按照5％至15％的摩尔比添加到所述TiO2粉末。如果相对于TiO2以5％以下的摩尔比添加MnCO3粉末、Cr2O3粉末，则无法获得实现抗静电的导电性，如果添加15％以上，则在本发明的基板烧结体产生龟裂，因此优选为添加5％至15％的范围的量。
并且，与MnCO3粉末、Cr2O3粉末一并添加到TiO2粉末的石墨粉末发挥在烧结过程中燃烧而形成孔隙的作用，为了获得20％至50％的孔隙率，相对于TiO2、MnCO3、Cr2O3的混合粉末的总量添加5重量％至20重量％。如果相对于TiO2、MnCO3、Cr2O3的混合粉末添加5重量％以下的石墨粉末的量，则孔隙率降至20％以下，从而基板的吸入力变弱而变得难以真空吸附，如果添加20重量％以上，则产生孔隙率变高至50％以上而基板的强度变低的问题，因此优选为以5％至20％的范围添加。
其次，加压成形步骤S2为如下步骤：将经由所述混合粉末制备步骤S1混合的TiO2、MnCO3、Cr2O3及石墨混合粉末放入到模具且施加压力来成形为长方体形状的基板，从而制造成形体。
最后，烧结步骤S3是在大气中的空气环境下以1,200℃至1,300℃的温度对经由所述加压成形步骤S2成形的成形体进行烧结的步骤，与在Ar、N等气体环境下以2,100℃至2,200℃的高温烧结陶瓷材料的情况不同，其是在大气中的空气环境下以1,200℃至1,300℃的温度范围进行烧结。
如上所述，在空气环境下以1,200℃至1,300℃的略低的烧结温度进行烧结，因此大幅减少烧结所需的能量费用，无需另外的烧结气体及真空状态的烧结炉，因此烧结作业的便利性增大。
如上所述，在经过烧结步骤后，在具有1012Ω·cm的电阻的TiO2内部，如氧空位及填隙型Ti(Ti interstitial)的缺陷增加，即电荷移动载子的浓度增加，因此电阻变低。作为一例，Ti3+化合物即Ti2O3具有10-1Ω·cm的电阻，Ti2+化合物即TiO具有10-5Ω·cm的电阻。本发明仅通过掺杂过渡金属来调节电阻而不进行还原热处理，故而难以形成纯相Ti2O3、TiO。一部分Ti以Ti3+的形式存在，因此具有通过Ti4+与Ti3+之间掺杂电子实现的导电机制。
利用通过保护电极(guarded electrode)法测定体积电阻的电阻测定器(TrekResistance meter 152-1)测定电阻。所述测定方法是利用环形端子法探针(152-CR-1)的方式，遵循美国国家标准学会静电放电(American National Standards Institute/Electrostatic Discharge，ANSI/ESD)协会(association)标准中的体积电阻标准即国际电工委员会(International Electrotechnical Commission，IEC)61340-2进行测定。
实验例1
在TiO2中添加原子价数为2价、3价、5价、6价的元素，观察对电阻产生的影响。其中，2价、3价用于测试受体掺杂的效果，5价、6价用于测试供体掺杂的效果。
在将各掺杂物Zn、Li、Nb、Mg、Mn、W、Ni、Co、Cu、Cr、Fe以ZnO、Li2CO3、Nb2O5、MgO、MnCO3、WO3、NiO、CoO、CuO、Cr2O3、Fe2O3的形态分别按照5％的摩尔比添加到TiO2粉末而利用球磨机进行混合后，利用喷雾干燥机进行干燥而形成颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为长方体形状的成形体，然后以900℃至1,350℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷试片。测定试片的密度及体积电阻，从而获得如图7的结果。
整体而言，供体掺杂降低电阻的效果优于受体掺杂，其原因在于：受体添加元素的离子半径相对较大，因此难以使用到TiO2晶格的内部。Ti4+的离子半径为
Figure BDA0002118518110000091
原子价数低于Ti4+的受体的离子半径如下。
Figure BDA0002118518110000092
这些受体的离子半径远远大于Ti4+而难以取代Ti离子的位置，从而形成2次相像或独立地存在，故而判断为无法有助于降低电阻。Mn3+与Fe3+的离子半径与Ti4+相似，因此认为可取代Ti离子的位置，但Mn掺杂的电阻为109Ω·cm、Fe掺杂为1011Ω·cm，因此判断其原因在于：Mn及Fe的价数与烧结温度对应地发生变化。
与此相比，原子价数高于Ti4+的供体的离子半径如下。
Figure BDA0002118518110000093
这些供体的离子半径与Ti4+相似或小于Ti4+，因此取代Ti离子的位置而增加如氧空位的缺陷的浓度，由此表现出电阻变低的效果。
通过本实验，受体为Mn3+、供体为Cr6+的掺杂最有效。
实验例2
在相对于TiO2而将MnCO3粉末分别以0％、5％、10％、15％的摩尔比添加到TiO2粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为长方体形状的成形体，然后以1,200℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。
测定通过如上所述的制程制造的各陶瓷基板的与MnCO3的添加量对应的体积电阻，从而获得如图8的结果。如图8所示，在相对于TiO2而以5％至15％左右添加MnCO3粉末时，可获得防止静电的109Ω·cm的电阻值。如上所述，可知在仅添加MnCO3粉末的情况下，基板的电阻值略微降低。
实验例3
在相对于TiO2而将MnCO3粉末以5％添加到TiO2粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为成形体，然后以1000℃、1100℃、1200℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。
测定通过如上所述的制程制造的各陶瓷基板的与烧结温度对应的密度、体积电阻，从而获得如图9(a)到图9(c)的结果。如图9(a)到图9(c)所示，在调节烧结温度时，可获得实现抗静电的电阻值(106Ω·cm至109Ω·cm)。
实验例4
在相对于TiO2而将Cr2O3粉末以5％的摩尔比添加到TiO2粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为成形体，然后以1000℃、1100℃、1200℃、1250℃、1350℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。
测定通过如上所述的制程制造的各陶瓷基板的与烧结温度对应的密度、体积电阻，从而获得如图10(a)到图10(e)的结果。如图10(a)到图10(e)所示，在将烧结温度调节为1000℃至1350℃的情况下，可获得实现抗静电的电阻值。
实验例5
在相对于TiO2而将以9∶1的摩尔比混合MnCO3粉末、Cr2O3粉末所得的粉末分别以0％、5％、10％、15％的摩尔比添加到TiO2粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为长方体形状的成形体，然后以1,200℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。
测定通过如上所述的制程制造的各陶瓷基板的与MnCO3、Cr2O3混合粉末(以9∶1混合)的添加量对应的体积电阻，从而获得如下述图11的结果。
如图11所示，可知与仅在TiO2粉末中添加MnCO3粉末的情况相比，在添加以9∶1的比率混合而成的MnCO3、Cr2O3混合粉末时，电阻值更降低。并且，在将以9∶1的比率混合而成的MnCO3、Cr2O3混合粉末以5％至15％添加到TiO2粉末时，可获得实现抗静电的106Ω·cm至109Ω·cm的电阻值。
实验例6
在相对于以85∶13.5∶1.5的摩尔比混合TiO2、MnCO3、Cr2O3粉末所得的粉末而分别以5％、10％、15％及20％添加石墨粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为长方体形状的成形体，然后以1,200℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。
测定通过如上所述的制程制造的各陶瓷基板的与石墨粉末的含量对应的孔隙率，从而获得如图12、图13的结果。如图12、图13所示，可知为了获得在真空吸附及强度方面无任何问题的陶瓷基板的孔隙率即20％至50％的孔隙率，需相对于TiO2、MnCO3、Cr2O3的混合粉末添加5％至20％的范围的量的石墨粉末。
实验例7
在相对于以85∶13.5∶1.5的摩尔比混合TiO2、MnCO3、Cr2O3粉末所得的粉末而以10％添加石墨粉末并利用球磨机进行混合后，利用喷雾干燥机进行干燥而制备颗粒状混合粉末，之后放入到模具而施加600Kgf/cm2的压力来成形为长方体形状的成形体，然后以1,150℃、1300℃的温度在空气环境下对所述成形体进行烧结而制造陶瓷基板。对通过如上所述的制程制造的各陶瓷基板的与烧结温度对应的微小结构进行观察而获得如图14的结果。
在图14中，表现出如下结果：成形体中孔隙的尺寸为约0.1μm至0.5μm，烧结温度越增加，则孔隙的尺寸越大且孔隙的数量越少。在1150℃下烧结的基板的孔隙率为35％，在1300℃下烧结的基板的孔隙率为21％。
如上所述，通过本发明的导电性多孔陶瓷基板的制造方法制造的导电性多孔陶瓷基板的特征在于：具有实现抗静电的电阻值、及可稳定地真空吸附半导体晶片或显示基板的孔隙率及强度。
如上所述，参照本发明的优选实施例进行了说明，但本技术领域内的普通技术人员可在不脱离随附的权利要求中所记载的本发明的思想及领域的范围内对本发明进行各种修正或变形而实施。

Claims (3)

1.一种导电性多孔陶瓷基板的制造方法，其特征在于，包括：
混合粉末制备步骤，在TiO2粉末中添加MnCO3粉末、Cr2O3粉末及石墨粉末而进行混合后，进行干燥而制备混合粉末；
加压成形步骤，将MnCO3、Cr2O3、TiO2及石墨的所述混合粉末放入到模具而施加压力来形成成形体；以及
烧结步骤，在大气中的空气环境下以1000℃以上且1300℃以下的温度对在所述加压成形步骤中成形的所述成形体进行烧结；且
所述混合粉末制备步骤在作为主原料的所述TiO2粉末中添加所述MnCO3粉末及所述Cr2O3粉末，以9∶1的摩尔比混合所述MnCO3粉末与所述Cr2O3粉末，相对于所述TiO2粉末以5％以上且15％以下的摩尔比混合所混合的所述MnCO3粉末及所述Cr2O3粉末，
在所述烧结步骤中，TiO2由MnCO3的Mn3+的受体掺杂及由Cr2O3的Cr6+的供体掺杂来实现半导体化，使得陶瓷基板经所述烧结步骤后的体积电阻为106Ω·cm以上至109Ω·cm以下的范围。
2.根据权利要求1所述的导电性多孔陶瓷基板的制造方法，其特征在于，相对于MnCO3、Cr2O3及TiO2混合粉末的总量，以5重量％以上且15重量％以下添加所述石墨粉末。
3.根据权利要求1所述的导电性多孔陶瓷基板的制造方法，其特征在于，
所述导电性多孔陶瓷基板的孔隙率为20％以上且50％以下。
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