CN110651364B - 具有表面安装裸片支撑结构的半导体装置组合件 - Google Patents

具有表面安装裸片支撑结构的半导体装置组合件 Download PDF

Info

Publication number
CN110651364B
CN110651364B CN201880033499.2A CN201880033499A CN110651364B CN 110651364 B CN110651364 B CN 110651364B CN 201880033499 A CN201880033499 A CN 201880033499A CN 110651364 B CN110651364 B CN 110651364B
Authority
CN
China
Prior art keywords
package element
die support
semiconductor device
package
device assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880033499.2A
Other languages
English (en)
Other versions
CN110651364A (zh
Inventor
B·P·沃兹
B·L·麦克莱恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN110651364A publication Critical patent/CN110651364A/zh
Application granted granted Critical
Publication of CN110651364B publication Critical patent/CN110651364B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05561—On the entire surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14517—Bump connectors having different functions including bump connectors providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种半导体装置组合件。所述组合件包含第一封装元件及安置于所述第一封装元件上方的第二封装元件。所述组合件进一步包含所述第一及第二封装元件之间的多个裸片支撑结构，其中所述多个裸片支撑结构中的每一者具有第一高度、表面安装到所述第一封装元件的下部分及与所述第二封装元件接触的上部分。所述组合件进一步包含所述第一及第二封装元件之间的多个互连件，其中所述多个互连件中的每一者包含具有第二高度的导电柱、导电垫及在所述导电柱与所述导电垫之间具有焊料接头厚度的接合材料。所述第一高度约等于所述焊料接头厚度及所述第二高度的总和。

Description

具有表面安装裸片支撑结构的半导体装置组合件
相关申请案的交叉参考
本申请案含有关于布兰登惠兹(Brandon Wirz)的标题为“具有裸片支撑结构的半导体装置组合件(SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES)”的同时申请的美国专利申请案的标的物，揭示内容以引用方式并入本文中的相关申请案转让给美光科技股份有限公司(Micron Technology,Inc.)且由代理人档案编号10829-9188.US00识别。
技术领域
所揭示实施例涉及具有表面安装裸片支撑结构的半导体装置组合件。在若干实施例中，本技术涉及经配置以机械地支撑定位于堆叠封装元件之间的互连件的表面安装裸片支撑结构。
背景技术
经封装半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于衬底上且围封于塑料保护覆盖物或金属散热片中的半导体裸片。芯片包含功能构件(例如存储器单元、处理器电路及成像器装置)以及电连接到功能构件的接合垫。接合垫可经电连接到保护覆盖物的外部的端子，以允许裸片连接到更高阶电路。在一些封装内，半导体裸片可通过放置于相邻裸片之间的个别互连件而彼此上下堆叠且彼此电连接。在这些封装中，每一互连件可包含导电材料(例如，焊料)及相邻裸片的相对表面上的一对接点。例如，金属焊料可经放置于接点之间且经回焊以形成导电接头。
传统焊料接头的一个挑战是其可易于在组装裸片期间断裂。例如，如果在相邻裸片的接合期间施加过大的力，那么焊料接头可被损坏。此可导致开路或跨接头的高电阻抗，或替代地可导致接头直径增加，直到其机械地接触一或多个相邻焊料接头，从而产生电短路。因此，需要在机械上更稳固的半导体装置组合件。
附图说明
图1是根据本技术的实施例的具有互连件及裸片支撑结构的半导体装置组合件的截面图。
图2A到2C是展示根据本技术的实施例配置的互连件及表面安装裸片支撑结构的半导体装置组合件的放大截面图。
图3A及3B是说明根据本技术的选定实施例的处于制造方法中的各种阶段的半导体装置组合件的截面图。
图4A及4B是说明根据本技术的选定实施例的处于制造方法中的各种阶段的半导体装置组合件的截面图。
图5是说明根据本技术的一个实施例的制造半导体装置组合件的方法的流程图。
图6是包含根据本技术的实施例配置的半导体装置组合件的系统的示意图。
具体实施方式
在以下描述中，论述许多具体细节以提供本技术的实施例的彻底及详尽描述。然而，所属领域的技术人员将意识到本发明可在没有一或多个具体细节的情况下实践。在其它例项中，未展示或未详细描述通常与半导体装置相关联的熟知结构或操作，以避免混淆本技术的方面。通常，应理解，除了本文中揭示的那些特定实施例以外的各种其它装置、系统及方法可在本技术的范围内。
如上文所论述，伴随对于增加的机械稳固性的需求增大而持续设计半导体装置。因此，根据本技术的半导体装置组合件的若干实施例可包含裸片支撑结构，所述裸片支撑结构可为组合件的堆叠半导体裸片提供增加的机械稳固性。
本技术的若干实施例涉及半导体装置组合件、半导体封装、包含半导体装置的系统及制造且操作半导体装置的方法。在一个实施例中，一种半导体装置组合件包含第一封装元件及安置于第一封装元件上方的第二封装元件。所述组合件进一步包含第一及第二封装元件之间的多个裸片支撑结构，其中多个裸片支撑结构中的每一者具有第一高度、表面安装到第一封装元件的下部分及与第二封装元件接触的上部分。组合件进一步包含第一及第二封装元件之间的多个互连件，其中多个互连件中的每一者包含具有第二高度的导电柱、导电垫及在导电柱与导电垫之间具有焊料接头厚度的接合材料。第一高度可约等于焊料接头厚度及第二高度的总和。互连件可视情况省略导电柱，使得第一高度可约等于焊料接头厚度。
下文描述具有表面安装裸片支撑结构的半导体装置组合件的实施例。在各种实施例中，表面安装裸片支撑结构可经配置以机械地支撑定位于半导体装置组合件中的堆叠裸片之间或裸片与上方堆叠裸片的衬底或中介层之间的互连件。裸片支撑结构也可视情况经配置以提供相邻封装元件之间(例如，相邻裸片之间或裸片与相邻衬底或中介层之间)的电互连件，或用于通过堆叠裸片传导热的热路径。术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装及/或衬底(例如，中介层、支撑件或其它适合衬底)的组合件。可例如以离散封装形式、条形或矩阵形式及/或晶片面板形式制造半导体装置组合件。术语“半导体装置”通常是指包含半导体材料的固态装置。半导体装置可包含(举例来说)半导体衬底、晶片、面板或从晶片或衬底单粒化的裸片。贯穿本发明，大致在半导体裸片的上下文中描述半导体装置；然而，半导体装置不限于半导体裸片。
术语“半导体装置封装”可指具有并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分地或全部地囊封至少一个半导体装置的外壳或壳体。半导体装置封装也可包含承载一或多个半导体装置且附接到或以其它方式并入到壳体中的中介层衬底。
如本文中所使用，术语“垂直”、“横向”、“上”及“下”可指图中所示的定向的半导体装置组合件视图中的构件的相对方向或位置。例如，“上”或“最上”可指定位为比另一构件更接近页面的顶部的构件。然而，这些术语应广义地解释为包含具有其它定向(例如其中可取决于定向而互换顶部/底部、上方/下方、上面/下面、上/下及左/右的颠倒或倾斜定向)的半导体装置及半导体装置组合件。
图1是根据本技术的实施例配置的具有第一及第二裸片支撑结构102a及102b(统称为“裸片支撑结构102”)的半导体装置组合件100(“组合件100”)的截面图。组合件100包含第一封装元件104a(例如，衬底、中介层或半导体裸片)、第二封装元件104b(例如，衬底、中介层或半导体裸片)(统称为“封装元件104”)及各别地垂直地延伸于封装元件104a及封装元件104b的第一及第二侧108a及108b之间的个别互连件106的阵列。互连件106可各自包含例如第一封装元件104a的第一侧108a上的第一导电构件(例如，导电垫110)、第二封装元件104b的第二侧108b上的第二导电构件(例如，导电柱112)及将导电柱112接合到导电垫110的接合材料114。
裸片支撑结构102经定位于互连件106的阵列的相对侧上的封装元件104的周边区域116中。裸片支撑结构102可各自包含具有表面安装到第一封装元件104a的第一侧108a的下部分及与第二封装元件104b的第二侧108b接触的上部分的结构元件120。结构元件120可为表面安装到第一封装元件104a上的一或多个安装垫118以提供到第一封装元件104a中的其它电路元件的电连接的离散电路元件(例如，电容器、电阻器、电感器、晶体管或类似物)。在另一实施例中，结构元件120可为与封装元件104的其它电路元件电隔离的块体材料或虚拟结构。在下文更详细描述的各种实施例中，裸片支撑结构102经配置以例如在装置制造期间，机械地支撑封装元件104且防止或至少抑制封装元件104的翘曲。
实际上，组合件100可包含比所说明实施例中展示的更大数目的互连件106及/或裸片支撑结构102。例如，组合件100可包含排列于封装元件104之间的数十、数百、数千或更多个互连件106。另外，在各种实施例中，裸片支撑结构102可有间隙地定位于个别互连件106及/或互连件106的群组之间(例如，阵列内的5个、20个、100个或更多个互连件的群组之间)。例如，在一些实施例中，裸片支撑结构102c(以隐藏线展示)可经定位于封装元件104的中心附近的中间区域124之间。在其它实施例中，裸片支撑结构102可经定位于封装元件104之间的各种其它位置处。
如图1中所进一步展示，封装元件104中的每一者包含半导体衬底126(例如，硅衬底、砷化镓衬底、有机层压衬底等)及从封装元件104的第一侧108a延伸通过衬底126到第二侧108b的导电元件(例如，贯穿硅通路、贯穿模制通路或连接封装衬底或中介层的前侧及背侧的其它导电部件)128。导电元件128耦合到对应互连件106。在一些实施例中，导电元件128可耦合到衬底垫130或定位于半导体衬底126的任一侧上的其它导电构件。
每一衬底126可包含耦合到衬底垫130及/或导电元件128中的一或多者的集成电路132(示意性地展示)。集成电路132可包含例如存储器电路(例如，动态随机存储器(DRAM))、控制器电路(例如，DRAM控制器)、逻辑电路及/或其它电路。在一些实施例中，组合件100可包含其它结构及构件(例如沉积或以其它方式形成在封装元件104周围及/或之间的底部填充材料(未展示))。在图1中所说明的实施例中，组合件100包含两个封装元件104。然而，实际上，组合件100可包含不同数目个封装元件(例如衬底上方的两个裸片、中介层上方的三个裸片、四个裸片、八个裸片、十六个裸片或更多)。例如，在另一实施例中，组合件100可包含第二封装元件104b上的第三封装元件104c(例如，以隐藏线展示的半导体裸片)。在一些实施例中，组合件100可包含将封装元件104围封于包壳内的壳体(未展示)(例如导热壳体)。在这些及其它实施例中，组合件100可包含经配置以将其它封装元件104b及104c可操作地耦合到外部电路(未展示)的支撑衬底(例如，封装元件104a)(例如中介层及/或印刷电路板)。半导体裸片可以类似于图1中所说明的方式类似地与此支撑衬底或中介层间隔开且由表面安装于支撑衬底或中介层上的裸片支撑结构102支撑。
图2A是展示根据本技术的实施例配置的若干互连件106及裸片支撑结构102a的放大截面图。参考图2A，裸片支撑结构102a包含具有表面安装到第一封装元件104a的第一侧108a的下部分120a及与第二封装元件104b的第二侧108b接触的上部分120b的结构元件120。可使用接合材料122(例如，焊料)将结构元件120表面安装到第一封装元件104a上的一或多个安装垫118。互连件106的导电垫110可耦合到形成于第一封装元件104a的第一侧108a上的第一再分布结构265a或形成经形成于第一封装元件104a的第一侧108a上的第一再分布结构265a的部分。导电柱112可耦合到形成于第二封装元件104b的第二侧上的第二再分布结构265b或形成经形成于第二封装元件104b的第二侧上的第二再分布结构265b的一部分。再分布结构265中的每一者可包含各种导电构件233及经配置以提供导电构件233之间的电隔离的钝化材料236(例如，氧化物材料)。导电构件233可包含例如耦合到互连件106、衬底垫130(图1)、导电元件128等中的一或多者的个别金属迹线及/或垫。
图2B是甚至更详细地展示根据本技术的一个方面的互连件106中的一者的进一步放大截面图。互连件106的导电柱112包含通过接合材料114附接到导电垫110的端部。互连件106也可包含形成于导电柱112的端部上方的第一势磊材料255(例如，镍、镍基金属间化合物及/或金)，及形成于导电垫110上方的第二势磊材料253(例如，镍、镍基金属间化合物及/或金)。势磊材料可促进接合及/或防止或至少抑制用于形成导电柱112及导电垫110的铜或其它金属的电迁移。接合材料114桥接导电柱112与导电垫110之间的间隙g1(所属领域的技术人员也已知为焊料接头厚度)。焊料接头厚度g1至少部分由导电柱112从第二封装元件104b的第二侧108b的第一突出高度d1指定。
图2C是甚至更详细地展示图2A的裸片支撑结构102a的进一步放大截面图。结构元件120以第二高度d2延伸于安装垫118上方，所述第二高度d2近似界定第一及第二封装元件104之间的间隔。就此来说，第二高度d2近似等于焊料接头厚度g1与个别互连件106的导电柱112的第一高度d1的总和。
根据本技术的一个方面，提供具有经配置以机械地支撑封装元件104的裸片支撑结构102的装置组合件100简化且改进制造装置组合件100的良率。就此来说，在封装元件之间形成互连件的一个挑战是封装元件可具有固有量的翘曲(例如，裸片翘曲)，所述翘曲可在封装元件之间的互连件上产生拉力及/或压缩力。在缺少裸片支撑结构的情况中，这些力可在装置的组装期间损坏互连件、拉开互连件(例如，拉力)且导致开路、或过度地压缩互连件(例如，压缩力)且导致来自相邻互连件的接合材料相接且产生短路。通过在封装元件的周边区域116周围(例如，且视情况在中间区域124中)提供裸片支撑结构102，热压缩接合操作可用于通过将封装元件104压缩在一起，直到每一裸片支撑结构102的结构元件120的上部分120b与第二封装元件104b的第二侧108b接触而迫使封装元件104成平行平面对准。在裸片支撑结构102确保封装元件104的平行平面对准的情况下，互连件106的焊料接头厚度g1可(例如，通过将互连件106的导电柱112的第一高度d1选择为比裸片支撑结构102的结构元件120的第二高度d2小所要量的焊料接头厚度g1)经准确地压缩到所要范围内。不仅在添加到堆叠的最上封装元件中，而且在可以其它方式在其焊料连接的非有意回焊期间经受翘曲的堆叠中的每个封装元件中，压缩接合操作可通过迫使封装元件成平行平面对准而抵消封装元件104中的任何固有翘曲(例如，裸片翘曲)。
根据本技术的另一方面，裸片支撑结构102的机械强度可允许热压缩接合操作以利用力反馈作为用于操作的控制机构，而非z维偏移，这可进一步简化且改进接合操作的质量。例如，在热压缩接合操作期间，在回焊裸片支撑结构102及互连件106中的接合材料时，可将力施加到两个或两个以上封装元件的堆叠，使得裸片支撑结构102的结构元件120的上部分120b与第二封装元件104b的第二侧108b接触，且因此确定对力的经测量阻力增加。对经施加压缩力的阻力的经测量增加可用于确定导电柱112与导电垫110之间的焊料接头厚度g1因此已(例如，归因于导电柱112的高度d1与裸片支撑结构102的结构元件120的高度d2之间的预定差异)减小到已知范围内。如所属领域的技术人员将易于了解，测量此接合操作中对压缩力的阻力是比维持跨接合轮廓的z维移动简单得多的工程挑战。
例如，图3A及3B是说明根据本技术的选定实施例的处于制造方法中的各种阶段的半导体装置组合件100的截面图。在图3A中，说明在热压缩接合操作开始时的组合件100，其中加热已导致互连件106中的接合材料114各别地回焊且电连接导电柱112及导电垫110的第一及第二势磊材料255及253。在施加压缩力之前，裸片支撑结构102的结构元件120的上部分120b不与第二封装元件104b的第二侧108b接触，且由互连件106的接合材料114桥接的间隙g1(例如，焊料接头厚度)仍大于所要最终量。
在图3B中，说明在热压缩接合操作完成时的组合件100，其中压缩力及经施加热已导致裸片支撑结构102的结构元件120的上部分120b接触第二封装元件104b的第二侧108b，使得由互连件106的接合材料114桥接的间隙g1(例如，焊料接头厚度)在所要范围内。在冷却之后，接合材料114将封装元件104a及104b固化且固定在压缩操作已迫使其所成的平行平面对准(例如，克服任何固有翘曲)中。
尽管在图1到3B中所说明的实施例中，互连件106经说明为包含从封装元件104中的一者突出的柱(例如，使得焊料接头厚度g1可特性化为约等于裸片支撑结构的结构元件120的高度d2与导电柱的高度d1之间的差)，但在其它实施例中，封装元件之间的互连件可具有数个不同结构中的任一者(包含省略导电柱的结构)。例如，图4A及4B说明其中半导体裸片与支撑衬底之间(例如，或两个半导体裸片之间)的互连件是由导电垫上的简单焊料凸块形成(例如，省略前述实施例的柱)的实施例。在此布置中，互连件的焊料接头厚度可约等于裸片支撑结构的高度。
转到图4A，说明在热压缩接合操作开始时的半导体装置组合件400，其中热已导致互连件406中的焊料凸块413及414各别地回焊且电连接上导电垫412及下导电垫410。在施加压缩力之后，裸片支撑结构402的结构元件420的上部分420b不与上半导体裸片404b的第二侧408b接触，且由互连件406的接合材料413及414桥接的间隙g2(例如，焊料接头厚度)仍大于所要最终量。
在图4B中，说明在热压缩接合操作完成时的组合件400，其中压缩力已导致裸片支撑结构402的结构元件420的上部分420b接触上半导体裸片404b的第二侧408b，使得由互连件406的组合接合材料415桥接的间隙g2(例如，焊料接头厚度)在所要范围内。在冷却之后，接合材料415使上半导体裸片404b及下支撑衬底404a(例如，或中介层或半导体裸片)固化且固定在压缩操作已迫使其所成的平行平面对准(例如，克服任何固有翘曲)中。如参考图4B可见，裸片支撑结构402的结构元件420的高度d3约等于上半导体裸片404b与下支撑衬底404a之间的距离，在其中裸片由焊料凸块接合互连的此实施例中，所述距离也约等于焊料接头厚度g2。
根据本技术的一个方面，在晶片或面板上包含裸片支撑结构允许裸片堆叠的晶片或面板级组装，而不经历在传统晶片或面板级组装操作中由裸片翘曲缺陷导致的良率的减小。就此来说，晶片或面板上的裸片支撑结构的布置可经选择以平衡对翘曲减轻的需求与专用于裸片支撑结构的面积(real estate)量。在一个实施例中，可通过利用电作用裸片支撑结构替代其它电路元件(例如，通过利用表面安装电容器作为裸片支撑元件，所述裸片支撑元件另外将消耗半导体封装中的其它处(例如靠近裸片堆叠的支撑衬底上)的表面积)而非使用在裸片的电路中不提供电功能的虚设(例如，电隔离或非作用)裸片支撑结构来减轻归因于包含裸片支撑结构的可使用裸片面积的损失。所属领域的技术人员将易于了解，使用离散电路元件作为裸片支撑结构将确定表面安装裸片支撑结构所需的安装垫的数目(例如，两个安装垫用于两端子元件、三个安装垫用于三端子元件等)。
根据本技术的另一方面，使用大于互连件106(例如，具有大于互连件106的宽度)的裸片支撑结构102的一个好处是裸片支撑结构102可提供以抵抗压缩力的改进机械支撑(例如，裸片支撑结构102更机械稳固且可在热压缩接合操作期间更好地承受压缩力)。
图5是说明根据本技术的一个方面的用于制造半导体装置的方法的流程图。方法包含提供包含多个表面安装裸片支撑件及多个导电垫的第一封装元件(例如，支撑衬底、中介层或半导体裸片)(框510)且将第二封装元件(例如，支撑衬底、中介层或半导体裸片)安置于第一封装元件上方(框520)。第二封装元件包含多个导电元件，各自通过接合材料而与多个导电垫中的对应者分离。方法进一步包含回焊接合材料(框530)且施加力以将第一封装元件及封装元件裸片压缩在一起，使得裸片支撑结构中的每一者接触第二封装元件(框540)。当施加力时，方法进一步包含测量第一及第二封装元件的相对移动，以确定何时已使裸片支撑结构与第二封装元件接触(框550)。
上文参考图1到5所描述的裸片支撑结构及/或半导体装置组合件中的任一者可经并入到无数的更大及/或更复杂系统中的任一者中，其的代表性实例是图6中示意性地展示的系统690。系统690可包含半导体装置组合件600、电源692、驱动器694、处理器696及/或其它子系统或组件698。半导体装置组合件600可包含大致类似于上文所描述的半导体装置组合件的那些构件的构件，且可因此包含用于机械地支撑定位于组合件的堆叠半导体裸片之间的互连件的裸片支撑结构。所得系统690可执行多种功能(例如存储器存储、数据处理及/或其它适合功能)中的任一者。因此，代表性系统690可包含(不限于)手持式装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、车辆或其它机器及器具。系统690的组件可容纳于单个单元中或(例如，通过通信网络)分布遍及多个互连单元。系统690的组件也可包含远程装置及多种计算机可读媒体中的任一者。
从前文，将了解为了阐释目的已在本文中描述技术的特定实施例，但可在不偏离本发明的情况下作出各种修改。此外，尽管已在那些实施例的上下文中描述与新技术的特定实施例相关联的优点，但其它实施例也可展示这些优点，且并非所有实施例一定需要展现这些优点以落于本技术的范围内。因此，本发明及相关技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (16)

1.一种半导体装置组合件，其包括：
第一封装元件；
第二封装元件，其经安置于所述第一封装元件上方；
多个裸片支撑结构，其在所述第一及第二封装元件之间，其中所述多个裸片支撑结构中的每一者具有第一高度、表面安装到所述第一封装元件的下部分及与所述第二封装元件接触的上部分；及
多个互连件，其在所述第一及第二封装元件之间，其中所述多个互连件中的每一者包含具有第二高度的导电柱、导电垫及在所述导电柱与所述导电垫之间具有焊料接头厚度的接合材料，
其中所述第一高度约等于所述焊料接头厚度及所述第二高度的总和，且
其中所述多个裸片支撑结构中的至少一者包含电连接到所述第一封装元件中的其它电路元件的离散电容器。
2.根据权利要求1所述的半导体装置组合件，其中所述多个裸片支撑结构包含围绕所述半导体装置组合件的周边安置的裸片支撑结构。
3.根据权利要求1所述的半导体装置组合件，其中所述多个裸片支撑结构包含安置于所述半导体装置组合件的中间区域中的裸片支撑结构。
4.根据权利要求1所述的半导体装置组合件，其中所述多个裸片支撑结构中的每一者经表面安装到所述第一封装元件上的一或多个安装垫。
5.根据权利要求1所述的半导体装置组合件，其中所述第一封装元件包括逻辑裸片，且其中所述第二封装元件包括存储器裸片。
6.根据权利要求1所述的半导体装置组合件，其中所述第一封装元件包括支撑衬底，且其中所述第二封装元件包括逻辑裸片。
7.一种半导体装置组合件，其包括：
第一封装元件；
第二封装元件，其经安置于所述第一封装元件上方，所述第二封装元件包括多个导电构件及经配置以提供所述导电构件之间的电隔离的钝化材料；
多个裸片支撑结构，其在所述第一封装元件及所述第二封装元件之间，其中所述多个裸片支撑结构中的每一者是整体结构，所述整体结构具有第一高度、安装到所述第一封装元件的下表面及与所述第二封装元件的所述钝化材料直接接触的上表面，且所述整体结构与所述半导体装置组合件的其它电路元件电隔离；及
多个互连件，其在所述第一封装元件及所述第二封装元件之间，其中所述多个互连件中的每一者包含所述第一封装元件上的第一导电元件、所述第二封装元件的所述多个导电构件中的一者上的第二导电元件及在所述第一导电元件及所述第二导电元件之间的接合材料，
其中所述多个裸片支撑结构中的每一者具有比所述多个互连件中的每一者更大的宽度，且
其中所述多个裸片支撑结构中的至少一者包括电连接到所述第一封装元件中的其它电路元件的离散电容器。
8.根据权利要求7所述的半导体装置组合件，其中所述多个裸片支撑结构包含围绕所述半导体装置组合件的周边安置的裸片支撑结构。
9.根据权利要求7所述的半导体装置组合件，其中所述多个裸片支撑结构包含安置于所述半导体装置组合件的中间区域中的裸片支撑结构。
10.根据权利要求7所述的半导体装置组合件，其中所述多个裸片支撑结构中的每一者经表面安装到所述第一封装元件上的一或多个安装垫。
11.根据权利要求7所述的半导体装置组合件，其中所述第一封装元件包括逻辑裸片，且其中所述第二封装元件包括存储器裸片。
12.根据权利要求7所述的半导体装置组合件，其中所述第一封装元件包括支撑衬底，且其中所述第二封装元件包括逻辑裸片。
13.一种制造半导体装置组合件的方法，其包括以下步骤：
将第二封装元件安置于第一封装元件上方，所述第一封装元件包含多个表面安装裸片支撑结构及多个导电垫，所述第二封装元件包含多个导电元件，其中所述多个导电元件中的每一者通过接合材料而与所述多个导电垫中的对应者分离；
回焊所述接合材料；及
使所述第一封装元件及所述第二封装元件中的至少一者朝向彼此移动，使得所述多个表面安装裸片支撑结构中的每一者接触所述第二封装元件，且其中所述多个表面安装裸片支撑结构中的至少一者包括电连接到所述第一封装元件中的其它电路元件的离散电容器。
14.根据权利要求13所述的方法，其进一步包括以下步骤：
测量所述第一封装元件及所述第二封装元件朝向彼此的所述移动，以确定所述多个表面安装裸片支撑结构何时已与所述第二封装元件接触。
15.根据权利要求13所述的方法，其进一步包括以下步骤：
在所述表面安装裸片支撑结构接触所述第二封装元件之后固化所述接合材料。
16.根据权利要求13所述的方法，其中所述多个导电元件包含从所述第二封装元件延伸的导电柱。
CN201880033499.2A 2017-05-23 2018-04-25 具有表面安装裸片支撑结构的半导体装置组合件 Active CN110651364B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/603,327 2017-05-23
US15/603,327 US10950568B2 (en) 2017-05-23 2017-05-23 Semiconductor device assembly with surface-mount die support structures
PCT/US2018/029415 WO2018217389A1 (en) 2017-05-23 2018-04-25 Semiconductor device assembly with surface-mount die support structures

Publications (2)

Publication Number Publication Date
CN110651364A CN110651364A (zh) 2020-01-03
CN110651364B true CN110651364B (zh) 2023-04-04

Family

ID=64396839

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880033499.2A Active CN110651364B (zh) 2017-05-23 2018-04-25 具有表面安装裸片支撑结构的半导体装置组合件

Country Status (4)

Country Link
US (2) US10950568B2 (zh)
CN (1) CN110651364B (zh)
TW (1) TWI693693B (zh)
WO (1) WO2018217389A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10950568B2 (en) 2017-05-23 2021-03-16 Micron Technology, Inc. Semiconductor device assembly with surface-mount die support structures
US10825799B2 (en) * 2018-12-19 2020-11-03 Nanya Technology Corporation Semiconductor structure
US11721677B2 (en) * 2018-12-27 2023-08-08 Intel Corporation Microelectronic assemblies having an integrated capacitor
CN110970390B (zh) * 2019-12-12 2021-05-07 南通大学 一种微细间距铜柱晶圆级封装结构及可靠性优化方法
US11289453B2 (en) 2020-02-27 2022-03-29 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect structure coupled to the substrate
US11227814B2 (en) * 2020-03-16 2022-01-18 Nanya Technology Corporation Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof
US11127632B1 (en) * 2020-03-19 2021-09-21 Nanya Technology Corporation Semiconductor device with conductive protrusions and method for fabricating the same
KR20210125864A (ko) * 2020-04-09 2021-10-19 에스케이하이닉스 주식회사 매립된 솔더의 접합 구조를 구비하는 반도체 패키지
US11309249B2 (en) * 2020-05-04 2022-04-19 Nanya Technology Corporation Semiconductor package with air gap and manufacturing method thereof
KR20220076894A (ko) 2020-12-01 2022-06-08 삼성전자주식회사 지지 부재를 갖는 반도체 패키지
US20240203921A1 (en) * 2021-11-04 2024-06-20 Dyi-chung Hu Semiconductor substrate structure, semiconductor structure and manufacturing method thereof
US11948899B2 (en) * 2021-11-04 2024-04-02 Dyi-chung Hu Semiconductor substrate structure and manufacturing method thereof
WO2023218301A1 (en) * 2022-05-09 2023-11-16 International Business Machines Corporation Electronic structure and method of manufacturing an electronic structure
CN115020396B (zh) * 2022-05-25 2023-08-01 杭州道铭微电子有限公司 一种芯片封装结构及封装方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10227342A1 (de) * 2002-06-19 2004-01-15 Infineon Technologies Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung
CN101681886A (zh) * 2007-06-15 2010-03-24 美光科技公司 半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法
CN104241215A (zh) * 2013-06-14 2014-12-24 日月光半导体制造股份有限公司 半导体封装结构及半导体工艺

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7335995B2 (en) * 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
US6900991B2 (en) * 2001-12-03 2005-05-31 Intel Corporation Electronic assembly with sandwiched capacitors and methods of manufacture
JP4104490B2 (ja) * 2003-05-21 2008-06-18 オリンパス株式会社 半導体装置の製造方法
US6998539B2 (en) * 2003-05-27 2006-02-14 Xerox Corporation Standoff/mask structure for electrical interconnect
WO2005122706A2 (en) 2004-05-31 2005-12-29 Joon-Mo Kang Method of aligning semiconductor device and semiconductor structure thereof
US7312529B2 (en) 2005-07-05 2007-12-25 International Business Machines Corporation Structure and method for producing multiple size interconnections
KR100744151B1 (ko) 2006-09-11 2007-08-01 삼성전자주식회사 솔더 넌-엣 불량을 억제하는 구조의 패키지 온 패키지
US8501534B2 (en) 2008-07-16 2013-08-06 Infineon Technologies Ag Method for housing an electronic component in a device package and an electronic component housed in the device package
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
KR101046394B1 (ko) * 2010-02-03 2011-07-05 주식회사 하이닉스반도체 스택 패키지
KR101692702B1 (ko) * 2010-07-01 2017-01-18 삼성전자주식회사 반도체 패키지 및 이를 제조하는 방법
US8227924B2 (en) * 2010-07-13 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate stand-offs for semiconductor devices
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
US8907469B2 (en) 2012-01-19 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package assembly and method of forming the same
US20130277801A1 (en) * 2012-04-19 2013-10-24 Mediatek Inc. Chip package
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9111912B2 (en) 2013-05-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9559071B2 (en) * 2013-06-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming hybrid bonding structures with elongated bumps
US9437551B2 (en) * 2014-02-13 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Concentric bump design for the alignment in die stacking
KR102237978B1 (ko) 2014-09-11 2021-04-09 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI611486B (zh) * 2014-12-31 2018-01-11 矽品精密工業股份有限公司 半導體結構及其製法
US9607973B1 (en) * 2015-11-19 2017-03-28 Globalfoundries Inc. Method for establishing interconnects in packages using thin interposers
US9553079B1 (en) * 2015-12-15 2017-01-24 International Business Machines Corporation Flip chip assembly with connected component
US10032750B2 (en) * 2016-06-29 2018-07-24 International Business Machines Corporation Integrated DC-DC power converters through face-to-face bonding
US9899313B2 (en) * 2016-07-11 2018-02-20 International Business Machines Corporation Multi terminal capacitor within input output path of semiconductor package interconnect
US10950568B2 (en) 2017-05-23 2021-03-16 Micron Technology, Inc. Semiconductor device assembly with surface-mount die support structures
US10923447B2 (en) 2017-05-23 2021-02-16 Micron Technology, Inc. Semiconductor device assembly with die support structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10227342A1 (de) * 2002-06-19 2004-01-15 Infineon Technologies Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung
CN101681886A (zh) * 2007-06-15 2010-03-24 美光科技公司 半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法
CN104241215A (zh) * 2013-06-14 2014-12-24 日月光半导体制造股份有限公司 半导体封装结构及半导体工艺

Also Published As

Publication number Publication date
WO2018217389A1 (en) 2018-11-29
US20180342476A1 (en) 2018-11-29
US20210193606A1 (en) 2021-06-24
US12087720B2 (en) 2024-09-10
TW201911526A (zh) 2019-03-16
CN110651364A (zh) 2020-01-03
TWI693693B (zh) 2020-05-11
US10950568B2 (en) 2021-03-16

Similar Documents

Publication Publication Date Title
CN110651364B (zh) 具有表面安装裸片支撑结构的半导体装置组合件
US10396059B2 (en) Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US20210167030A1 (en) Semiconductor device assembly with die support structures
US8597981B2 (en) Microelectronic devices and methods for manufacturing microelectronic devices
US8803307B2 (en) Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices
US20150380394A1 (en) Semiconductor packages and methods for fabricating the same
US20050173807A1 (en) High density vertically stacked semiconductor device
CN110692132B (zh) 具有环形中介件的半导体装置组合件
JP4896010B2 (ja) 積層型半導体装置及びその製造方法
US20180114773A1 (en) Semiconductor package and method of fabricating semiconductor package
CN113053858A (zh) 具有扇出边沿的面对面半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant