CN110635769B - Differential low noise amplifier - Google Patents

Differential low noise amplifier Download PDF

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Publication number
CN110635769B
CN110635769B CN201910947133.2A CN201910947133A CN110635769B CN 110635769 B CN110635769 B CN 110635769B CN 201910947133 A CN201910947133 A CN 201910947133A CN 110635769 B CN110635769 B CN 110635769B
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nmos tube
tube
nmos
drain electrode
electrode
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CN110635769A (en
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戴若凡
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The application discloses a differential low noise amplifier belongs to the technical field of electronic circuits. The differential low-noise amplifier comprises an input stage amplifying circuit, an output stage amplifying circuit and a square law circuit, wherein resistors are connected between the source electrodes and the body ends of a differential input main amplifying tube pair in the input stage amplifying circuit; the square law circuit comprises a first PMOS tube and a second PMOS tube, wherein the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are respectively connected with the grid electrodes of the differential input main amplifying tube pair, and the drain electrode of the first PMOS tube is grounded through a load after being connected with the drain electrode of the second PMOS tube; the common ends of the first PMOS tube and the second PMOS tube are respectively connected with the body ends of the differential input main amplifying tube pair through a direct coupling capacitor; the problem that the third-order intermodulation nonlinear distortion is increased due to the source feedback inductance of the differential low-noise amplifier is solved, and the effects of enhancing linearity, improving the input third-order intermodulation cut-off point and improving the dynamic range of the radio frequency front-end system are achieved.

Description

Differential low noise amplifier
Technical Field
The application relates to the technical field of electronic circuits, in particular to a differential low-noise amplifier.
Background
With the development of wireless communication technology, there is also a higher demand for the performance of transceivers. The linearity of the low noise amplifier, which is a key module of the rf receiver, determines the maximum signal strength that the rf receiver can receive. The linearity of the low noise amplifier is increased, which improves the reception range of the radio frequency receiver.
Fig. 1 is a schematic diagram of a conventional source inductance feedback differential low noise amplifier including an input stage amplifying circuit and an output stage amplifying circuit. The input stage amplifying circuit comprises a first NMOS tube M1 and a third NMOS tube M1, a radio frequency input signal RFin+ is connected with the grid electrode of the first NMOS tube M1 through a blocking capacitor Cg1, the radio frequency input signal RFin-is connected with the grid electrode of the third NMOS tube M3 through a blocking capacitor Cg2, the source electrode of the first NMOS tube M1 and the source electrode of the third NMOS tube M3 are grounded through a feedback inductor Ls, the grid electrodes of the first NMOS tube M1 and the grid electrode of the third NMOS tube M3 are connected with a bias voltage Vg through an inductor Lg, and the drain electrodes of the first NMOS tube M1 and the third NMOS tube M3 output amplified signals to the output stage amplifying circuit. The output stage amplifying circuit comprises a second NMOS tube M2 and a fourth NMOS tube M4, wherein the source electrode of the second NMOS tube M2 is connected with the drain electrode of the first NMOS tube M1, the source electrode of the fourth NMOS tube M4 is connected with the drain electrode of the third NMOS tube M3, the grid electrode of the second NMOS tube M2 is connected with a power supply voltage Vdd through a resistor Rg2 and an inductor Ld, the grid electrode of the fourth NMOS tube M4 is connected with the power supply voltage Vdd through a resistor Rg4 and the inductor Ld, the drain electrode of the second NMOS tube M2 is connected with one end of a capacitor Co1, the other end of the capacitor Co2 outputs a radio frequency signal RFout-, and the drain electrode of the fourth NMOS tube M4 is connected with the capacitor Co2 to output a radio frequency signal RFout+.
As can be seen from fig. 1, although the differential structure suppresses the common mode and even nonlinear distortion of the low noise amplifier, the source feedback inductance Ls in the source inductance feedback matching design further performs intermodulation effect on the feedback of even nonlinearity and the gate fundamental wave, and the additional added third-order intermodulation nonlinear distortion is generated in the drain output signals of the first NMOS transistor M1 and the third NMOS transistor M3, which worsens the third-order nonlinearity of the low noise amplifier.
Disclosure of Invention
The application provides a differential low-noise amplifier, which can solve the problem that in the related art, the differential low-noise amplifier is increased in nonlinear distortion of third-order intermodulation due to source feedback inductance.
In one aspect, an embodiment of the present application provides a differential low noise amplifier, including an input stage amplifying circuit, an output stage amplifying circuit, and a square law circuit;
the input stage amplifying circuit comprises a first NMOS tube and a second NMOS tube, wherein the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are signal input ends of the input stage amplifying circuit; the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are output ends of the input stage amplifying circuit; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded through symmetrical tap feedback inductors; the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected with a first bias voltage through symmetrical tap matching bias inductors; a first resistor is connected between the source electrode and the body end of the first NMOS tube, and a second resistor is connected between the source electrode and the body end of the second NMOS tube;
the output stage amplifying circuit comprises a third NMOS tube and a fourth NMOS tube, wherein the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected with the power supply voltage through symmetrical tap load inductors; the grid electrode of the third NMOS tube is connected with the symmetrical tap load inductor through a first bias resistor, the grid electrode of the fourth NMOS tube is connected with the symmetrical tap load inductor through a second bias resistor, and the tap end of the symmetrical tap load inductor is connected with the power supply voltage; the grid electrode of the third NMOS tube is grounded through a first capacitor, and the grid electrode of the fourth NMOS tube is grounded through a second capacitor; the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are the signal output ends of the differential low-noise amplifier;
the square law circuit comprises a first PMOS tube and a second PMOS tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then grounded through a load; the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then is respectively connected with the body end of the first NMOS tube and the body end of the second NMOS tube through a direct coupling capacitor; the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and then is connected with the power supply voltage; the grid electrode of the first PMOS tube is connected with the second bias voltage through the first load resistor, and the grid electrode of the second PMOS tube is connected with the second bias voltage through the second load resistor.
Optionally, in the input stage amplifying circuit, a gate of the first NMOS tube is connected to the radio frequency signal through a first input coupling capacitor, and a gate of the second NMOS tube is connected to the radio frequency signal through a second input coupling capacitor;
in the output stage amplifying circuit, the drain electrode of the third NMOS tube is connected with one end of a first output coupling capacitor, the other end of the first output coupling capacitor is a signal output end, the drain electrode of the fourth NMOS tube is connected with one end of a second output coupling capacitor, and the other end of the second output coupling capacitor is a signal output end;
the radio frequency signal is a differential signal.
Optionally, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor through a third capacitor, and the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor through a fourth capacitor.
Optionally, a source electrode of the first NMOS tube is connected with a first end of the symmetrical tap feedback inductor, a source electrode of the second NMOS tube is connected with a second end of the symmetrical tap feedback inductor, and a third end of the symmetrical tap feedback inductor is grounded;
the grid electrode of the first NMOS tube is connected with the first end of the symmetrical tap matching bias inductor, the grid electrode of the second NMOS tube is connected with the second end of the symmetrical tap matching bias inductor, and the third end of the symmetrical tap matching bias inductor is tapped with the first bias voltage;
the drain electrode of the third NMOS tube is connected with the first end of the symmetrical tap load inductor, the drain electrode of the fourth NMOS tube is connected with the second end of the symmetrical tap load inductor, the grid electrode of the third NMOS tube is connected with the first end of the symmetrical tap load inductor through the first bias resistor, the grid electrode of the fourth NMOS tube is connected with the second end of the symmetrical tap load inductor through the second bias resistor, and the third end of the symmetrical tap load inductor is connected with the power supply voltage.
Optionally, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor through a third capacitor, and the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor through a fourth capacitor.
Optionally, the load is an adjustable load, and the load is used for compensating the phase and adjusting the amplitude of the second-order intermodulation injected into the first NMOS transistor and the second NMOS transistor substrate.
Optionally, the load is formed by connecting a fifth NMOS tube in parallel with a fifth capacitor;
the drain electrode and the source electrode of the fifth NMOS tube are respectively connected with a fifth capacitor, and the grid electrode of the fifth NMOS tube is connected with the drain electrode;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then connected with the drain electrode of the fifth NMOS tube and the common end of the fifth capacitor;
the source of the fifth NMOS tube is grounded to the common ground of the fifth capacitor.
Optionally, the load is an adjustable load, and the voltage amplitude of the second-order intermodulation item IM2 injected into the first NMOS tube and the second NMOS tube substrate is adjusted by adjusting the width-to-length ratio of the fifth NMOS tube.
Optionally, the first resistor and the second resistor are used for keeping the same potential of direct current and generating alternating current blocking and substrate bias effects.
The technical scheme of the application at least comprises the following advantages:
the embodiment of the application provides a differential low noise amplifier, this differential low noise amplifier is source inductance feedback full differential structure, increase square law circuit in this differential low noise amplifier, square law circuit comprises parallelly connected summation differential tube to first PMOS pipe and second PMOS pipe, including differential input main amplifier tube to first NMOS pipe and second NMOS pipe in the input stage amplifier circuit, the grid of first PMOS pipe is connected with the grid of first NMOS pipe, the grid of second PMOS pipe is connected with the grid of second NMOS pipe, square law circuit's output is connected respectively with the body end of first NMOS pipe through blocking coupling capacitor, the body end of second NMOS pipe, square law circuit's output is through load ground with the second order intermodulation of square law circuit output injection differential input main amplifier tube pair's body end, all be connected with the resistance between the source and the body end of first NMOS pipe and second NMOS pipe in the input stage amplifier circuit, direct current equipotential, alternating current blocking and substrate bias effect have been realized through this resistance, the effect of enhancing the third order intermodulation effect on third order differential input system's low-order intermodulation noise has been effectively eliminated, the linear cut-off range of IIP has been improved, IIP dynamic range has been improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional source inductance feedback differential low noise amplifier in the prior art;
fig. 2 is a schematic structural diagram of a differential low noise amplifier according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a portion of a differential low noise amplifier according to an embodiment of the present application;
FIG. 4 is a schematic circuit diagram of a differential low noise amplifier provided in an embodiment of the present application;
fig. 5 is a diagram illustrating a comparison of IIP3 of an existing differential low noise amplifier with IIP3 of a differential low noise amplifier provided in an embodiment of the present application according to an exemplary embodiment.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The embodiment of the application provides a differential low-noise amplifier, which comprises an input stage amplifying circuit, an output stage amplifying building circuit and a square law circuit. The input stage amplifying circuit is connected with the output stage amplifying circuit, and the square law circuit is connected with the input stage amplifying circuit. As shown in fig. 2, the input stage amplifying circuit includes a first NMOS transistor M1 and a second NMOS transistor M3, where the first NMOS transistor M1 and the second NMOS transistor M3 are a differential input main amplifying transistor pair. The output stage amplifying circuit comprises a third NMOS tube M2 and a fourth NMOS tube M4. The square law circuit comprises a first PMOS tube M5 and a second PMOS tube M6, and the first PMOS tube M5 and the second PMOS tube M6 form a parallel summation differential tube pair.
The grid electrode of the first NMOS tube M1 and the grid electrode of the second NMOS tube M3 are signal input ends of an input stage amplifying circuit, the grid electrode of the first NMOS tube M1 is connected with a radio frequency signal RFin+ through a first input coupling capacitor Cg1, and the grid electrode of the second NMOS tube M3 is connected with the radio frequency signal RFin-through a second input coupling capacitor Cg3, and the radio frequency signal RFin+ and the radio frequency signal RFin-are differential signals.
The source electrode of the first NMOS tube M1 and the source electrode of the second NMOS tube M3 are grounded through a symmetrical tap feedback inductor Ls. Specifically, a source of the first NMOS transistor M1 is connected to a first end of the symmetrical tap feedback inductor Ls, a source of the second NMOS transistor M3 is connected to a second end of the symmetrical tap feedback inductor Ls, and a third end of the tap feedback inductor Ls is grounded.
A first resistor Rb1 is connected between the source and the body of the first NMOS transistor M1, and a second resistor Rb2 is connected between the source and the body of the second NMOS transistor M3. The first resistor Rb1 and the second resistor Rb2 are used to maintain the same dc potential and to generate ac blocking and substrate bias effects.
The first resistor Rb1 and the second resistor Rb2 are large resistors. Optionally, the resistance of the first resistor Rb1 and the resistance of the second resistor Rb2 are both greater than or equal to 5kΩ. The specific values of the resistance value of the first resistor Rb1 and the resistance value of the second resistor Rb2 are also determined according to the circuit area and the performance of the differential low noise amplifier, which is not limited in this application.
The grid electrode of the first NMOS tube M1 and the grid electrode of the second NMOS tube M3 are connected with a first bias voltage Vgbias1 through a symmetrical tap matching bias inductance Lg. Specifically, a gate of the first NMOS transistor M1 is connected to a first end of the symmetrical tap matching offset inductor Lg, a gate of the second NMOS transistor M3 is connected to a second end of the symmetrical tap matching offset inductor Lg, and a third end of the symmetrical tap matching offset inductor Lg is connected to the first offset voltage Vgbis1.
The drain electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M3 are output ends of the input stage amplifying circuit.
The source electrode of the third NMOS tube M2 is connected with the drain electrode of the first NMOS tube M1, and the source electrode of the fourth NMOS tube M4 is connected with the drain electrode of the second NMOS tube M3.
The drain electrode of the third NMOS tube M2 and the drain electrode of the fourth NMOS tube M4 are connected with the power supply voltage Vdd through a symmetrical tap load inductance Ld, the grid electrode of the third NMOS tube M2 is connected with the symmetrical tap load inductance Ld through a first bias resistor Rg2, the grid electrode of the fourth NMOS tube M4 is connected with the symmetrical tap load inductance Ld through a second bias resistor Rg4, and the tap end of the symmetrical tap load inductance Ld is connected with the power supply voltage Vdd. Specifically, the drain electrode of the third NMOS transistor M2 is connected to the first end of the symmetrical tap load inductor Ld, the drain electrode of the fourth NMOS transistor M4 is connected to the second end of the symmetrical tap load inductor Ld, the gate electrode of the third NMOS transistor M2 is connected to the first end of the symmetrical tap load inductor Ld through the first bias resistor Rg2, the gate electrode of the fourth NMOS transistor M4 is connected to the second end of the symmetrical tap load inductor Ld through the second bias resistor Rg4, and the third end tap of the symmetrical tap load inductor Ld is connected to the power supply voltage Vdd.
The gate of the third NMOS transistor M2 is grounded through the first capacitor Cg2, and the gate of the fourth NMOS transistor M4 is grounded through the second capacitor Cg 4. The drain electrode of the third NMOS tube M2 and the drain electrode of the fourth NMOS tube M4 are the signal output ends of the differential low noise amplifier. The drain electrode of the third NMOS tube M2 is connected with one end of a first output coupling capacitor Co1, the other end of the first output coupling capacitor Co1 is a signal output end RFout-, the drain electrode of the fourth NMOS tube M4 is connected with one end of a second output coupling capacitor Co2, and the other end of the second output coupling capacitor Co2 is a signal output end RFout+.
In the square-law circuit, a first PMOS tube M5 and a second PMOS tube M6 are respectively in alternating current coupling with the grid electrodes of a differential input main amplifying tube pair (a first NMOS tube M1 and a second NMOS tube M3), and meanwhile, second-order intermodulation output by the square-law circuit is injected into the body end of the differential input main amplifying tube pair for linearity enhancement.
The grid electrode of the first PMOS tube M5 is connected with the grid electrode of the first NMOS tube M1 through a third capacitor Cg5, and the grid electrode of the second PMOS tube M6 is connected with the grid electrode of the second NMOS tube M3 through a fourth capacitor Cg 6. The drain electrode of the first PMOS tube M5 is connected with the drain electrode of the second PMOS tube M6 and then grounded through a load ZL. The drain electrode of the first PMOS tube M5 is connected with the drain electrode of the second PMOS tube M6, and then is respectively connected with the body end of the first NMOS tube M1 and the body end of the second NMOS tube M3 through a direct coupling capacitor Cac. The source of the first PMOS transistor M5 is connected to the source of the second PMOS transistor M6 and then to the power supply voltage Vdd. The grid electrode of the first PMOS tube M5 is connected with the second bias voltage Vgbias2 through a first load resistor Rg5, and the grid electrode of the second PMOS tube M6 is connected with the second bias voltage Vgbias2 through a second load resistor Rg 6.
The load ZL is an adjustable load, the load ZL is used for compensating the phase, and the amplitude of the second-order intermodulation injected into the substrate of the main amplifying tube (the first NMOS tube M1 and the second NMOS tube M3) is adjusted, so that the influence of second-order intermodulation source feedback on the third-order intermodulation is eliminated in the same reverse direction.
Since the circuit structure of the differential low noise amplifying circuit is symmetrical, a circuit on one side is described, the load ZL acts as an impedance, and as shown in fig. 3, a small signal analysis is performed on the circuit shown in fig. 3.
For a first PMOS tube M5 and a second PMOS tube M6 in the square law circuit:
i dM5 ＝g m5 Vgs+g' m5 Vgs 2 +g” m5 Vgs 3 ；
i dM6 ＝-g m6 Vgs+g' m6 Vgs 2 -g” m6 Vgs 3 ；
i dM5 represents drain current of the first PMOS tube M5, vgs represents bias voltage of small signal, g m5 Represents the transconductance, g 'of the first PMOS tube M5' m5 Representing the transconductance of the first PMOS tube M5, g' m5 The partial conductance of the transconductance of the first PMOS tube M5 is represented; i.e dM6 Represents drain current of the second PMOS tube M6, vgs represents bias voltage of small signal g m6 Represents the transconductance, g 'of the second PMOS tube M6' m6 Representing the transconductance of the second PMOS tube M6, g' m6 And the partial conductance of the transconductance of the second PMOS tube M6 is represented.
Thus, i b ＝i dM5 +i dM6 ＝2g' m Vgs 2 The method comprises the steps of carrying out a first treatment on the surface of the It can be seen that the odd-order nonlinearities cancel and the even-order nonlinearities sum. Generating a voltage V by a load ZL b ，V b ＝i b R ZL The method comprises the steps of carrying out a first treatment on the surface of the I can be obtained dM1 ＝g m1 Vgs+g' m1 Vgs 2 -g' mb1 V b s 2 +...；i dM1 Represents the drain current g of the first NMOS transistor M1 m1 Represents the transconductance, g 'of the first NMOS transistor M1' m1 Represents the transconductance, g ', of the first NMOS transistor M1' mb1 For transconductance of the first resistor Rb1, R ZL The resistance of the load ZL is indicated.
As can be seen from fig. 3, the square law circuit injects the second-order intermodulation into the body end of the main amplifying tube, i.e. the first NMOS tube M1, and the ac path is isolated and blocked due to the existence of the first resistor Rb1, so as to generate a substrate bias effect, and the influence of the second-order intermodulation source feedback on the third-order intermodulation can be effectively eliminated by using the substrate bias effect, so that the linearity of the low-noise amplifier is enhanced, the Input third-order intermodulation (Input two tone 3rd order intercept point,IIP3) is improved, and the dynamic range of the radio frequency front-end system is improved.
In an alternative embodiment based on the embodiment shown in fig. 2, the load ZL is formed by connecting a fifth NMOS tube ML in parallel with a fifth capacitor CL, and as shown in fig. 4, the drain and the source of the fifth NMOS tube ML are respectively connected with the fifth capacitor CL; the gate and drain of the fifth NMOS tube ML are connected, and the fifth NMOS tube is equivalent to a diode.
The drain electrode of the first PMOS tube M5 is connected with the drain electrode of the second PMOS tube M6 and then is connected with the common end of the drain electrode of the fifth NMOS tube ML and the fifth capacitor CL; the source of the fifth NMOS transistor ML is grounded to the common ground of the fifth capacitor CL.
In the embodiment shown in fig. 4, the load ZL formed by connecting the fifth NMOS tube ML in parallel with the fifth capacitor CL is an adjustable load, and is realized by adjusting the width-to-length ratio of the fifth NMOS tube ML. Specifically, the voltage amplitude of the second-order intermodulation products (2nd order two tone intermodulation product,IM2) injected into the substrates of the first NMOS tube M1 and the second NMOS tube M3 is adjusted by adjusting the width-to-length ratio of the fifth NMOS tube ML.
In addition, the fifth capacitor CL and the impedance of the fifth NMOS tube ML form an RC phase compensation structure, so that the IM2 injection compensation in the equal-large reverse direction is ensured.
In one example, for the differential low noise amplifier shown in fig. 1, a third-order intermodulation output curve is obtained, which is shown as an old third-order intermodulation output curve 51 in fig. 5, for the differential low noise amplifier shown in fig. 4, a third-order intermodulation output curve is obtained, which is shown as a new third-order intermodulation output curve 52 in fig. 5, fig. 5 also shows a first-order linear output curve, the intersection point of the old third-order intermodulation output curve 51 and the first-order linear output curve 53 is an old IIP3, the value is 2.1dBm, the intersection point of the new third-order intermodulation output curve 52 and the first-order linear output curve 53 is a new IIP3, the value is 6.3dBm, the IIP3 for measuring linearity is increased by 4.2dBm, that is Δiip3=4.2 dBm, which illustrates that the differential low noise amplifier shown in fig. 4 can effectively improve linearity compared to the differential low noise amplifier shown in fig. 1.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (8)

1. The differential low-noise amplifier is characterized by comprising an input stage amplifying circuit, an output stage amplifying circuit and a square law circuit;
the input stage amplifying circuit comprises a first NMOS tube and a second NMOS tube, wherein the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are signal input ends of the input stage amplifying circuit; the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are output ends of the input stage amplifying circuit; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded through symmetrical tap feedback inductors; the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected with a first bias voltage through symmetrical tap matching bias inductors; a first resistor is connected between the source electrode and the body end of the first NMOS tube, and a second resistor is connected between the source electrode and the body end of the second NMOS tube;
the output stage amplifying circuit comprises a third NMOS tube and a fourth NMOS tube, wherein the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected with a power supply voltage through symmetrical tap load inductors; the grid electrode of the third NMOS tube is connected with the symmetrical tap load inductor through a first bias resistor, the grid electrode of the fourth NMOS tube is connected with the symmetrical tap load inductor through a second bias resistor, and the tap end of the symmetrical tap load inductor is connected with a power supply voltage; the grid electrode of the third NMOS tube is grounded through a first capacitor, and the grid electrode of the fourth NMOS tube is grounded through a second capacitor; the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are the signal output ends of the differential low-noise amplifier;
the square law circuit comprises a first PMOS tube and a second PMOS tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then grounded through a load; the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then is respectively connected with the body end of the first NMOS tube and the body end of the second NMOS tube through a direct coupling capacitor; the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and then connected with the power supply voltage; the grid electrode of the first PMOS tube is connected with the second bias voltage through a first load resistor, and the grid electrode of the second PMOS tube is connected with the second bias voltage through a second load resistor.
2. The differential low noise amplifier according to claim 1, wherein in the input stage amplifying circuit, a gate of the first NMOS transistor is connected to a radio frequency signal through a first input coupling capacitor, and a gate of the second NMOS transistor is connected to a radio frequency signal through a second input coupling capacitor;
in the output stage amplifying circuit, a drain electrode of the third NMOS tube is connected with one end of a first output coupling capacitor, the other end of the first output coupling capacitor is a signal output end, a drain electrode of the fourth NMOS tube is connected with one end of a second output coupling capacitor, and the other end of the second output coupling capacitor is a signal output end;
the radio frequency signal is a differential signal.
3. The differential low noise amplifier of claim 1, wherein a source of the first NMOS transistor is connected to a first terminal of the symmetrical tap feedback inductance, a source of the second NMOS transistor is connected to a second terminal of the symmetrical tap feedback inductance, and a third terminal of the symmetrical tap feedback inductance is tapped to ground;
the grid electrode of the first NMOS tube is connected with the first end of the symmetrical tap matching bias inductor, the grid electrode of the second NMOS tube is connected with the second end of the symmetrical tap matching bias inductor, and the third end of the symmetrical tap matching bias inductor is tapped with a first bias voltage;
the drain electrode of the third NMOS tube is connected with the first end of the symmetrical tap load inductor, the drain electrode of the fourth NMOS tube is connected with the second end of the symmetrical tap load inductor, the grid electrode of the third NMOS tube is connected with the first end of the symmetrical tap load inductor through a first bias resistor, the grid electrode of the fourth NMOS tube is connected with the second end of the symmetrical tap load inductor through a second bias resistor, and the third end tap of the symmetrical tap load inductor is connected with the power supply voltage.
4. The differential low noise amplifier of claim 1, wherein the gate of the first PMOS is connected to the gate of the first NMOS through a third capacitor, and the gate of the second PMOS is connected to the gate of the second NMOS through a fourth capacitor.
5. The differential low noise amplifier of claim 1, wherein the load is an adjustable load for compensating for phase and adjusting the amplitude of the first NMOS transistor and second NMOS transistor substrate injection second order intermodulation.
6. The differential low noise amplifier according to claim 1, wherein the load is constituted by a fifth NMOS transistor connected in parallel with a fifth capacitor;
the drain electrode and the source electrode of the fifth NMOS tube are respectively connected with the fifth capacitor, and the grid electrode of the fifth NMOS tube is connected with the drain electrode;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube and then connected with the drain electrode of the fifth NMOS tube and the common end of the fifth capacitor;
and the common ground of the source electrode of the fifth NMOS tube and the fifth capacitor is grounded.
7. The differential low noise amplifier of claim 6, wherein the load is an adjustable load, and wherein the voltage amplitude of the first NMOS transistor and the second NMOS transistor substrate injection second order intermodulation products IM2 is adjusted by adjusting the aspect ratio of the fifth NMOS transistor.
8. A differential low noise amplifier according to any of claims 1 to 6, wherein said first resistor and said second resistor are adapted to maintain a dc common potential and to produce ac blocking and substrate biasing effects.
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