CN110556415A - 一种高可靠性外延栅的SiC MOSFET器件及其制备方法 - Google Patents
一种高可靠性外延栅的SiC MOSFET器件及其制备方法 Download PDFInfo
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Abstract
本发明公开了一种高可靠性外延栅的SiC MOSFET器件,同时,本发明还提供了一种高可靠性外延栅的SiC MOSFET器件的制备方法。本发明由于绝缘介质栅是通过外延高电阻率的本征SiC得到,与衬底外延SiC晶格常数匹配度高,可以降低SiC MOSFET器件介质层与碳化硅间的界面态密度,从而降低对载流子输运的散射,提高载流子迁移率。SiC的介电常数与SiO2相比较高,可以缓解电场过于集中在栅介质层,同时SiC的临界电场远高于SiO2,所以可以提高SiC MOSFET器件的抗击穿能力和稳定性。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种高可靠性外延栅的SiC MOSFET器件,同时,本发明还涉及一种高可靠性外延栅的SiC MOSFET器件的制备方法。
背景技术
碳化硅(SiC)是一种优异性能的宽禁带半导体,不但具有禁带宽、热导率高、击穿场强高、饱和电子漂移速率高等特点,而且还具有极好的物理及化学稳定性、极强的抗辐照能力和机械强度等。因此,SiC可用于研制高温、大功率、高频功率器件。目前,SiC基MOS功率器件的绝缘介质栅主要是通过热氧化得到的SiO2,热氧化SiC衬底而形成的SiO2层的介电常数和SiC相比较低,使得SiO2内部的场强比SiC衬底高,常常导致SiO2比SiC先被击穿,显示不出SiC材料的优越性。其次、SiO2与SiC衬底之间有较多的界面态,界面态对载流子的散射导致MOS器件沟道的载流子迁移率比SiC体材料低一个数量级,这就需要寻找新的合适的介质层,取代SiO2以提高4H-SiC基MOSFET器件的电子迁移率及可靠性。
发明内容
本发明的目的在于提供一种高可靠性外延栅的SiC MOSFET器件及其制备方法,以解决上述背景技术中提出现有技术中不仅工作效率低下,而且浪费大量人力的问题。
为实现上述目的,本发明采用了如下技术方案:
一种高可靠性外延栅的SiC MOSFET器件的制备方法,包括如下步骤:
S1、选取SiC衬底和SiC外延层,对SiC衬底和SiC外延层进行清洗并且干燥;
S2、在SiC外延层表面上进行铝离子注入,形成P-well阱区;
S3、在P-well阱区上表面进行氮离子注入,形成源极接触n+区域;
S4、在源极接触n+区域上表面进行铝离子注入,形成源极接触P+区域;
S5、对注入的杂质离子进行高温激活;
S6、对高温激活后的SiC衬底和SiC外延层进行表面处理,使SiC外延层上表面干净、平坦,适合进行再次SiC外延;
S7、在SiC外延层上表面进行本征SiC层外延,形成绝缘SiC外延层,以此作为SiCMOSFET器件的绝缘栅介质层;
S8、在绝缘SiC外延层上淀积多晶硅栅极,并且对绝缘SiC外延层和多晶硅栅极光刻、刻蚀,刻蚀出接触孔区域;
S9、绝缘介质层的沉积以及光刻、刻蚀,形成源极接触孔;
S10、源极金属的沉积、光刻刻蚀以及高温合金,与源极接触n+区域和源极接触P+区域形成良好欧姆接触;
S11、晶圆背面漏极金属的沉积以及高温合金,形成SiC MOSFET器件器件结构,完成制备。
优选的,所述步骤S2包括:
S21、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1.5μm的Al作为P-well阱区离子注入的阻挡层,通过光刻和刻蚀形成P-well阱区注入区;
S22、在650℃的温度下对SiC外延层正面进行多次Al离子注入,在P-well阱区注入区形成深度为0.5μm,掺杂浓度为3×1018cm-3的P-well阱区;
S23、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
优选的,所述步骤S3包括:
S31、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1μm的Al作为源极接触n+区域离子注入的阻挡层,通过光刻和刻蚀形成源极接触n+区域注入区;
S32、在500℃的温度下对SiC外延层正面进行多次氮离子注入,在源极接触n+区域注入区形成深度为0.25μm,掺杂浓度为1×1019cm-3的源极接触n+区域;
S33、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
优选的,所述步骤S4包括:
S41、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1.5μm的Al作为源极接触P+区域离子注入的阻挡层,通过光刻和刻蚀形成源极接触P+区域注入区;
S42、在650℃的温度下对SiC外延层正面进行多次Al离子注入,在源极接触P+区域注入区形成深度为0.5μm,掺杂浓度为1×1019cm-3的源极接触P+区域;
S43、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
优选的,所述步骤S5包括:
采用RCA清洗标准对碳化硅表面进行清洗,烘干后制作碳膜保护,然后在1700℃氩气氛围中进行离子激活退火10min。
优选的,所述步骤S6包括:
通过氧等离子体去除碳膜,采用RCA清洗标准对碳化硅表面进行清洗,烘干。
优选的,所述步骤S7包括:
在SiC外延层上表面外延生长厚度为50nm的绝缘SiC外延层,其工艺条件是:外延温度为1600℃,压力100mbar,反应气体采用硅烷和丙烷,载运气体采用纯氢气。
优选的,所述步骤S8包括:
用低压热壁化学气相淀积法在绝缘SiC外延层上表面淀积生长200nm的多晶硅,然后通过光刻、刻蚀保留住栅氧化膜上的多晶硅,形成磷离子掺杂浓度为1×1020cm-3,厚度为200nm的多晶硅栅极,其工艺条件是:淀积温度为600℃,淀积压强为60Pa,反应气体采用硅烷和磷化氢,载运气体采用氦气。
本发明还提供了一种高可靠性外延栅的SiC MOSFET器件,所述高可靠性外延栅的SiC MOSFET器件由以上所述的高可靠性外延栅的SiC MOSFET器件的制备方法制备得到。
本发明的技术效果和优点:
由于绝缘介质栅是通过外延高电阻率的本征SiC得到,与衬底外延SiC晶格常数匹配度高,可以降低SiC MOSFET器件介质层与碳化硅间的界面态密度,从而降低对载流子输运的散射,提高载流子迁移率。SiC的介电常数与SiO2相比较高,可以缓解电场过于集中在栅介质层,同时SiC的临界电场远高于SiO2,所以可以提高SiC MOSFET器件的抗击穿能力和稳定性。
附图说明
图1~10为本发明的一种高可靠性外延栅的SiC MOSFET器件的制备方法的工艺过程的截面结构示意图。
图中:101、SiC衬底;102、SiC外延层;103、P-well阱区;104、源极接触n+区域;105、源极接触P+区域;106、绝缘SiC外延层;106-1、接触孔区域;107、多晶硅栅极;108、绝缘介质层;108-1、源极接触孔;109、源极金属;110、晶圆背面漏极金属。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明提供了一种高可靠性外延栅的SiC MOSFET器件的制备方法,包括如下步骤:
S1、如图1所示,选取SiC衬底101和SiC外延层102,对SiC衬底101和SiC外延层102进行清洗并且干燥;
S2、如图2所示,在SiC外延层102表面上进行铝离子注入,形成P-well阱区103;
S21、通过低压热壁化学气相淀积法在SiC外延层102正面淀积一层厚度为1.5μm的Al作为P-well阱区103离子注入的阻挡层,通过光刻和刻蚀形成P-well阱区103注入区;
S22、在650℃的温度下对SiC外延层102正面进行多次Al离子注入,在P-well阱区103注入区形成深度为0.5μm,掺杂浓度为3×1018cm-3的P-well阱区103如图2所示;
S23、采用磷酸去除SiC外延层102正面的Al,并且清洗干燥;
S3、如图3所示,在P-well阱区103上表面进行氮离子注入,形成源极接触n+区域104;
S31、通过低压热壁化学气相淀积法在SiC外延层102正面淀积一层厚度为1μm的Al作为源极接触n+区域104离子注入的阻挡层,通过光刻和刻蚀形成源极接触n+区域104注入区;
S32、在500℃的温度下对SiC外延层102正面进行多次氮离子注入,在源极接触n+区域104注入区形成深度为0.25μm,掺杂浓度为1×1019cm-3的源极接触n+区域104;
S33、采用磷酸去除SiC外延层102正面的Al,并且清洗干燥;
S4、如图4所示,在源极接触n+区域104上表面进行铝离子注入,形成源极接触P+区域105;
S41、通过低压热壁化学气相淀积法在SiC外延层102正面淀积一层厚度为1.5μm的Al作为源极接触P+区域105离子注入的阻挡层,通过光刻和刻蚀形成源极接触P+区域105注入区;
S42、在650℃的温度下对SiC外延层102正面进行多次Al离子注入,在源极接触P+区域105注入区形成深度为0.5μm,掺杂浓度为1×1019cm-3的源极接触P+区域105;
S43、采用磷酸去除SiC外延层102正面的Al,并且清洗干燥;
S5、对注入的杂质离子进行高温激活,采用RCA清洗标准对碳化硅表面进行清洗,烘干后制作碳膜保护,然后在1700℃氩气氛围中进行离子激活退火10min;
S6、对高温激活后的SiC衬底101和SiC外延层102进行表面处理,通过氧等离子体去除碳膜,采用RCA清洗标准对碳化硅表面进行清洗,烘干,使SiC外延层102上表面干净、平坦,适合进行再次SiC外延;
S7、如图5所示,在SiC外延层102上表面进行本征SiC层外延,在SiC外延层102上表面外延生长厚度为50nm的绝缘SiC外延层106,其工艺条件是:外延温度为1600℃,压力100mbar,反应气体采用硅烷和丙烷,载运气体采用纯氢气,形成绝缘SiC外延层106,以此作为SiC MOSFET器件的绝缘栅介质层;
S8、如图6所示,在绝缘SiC外延层106上淀积多晶硅栅极107,用低压热壁化学气相淀积法在绝缘SiC外延层106上表面淀积生长200nm的多晶硅,然后通过光刻、刻蚀保留住栅氧化膜上的多晶硅,形成磷离子掺杂浓度为1×1020cm-3,厚度为200nm的多晶硅栅极107,其工艺条件是:淀积温度为600℃,淀积压强为60Pa,反应气体采用硅烷和磷化氢,载运气体采用氦气,并且对绝缘SiC外延层106和多晶硅栅极107光刻、刻蚀,刻蚀出接触孔区域106-1;
S9、如图7和图8所示,绝缘介质层108的沉积以及光刻、刻蚀,形成源极接触孔108-1;
S10、如图9所示,源极金属109的沉积、光刻刻蚀以及高温合金,与源极接触n+区域104和源极接触P+区域105形成良好欧姆接触;
S11、如图10所示,晶圆背面漏极金属110的沉积以及高温合金,形成SiC MOSFET器件器件结构,完成制备。
本发明还提供了一种高可靠性外延栅的SiC MOSFET器件,该高可靠性外延栅的SiC MOSFET器件由以上的高可靠性外延栅的SiC MOSFET器件的制备方法制备得到。
综上,由于绝缘介质栅是通过外延高电阻率的本征SiC得到,与衬底外延SiC晶格常数匹配度高,可以降低SiC MOSFET器件介质层与碳化硅间的界面态密度,从而降低对载流子输运的散射,提高载流子迁移率。SiC的介电常数与SiO2相比较高,可以缓解电场过于集中在栅介质层,同时SiC的临界电场远高于SiO2,所以可以提高SiC MOSFET器件的抗击穿能力和稳定性。
最后应说明的是:以上所述仅为本发明的优选实施例而已,并不用于限制本发明,尽管参照前述实施例对本发明进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,包括如下步骤:
S1、选取SiC衬底和SiC外延层,对SiC衬底和SiC外延层进行清洗并且干燥;
S2、在SiC外延层表面上进行铝离子注入,形成P-well阱区;
S3、在P-well阱区上表面进行氮离子注入,形成源极接触n+区域;
S4、在源极接触n+区域上表面进行铝离子注入,形成源极接触P+区域;
S5、对注入的杂质离子进行高温激活;
S6、对高温激活后的SiC衬底和SiC外延层进行表面处理,使SiC外延层上表面干净、平坦,适合进行再次SiC外延;
S7、在SiC外延层上表面进行本征SiC层外延,形成绝缘SiC外延层,以此作为SiCMOSFET器件的绝缘栅介质层;
S8、在绝缘SiC外延层上淀积多晶硅栅极,并且对绝缘SiC外延层和多晶硅栅极光刻、刻蚀,刻蚀出接触孔区域;
S9、绝缘介质层的沉积以及光刻、刻蚀,形成源极接触孔;
S10、源极金属的沉积、光刻刻蚀以及高温合金,与源极接触n+区域和源极接触P+区域形成良好欧姆接触;
S11、晶圆背面漏极金属的沉积以及高温合金,形成SiC MOSFET器件器件结构,完成制备。
2.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S2包括:
S21、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1.5μm的Al作为P-well阱区离子注入的阻挡层,通过光刻和刻蚀形成P-well阱区注入区;
S22、在650℃的温度下对SiC外延层正面进行多次Al离子注入,在P-well阱区注入区形成深度为0.5μm,掺杂浓度为3×1018cm-3的P-well阱区;
S23、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
3.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S3包括:
S31、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1μm的Al作为源极接触n+区域离子注入的阻挡层,通过光刻和刻蚀形成源极接触n+区域注入区;
S32、在500℃的温度下对SiC外延层正面进行多次氮离子注入,在源极接触n+区域注入区形成深度为0.25μm,掺杂浓度为1×1019cm-3的源极接触n+区域;
S33、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
4.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S4包括:
S41、通过低压热壁化学气相淀积法在SiC外延层正面淀积一层厚度为1.5μm的Al作为源极接触P+区域离子注入的阻挡层,通过光刻和刻蚀形成源极接触P+区域注入区;
S42、在650℃的温度下对SiC外延层正面进行多次Al离子注入,在源极接触P+区域注入区形成深度为0.5μm,掺杂浓度为1×1019cm-3的源极接触P+区域;
S43、采用磷酸去除SiC外延层正面的Al,并且清洗干燥。
5.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S5包括:
采用RCA清洗标准对碳化硅表面进行清洗,烘干后制作碳膜保护,然后在1700℃氩气氛围中进行离子激活退火10min。
6.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S6包括:
通过氧等离子体去除碳膜,采用RCA清洗标准对碳化硅表面进行清洗,烘干。
7.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于,所述步骤S7包括:
在SiC外延层上表面外延生长厚度为50nm的绝缘SiC外延层,其工艺条件是:外延温度为1600℃,压力100mbar,反应气体采用硅烷和丙烷,载运气体采用纯氢气。
8.根据权利要求1所述的一种高可靠性外延栅的SiC MOSFET器件的制备方法,其特征在于:所述步骤S8包括:
用低压热壁化学气相淀积法在绝缘SiC外延层上表面淀积生长200nm的多晶硅,然后通过光刻、刻蚀保留住栅氧化膜上的多晶硅,形成磷离子掺杂浓度为1×1020cm-3,厚度为200nm的多晶硅栅极,其工艺条件是:淀积温度为600℃,淀积压强为60Pa,反应气体采用硅烷和磷化氢,载运气体采用氦气。
9.一种高可靠性外延栅的SiC MOSFET器件,其特征在于,所述高可靠性外延栅的SiCMOSFET器件由权利要求1~8中任意一项所述的高可靠性外延栅的SiC MOSFET器件的制备方法制备得到。
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