CN110534579A - A kind of graphene-based heterojunction field effect transistor, preparation method and its integrated circuit - Google Patents
A kind of graphene-based heterojunction field effect transistor, preparation method and its integrated circuit Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
The invention discloses a kind of graphene-based heterojunction field effect transistor, preparation method and its integrated circuits, belong to technical field of semiconductor device.Comprising: substrate, gate electrode, dielectric layer, graphene layer, source electrode and drain electrode, further includes: oxide semiconductor layer, and oxide semiconductor layer is arranged between graphene layer and source electrode and drain electrode, top-gated or bottom grating structure can be used in device.Preparation method includes: to deposit to form dielectric layer on gate electrode；Graphene layer is formed on the dielectric layer；Oxide semiconductor layer is formed on graphene layer；Source electrode and drain electrode is respectively formed at the both ends of oxide semiconductor layer.The present invention improves the on-off ratio of conventional graphite alkene FET device, and obtains sufficiently high mobility and saturable output characteristics, therefore can satisfy it in the related application of logic and RF application, and manufacture is simple, is conducive to large-scale production and application.
Description
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of graphene-based heterojunction field effect transistor,
Preparation method and its integrated circuit.
Background technique
In the past more than ten years, the two-dimensional material electronic material most with prospects as the rear silicon epoch causes industry
Extensive concern.Wherein, graphene has the carrier mobility of superelevation, this makes it show one's talent in numerous two-dimensional materials,
For constructing field effect transistor (FET), to substitute traditional silicon in future integrated circuits.In addition, graphene can pass through chemistry
Vapour deposition process carries out large area preparation, this is its another big advantage.But graphene itself lacks band gap, this leads to tradition
Graphene field effect transistor on-off ratio it is extremely low (usually less than 10), seriously limit its practical application potential, it is especially right
For logic circuit.
In recent years, a large amount of research work is dedicated to opening graphene band gap.For example, by preparing graphene nanobelt,
Its band gap can be expanded to about 400meV.However, the band gap of graphene nanobelt is inversely proportional with its width, the width of nanobelt
Edge that is very narrow, and must having neat and smooth is needed, this is greatly to challenge for batch production.Also, this method
Bring declining to a great extent for device mobility.On the other hand, under vertical electric field effect, building bilayer graphene also contributes to opening
Band gap, however prepare FET device on-off ratio less than 100, still far from the application for meeting logic circuit.
Researchers also proposed a kind of based on graphene/semiconductor Van der Waals hetero-junctions vertical FET (VFET), pass through
Electric field adjusts the work function of graphene, to influence the schottky barrier height at heterojunction boundary, finally controls hetero-junctions
Charge transport in vertical direction realizes effective switch of device.However, in the structure, the maximum advantage of graphene, i.e. " face
It is interior " carrier mobility of superelevation, it is not utilized effectively actually, this causes the mobility of device lower.In addition, passing
The output characteristics of system graphene field effect transistor is usually linear, it is difficult to reach saturation, this makes its answering in RF application
It is limited with also the same.The appearance of VFET can not solve the problems, such as this.
Therefore, it is necessary to improve to existing graphene field effect transistor, and propose corresponding manufacturing method, ability
Its above-mentioned intrinsic short slab is overcome, to meet the needs of practical application.
Summary of the invention
The object of the present invention is to provide a kind of graphene-based heterojunction field effect transistor, preparation method and its integrated electricity
Road is difficult to solve the problems, such as conventional graphite alkene FET device on-off ratio with mobility to take into account, output characteristics is difficult to be saturated.
The technical scheme to solve the above technical problems is that
A kind of graphene-based heterojunction field effect transistor, including substrate, gate electrode, dielectric layer, graphene layer, source electricity
Pole and drain electrode, further includes: oxide semiconductor layer, and oxide semiconductor layer is arranged in graphene layer and source electrode and electric leakage
Between pole.
Further, in preferred embodiments of the present invention, the material of above-mentioned oxide semiconductor layer be ZnO,
InGaZnO、Ga2O3、Cu2O, SnO or NiO.
The oxide semiconductor that the present invention uses all has wider forbidden bandwidth, since grapheme transistor on-off ratio is non-
It is often low, using the big characteristic of oxide semiconductor forbidden bandwidth, high on-off ratio device can be obtained with the hetero-junctions of graphene composition,
And also graphene can be made full use of to migrate high feature after device opening, so that device is provided simultaneously with high on-off ratio and height
The characteristics of mobility.
Further, in preferred embodiments of the present invention, above-mentioned oxide semiconductor is N-shaped or p-type.
Further, in preferred embodiments of the present invention, the material of above-mentioned dielectric layer is SiO2、Si3N4、BN、
Al2O3、HfO2、ZrO2、TiO2Or Y2O3One or more combinations.
Further, in preferred embodiments of the present invention, above-mentioned graphene layer is single layer, bilayer or multilayer；Source electrode
With electric leakage extremely single or multi-layer structure；The material of substrate is silicon, silica, silicon carbide, glass or high molecular polymer.
Further, in preferred embodiments of the present invention, above-mentioned field effect transistor uses bottom-gate type configuration or top-gated
Type structure.
The preparation method of above-mentioned graphene-based heterojunction field effect transistor, comprising the following steps:
Bottom grating structure:
Gate electrode is formed on the substrate；Deposition forms dielectric layer on gate electrode and substrate；It is formed on the dielectric layer
Graphene layer；Oxide semiconductor layer is formed on graphene layer；Source electrode is respectively formed at the both ends of oxide semiconductor layer
And drain electrode；
Top gate structure: both ends on substrate are respectively formed source electrode and drain electrode；It is formed on the source and drain electrodes
Oxide semiconductor layer；Graphene layer is formed in oxide semiconductor layer；Deposition forms dielectric layer on graphene layer；In electricity
Gate electrode is formed on dielectric layer.
Further, in preferred embodiments of the present invention, the mode of above-mentioned formation graphene layer is chemical vapor deposition
Method grows and shifts or mechanical stripping method.
Further, above-mentioned that also graphene layer and oxide semiconductor layer are carried out in preferred embodiments of the present invention
Patterned process.
A kind of integrated circuit, including the above-mentioned graphene-based heterojunction field effect transistor being prepared.
The invention has the following advantages:
1, the present invention improves the on-off ratio of conventional graphite alkene FET device, and obtains sufficiently high mobility and can
The output characteristics of saturation, therefore can satisfy it in the related application of logic and RF application, and manufacture is simple, is conducive to
Large-scale production and application.
2, the present invention is using oxide semiconductor-graphene hetero-junctions as the double channel of plane type field effect transistor
Layer, and source, drain electrode both ends catalytic oxidation object semiconductor layer, and (oxide semiconductor layer prevents not in contact with graphene layer
Source electrode and drain electrode is directly contacted with graphene layer), to equally form two concatenated VFET devices, it is located at
Vertical area below source, drain electrode can regulate and control the charge transport in formed schottky junction vertical direction simultaneously, that is, synchronize out
It opens/closes, therefore higher on-off ratio can be obtained；The double channel of plane additionally aids the superpower electricity for making full use of graphene
Lotus transport capability compensates for the deficiency of single VFET to obtain higher device mobility；In addition, oxide semiconductor ditch
The presence in road additionally aids the saturation for realizing transistor output characteristics, breaks through the inherent limitation of graphene-based FET device.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the diagrammatic cross-section of the graphene-based heterojunction field effect transistor of top gate type of the invention；
Fig. 2 is the diagrammatic cross-section of the graphene-based heterojunction field effect transistor of bottom gate type of the invention；
Fig. 3 is the schematic perspective view of the graphene-based heterojunction field effect transistor of bottom gate type of the invention；
Fig. 4 is the preparation flow figure of the graphene-based heterojunction field effect transistor of bottom gate type of the invention；
Fig. 5 is that the transfer characteristic for the InGaZnO/ graphene heterojunction field effect transistor that the embodiment of the present invention provides is bent
Line；
Fig. 6 is that the output characteristics for the InGaZnO/ graphene heterojunction field effect transistor that the embodiment of the present invention provides is bent
Line；
In figure, 1- substrate；2- gate electrode；3- dielectric layer；4- graphene layer；5- oxide semiconductor layer；6- source electrode；
7- drain electrode.
Specific embodiment
With reference to embodiments and principles and features of the present invention are described in attached drawing, and example is served only for explaining this
Invention, is not intended to limit the scope of the present invention.The person that is not specified actual conditions in embodiment, according to normal conditions or manufacturer builds
The condition of view carries out.Reagents or instruments used without specified manufacturer is the conventional production that can be obtained by commercially available purchase
Product.
Graphene-based heterojunction field effect transistor of the invention, comprising:
Top-gate type structure (as shown in Figure 1): it is followed successively by substrate, source electrode and drain electrode, oxide semiconductor from below to up
Layer, graphene layer, dielectric layer and gate electrode.
Bottom-gate type configuration (as shown in Figure 2): it is followed successively by substrate, gate electrode, dielectric layer, graphene layer, oxygen from below to up
Compound semiconductor layer and source electrode and drain electrode.
Wherein, the material of substrate is silicon, silica, silicon carbide, glass or high molecular polymer；The material of dielectric layer
Material is SiO2、Si3N4、BN、Al2O3、HfO2、ZrO2、TiO2Or Y2O3One or more combinations；Graphene layer is single layer, double
Layer or multilayer；The material of oxide semiconductor layer is ZnO, InGaZnO, Ga2O3、Cu2O, SnO or NiO, and oxide semiconductor
For N-shaped or p-type；Source electrode and drain electrode is single or multi-layer structure.
The preparation method of graphene-based heterojunction field effect transistor of the invention, comprising the following steps:
Bottom-gate type configuration (as shown in Figures 3 and 4):
Gate electrode is formed on the substrate；Deposition forms dielectric layer on gate electrode and substrate；It is formed on the dielectric layer
Graphene layer；Oxide semiconductor layer is formed on graphene layer；Source electrode is respectively formed at the both ends of oxide semiconductor layer
And drain electrode；
Top-gate type structure: both ends on substrate are respectively formed source electrode and drain electrode；Shape on the source and drain electrodes
At oxide semiconductor layer；Graphene layer is formed in oxide semiconductor layer；Deposition forms dielectric layer on graphene layer；In
Gate electrode is formed on dielectric layer.
Wherein, the mode for forming graphene layer is that chemical vapour deposition technique grows and shifts or mechanical stripping method；And it is above-mentioned
Patterned process also is carried out to graphene layer and oxide semiconductor layer in step.
Top-gate type structure or bottom gate type are used in the preparation method of graphene-based heterojunction field effect transistor of the invention
Structure, step parameter is consistent, and difference is that the position of substrate is different.
Embodiment 1:
The graphene-based heterojunction field effect transistor of the present embodiment, using bottom-gate type configuration: from bottom to top successively are as follows:
Substrate: Si (p++ heavy doping)/SiO is selected2, wherein heavy doping Si also serves as gate electrode, SiO2As dielectric
Layer, with a thickness of 300nm；
Graphene layer: the single-layer graphene grown on copper foil by chemical vapor deposition is transferred to electric Jie using wet process
On matter layer；
Oxide semiconductor layer: the InGaZnO film grown using magnetically controlled sputter method, with a thickness of 100nm；
Source electrode and drain electrode: the Ti/Au electrode formed by electron beam evaporation, wherein Ti is with a thickness of 20nm, Au thickness
For 160nm, the width of source electrode and drain electrode is W=25um, the distance L=20um of source electrode and drain electrode.Wherein, source electricity
Pole and drain electrode only with InGaZnO is thin contacts, without contacting graphene.
Embodiment 2:
The preparation method of the graphene-based heterojunction field effect transistor of the present embodiment, graphene-based hetero junction field effect are brilliant
Body pipe uses bottom-gate type configuration, comprising the following steps:
(1) surface treatment of substrate: by Si (p++ heavy doping)/SiO2Substrate is respectively in acetone, dehydrated alcohol and deionization
Be cleaned by ultrasonic 10min in water, then with being dried with nitrogen, and use hot plate toasted at a temperature of 80 DEG C -150 DEG C 5min-15min with
The steam of substrate surface is removed, guarantees Si (p++ heavy doping)/SiO2Substrate surface cleaning, drying.
(2) transfer of graphene film: utilizing conventional wet transfer method, will be grown on copper foil by chemical vapour deposition technique
The single-layer graphene grown is transferred to Si/SiO2Substrate.
(3) grow oxide semiconductor layer: magnetron sputtering apparatus vacuumizes, and back end vacuum degree is 2.0 × 10-6Torr is raw
Long temperature is room temperature, and operating air pressure is 5.0 × 10-1Pa is passed through Ar/O2Gas grows the InGaZnO film of 100nm, by graphite
Alkene is completely covered.
(4) photoetching process:
(4.1) AZ6112 photoresist is coated uniformly in step 3 on film by gluing with the revolving speed of 3000r/min；
(4.2) front baking, the photoresist after coating bake 60s at 100 DEG C；
(4.3) it exposes, on a photoresist by the covering of designed photolithography plate, time for exposure 0.8-1.2s；
(4.4) develop, the sample after exposure is put into developer solution, developing time 30s；
(4.5) it checks, checks whether graphic width distance meets the size of setting.
(5) etching process:
(5.1) salt acid etch InGaZnO is used, hydrochloric acid proportion is HCl:H2O (1:10) etches 30s；
(5.2) reactive ion etching graphene, with power 20W, throughput 20sccm, time 20s.
(6) photoetching process:
(6.1) AZ5214 reversal photoresist is coated uniformly in step 3 on film by gluing with the revolving speed of 3000r/min；
(6.2) front baking, the photoresist after coating bake 60s at 100 DEG C；
(6.3) it exposes for the first time, on a photoresist by the covering of designed photolithography plate, time for exposure 0.8s-1.2s；
(6.4) it dries afterwards, the photoresist after exposure bakes 90s at 120 DEG C；
(6.5) general exposure, unglazed mechanical, time for exposure 45s；
(6.6) develop, the sample after pan-exposure is put into developer solution, developing time 50s；
(6.7) it checks, checks whether graphic width spacing meets the size of setting.
(7) electron beam evaporation method evaporation metal Ti, thickness 20nm, evaporation rate the formation of source electrode and drain electrode: are utilized
It is maintained at 0.1nm/s；Then evaporation metal Au, thickness 160nm, evaporation rate are maintained at 2nm/s, have deposited gold again on Ti layer
After category, sample is sequentially placed into acetone, dehydrated alcohol, in deionized water, photoresist and extra Ti, Au are removed, to obtain
Patterned electrode layer.
The graphene heterojunction field effect transistor that above-described embodiment is prepared is tested for the property, is obtained
The transfer characteristic curve of InGaZnO/ graphene heterojunction field effect transistor, as shown in Figure 5.And InGaZnO/ graphene is different
The output characteristic curve of matter junction field effect transistor, as shown in Figure 6
From Fig. 5 it is known that the current on/off ratio of InGaZnO/ graphene heterojunction field effect transistor is 3x106, move
Shifting rate is 220cm2/V·s；Compared to traditional graphene FET device, on-off ratio improves 5 orders of magnitude；Compared to simple
InGaZnO thin film transistor (TFT) and graphene VFET device, device mobility be increased dramatically.In other words, InGaZnO/
Graphene heterojunction field effect transistor can combine high on-off ratio and high mobility.From Fig. 6 it is known that InGaZnO/ stone
Apparent saturated characteristic is presented in black alkene heterojunction field effect transistor, breaches the inherent limitation of graphene FET device.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of graphene-based heterojunction field effect transistor, including substrate, gate electrode, dielectric layer, graphene layer, source electrode
And drain electrode, which is characterized in that further include: oxide semiconductor layer, and oxide semiconductor layer is arranged in graphene layer and source
Between electrode and drain electrode.
2. graphene-based heterojunction field effect transistor according to claim 1, which is characterized in that the oxide is partly led
The material of body layer is ZnO, InGaZnO, Ga2O3、Cu2O, SnO or NiO.
3. graphene-based heterojunction field effect transistor according to claim 2, which is characterized in that the oxide is partly led
Body is N-shaped or p-type.
4. graphene-based heterojunction field effect transistor according to claim 1, which is characterized in that the dielectric layer
Material is SiO2、Si3N4、BN、Al2O3、HfO2、ZrO2、TiO2Or Y2O3One or more combinations.
5. graphene-based heterojunction field effect transistor according to claim 1, which is characterized in that the graphene layer is
Single layer, bilayer or multilayer；The source electrode and drain electrode is single or multi-layer structure；The material of the substrate is silicon, titanium dioxide
Silicon, silicon carbide, glass or high molecular polymer.
6. graphene-based heterojunction field effect transistor according to claim 1-5, which is characterized in that the field
Effect transistor uses bottom-gate type configuration or top-gate type structure.
7. the preparation method of graphene-based heterojunction field effect transistor described in any one of claims 1-6, which is characterized in that
The following steps are included:
Bottom-gate type configuration: gate electrode is formed on the substrate；Deposition forms dielectric layer on gate electrode and substrate；In dielectric layer
Upper formation graphene layer；Oxide semiconductor layer is formed on graphene layer；It is respectively formed at the both ends of oxide semiconductor layer
Source electrode and drain electrode；
Top-gate type structure: both ends on substrate are respectively formed source electrode and drain electrode；Oxygen is formed on the source and drain electrodes
Compound semiconductor layer；Graphene layer is formed in oxide semiconductor layer；Deposition forms dielectric layer on graphene layer；It is situated between in electricity
Gate electrode is formed on matter layer.
8. the preparation method of graphene-based heterojunction field effect transistor as claimed in claim 7, which is characterized in that form graphite
The mode of alkene layer is that chemical vapour deposition technique grows and shifts or mechanical stripping method.
9. the preparation method of graphene-based heterojunction field effect transistor as claimed in claim 7, which is characterized in that also to graphite
Alkene layer and oxide semiconductor layer carry out patterned process.
10. a kind of integrated circuit, the graphene-based heterojunction field effect transistor being prepared including claim 7.
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