CN110224030A - A kind of production method of the thin film transistor (TFT) and transistor of sub-micron heterojunction structure - Google Patents
A kind of production method of the thin film transistor (TFT) and transistor of sub-micron heterojunction structure Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
The present invention relates to technical field of semiconductors, more specifically, it is related to the production method of the thin film transistor (TFT) and transistor of a kind of sub-micron heterojunction structure, the grid for including substrate and being connect with substrate, substrate and grid connect insulating layer, and insulating layer connects active layer, and active layer connects source-drain electrode metal layer, wherein, active layer is the periodical heterojunction structure that is formed after submicron interstitial layer covering material.Transistor of the invention is regulated and controled by grid, and can increase transistor opens electric current, reduces the powered-down stream of transistor, improves transistor performance.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of thin film transistor (TFT) of sub-micron heterojunction structure
And the production method of transistor.
Background technique
Thin film transistor (TFT) (TFTs) and field effect transistor (FETs) are constructing function electronic circuit and exploration transmitting physical
Basic unit.In traditional TFTs or FETs, uniform semiconductor film limits size of current, on-off ratio, detection
The performances such as sensitivity and transmitting physical, in this case, the promotion of transistor performance generally require to find new material, and
The potentiality for having excavated material are difficult further to be promoted.
In recent years, novel near field photolithography technology is reported, by the technology, sub-micron can be realized to certain material
The patterning of the controllable striped interstitial structure of rank.Based near field photolithography technology, the TFTs with sub-micron heterojunction structure is developed, is led to
It crosses degeneracy material and nondegenerate material forms periodical hetero-junctions active layer, regulated and controled by grid, opening for transistor can be increased
Electric current reduces the powered-down stream of transistor.
Summary of the invention
The present invention in order to overcome at least one of the drawbacks of the prior art described above, provides a kind of the thin of sub-micron heterojunction structure
The production method of film transistor and transistor, transistor have the active layer of periodical hetero-junctions, are regulated and controled by grid, Ke Yizeng
Big transistor opens electric current, reduces the powered-down stream of transistor, improves transistor performance.
In order to solve the above technical problems, the technical solution adopted by the present invention is that: a kind of film of sub-micron heterojunction structure is brilliant
The grid that body pipe includes substrate and is connect with substrate, substrate and grid connect insulating layer, and insulating layer connects active layer, active
Layer connection source-drain electrode metal layer, wherein active layer is the periodical heterojunction structure that is formed after submicron interstitial layer covering material.
In the present solution, the substrate of thin film transistor (TFT) is connect with grid, insulating layer is connect with substrate and grid, insulating layer with have
Active layer connection, source-drain electrode metal layer are connect with active layer, and active layer is periodical heterojunction structure, and periodical heterojunction structure is sub-micro
It is formed, is regulated and controled by grid, can increase transistor opens electric current, reduces the powered-down of transistor after rice clearance layer covering material
Stream, high improves device performance.
In one embodiment, insulating layer is oxidation insulating layer or polymer insulation layer.
In one embodiment, active layer is that the submicron interstitial layer filling covering nondegenerate that degeneracy material is formed partly is led
The periodical heterojunction structure that body material is formed.
Preferably, degeneracy material includes but is not limited to InSnO, and the nondegenerate semiconductor material includes but is not limited to
InGaZnO、GaSnO。
Source-drain electrode metal layer includes but is not limited to Mo, Al, and the material of the substrate includes but is not limited to Si, glass, flexibility
Substrate.
When substrate is Si, substrate is directly connected to insulating layer.
When substrate is glass or flexible substrate, deposit one layer of gate electrode on substrate, gate electrode include but is not limited to Cr/Au,
Al、Mo。
The present invention provides the production method of the thin film transistor (TFT) of sub-micron heterojunction structure, will be deposited on substrate and grid
Degeneracy patterns of material forms submicron interstitial layer, then deposits one layer of nondegenerate semiconductor material on substrate and grid and scheme
Case forms active layer, the sedimentary origin on active layer with the nondegenerate semiconductor material filling submicron interstitial layer after patterning
Drain metal layer.
Specifically include following steps:
S1: substrate is cleaned and is dried up；
S2: when the substrate is Si, it is directly used as Si-gate；When the substrate is glass or flexible substrate, in the substrate
It is upper first to deposit one layer of gate electrode；
S3: spin coating or the deposition insulating layer on substrate and grid；
S4: depositing degeneracy material on substrate and grid, using near field photolithography technology, patterns degeneracy material to obtain Asia
Micron interstitial striated structure；
S5: depositing nondegenerate semiconductor material on substrate and grid, and selective etch goes out to fill covering degeneracy material sections
The nondegenerate semiconductor patterning in domain, then hydatogenesis or splash-proofing sputtering metal layer in vacuum environment, different to complete sub-micron
Matter configuration thin film transistor.
Preferably, the channel gap of submicron interstitial layer is 200nm~3um, fills sub-micro using nondegenerate semiconductor film
The channel gap of rice clearance layer, the periodical hetero-junctions of collimated source drain directions is generated with degeneracy material, in source electrode and drain electrode
Between establish current path.
In VG<VTHWhen, the electron concentration of nondegenerate semiconductor film is low, space-charge region is formed, at degeneracy/nondegenerate interface
Induction built in field nearby, hinders electron transport, and periodical heterojunction structure further decreases powered-down stream；In VG>VTHWhen, non-letter
And carrier concentration increases in semiconductor, forms interfringe electron propagation ducts on submicron interstitial layer, periodical hetero-junctions
Structure is further promoted and opens electric current.Therefore, source and drain electrode current mainly regulates and controls nondegenerate semiconductor film by grid and realizes.
Compared with prior art, the present invention having the following characteristics that
The present invention patterns degeneracy material membrane by near field photolithography technology, forms submicron interstitial striated structure, then sputter
The gap of nondegenerate semiconductor film filling covering submicron interstitial layer constitutes active layer, applies on transistor arrangement, is formed sub-
Micron order and periodical degeneracy adulterate hetero-junctions oxide thin film transistor, have the characteristics that high on-off ratio.The present invention and tradition
Uniform semiconductor thin-film transistor is compared, and has submicron order and periodical degeneracy doping hetero-junctions oxide thin film transistor tool
Have grid regulate and control nondegenerate semiconductor film carrier concentration, hinder or connection submicron interstitial layer striped between electron-transport, lead to
Periodical heterojunction structure is crossed, powered-down stream is inhibited, increases the characteristics of opening electric current, transistor switch ratio can be greatly improved, mutual conductance, move
Shifting rate.This programme demonstrates the feasibility that various submicrometer structures or interface are made in TFTs or FETs, and is significantly expanded
The research range of multi-functional TFTs or FETs.
Detailed description of the invention
Fig. 1 is near field photolithography technical principle in the embodiment of the present invention.
Fig. 2 is transistor device structures and SEM image in the embodiment of the present invention.
Fig. 3 is that transistor measures characteristic in the embodiment of the present invention.
Specific embodiment
Attached drawing only for illustration, is not considered as limiting the invention；In order to better illustrate this embodiment, attached
Scheme certain components to have omission, zoom in or out, does not represent the size of actual product；To those skilled in the art,
The omitting of some known structures and their instructions in the attached drawings are understandable.Being given for example only property of positional relationship is described in attached drawing
Illustrate, is not considered as limiting the invention.
The same or similar label correspond to the same or similar components in the attached drawing of the embodiment of the present invention；It is retouched in of the invention
In stating, it is to be understood that if the orientation or positional relationship for having the instructions such as term " on ", "lower", "left", "right" is based on attached drawing
Shown in orientation or positional relationship, be merely for convenience of description of the present invention and simplification of the description, rather than indication or suggestion is signified
Device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore positional relationship is described in attached drawing
Term only for illustration, should not be understood as the limitation to this patent, for the ordinary skill in the art, can
To understand the concrete meaning of above-mentioned term as the case may be.
Embodiment 1:
The present invention provides a kind of thin film transistor (TFT) of sub-micron heterojunction structure, and thin film transistor (TFT) includes substrate and and substrate
The grid of connection, substrate and grid connect insulating layer, and insulating layer connects active layer, and active layer connects source-drain electrode metal layer.
In the present embodiment, active layer is the submicron interstitial layer filling covering nondegenerate semiconductor material that degeneracy material is formed
The periodical heterojunction structure of formation, degeneracy material are InSnO, can also be PEDOT:PSS, as long as the enough height of materials conductive rate, nothing
Machine material, organic material.
Nondegenerate semiconductor material is one of InGaZnO, GaSnO, can also be C8-BTBT or P3HT, as long as
The organic semiconducting materials of nondegenerate class.
Source-drain electrode metal layer is one of Mo, Al, can also be Au, it is suitable to be selected according to semiconductor material work function
S/D electrode.
When the material of substrate is Si, substrate is directly connected to insulating layer, and insulating layer is oxidation insulating layer or polymer insulation
Layer.
When substrate is glass or flexible substrate, one layer of gate electrode is deposited on substrate, in gate electrode Cr/Au, Al, Mo
One kind can also be Ti, while the metal that can theoretically do electrode is ok.
In the present embodiment, a kind of production method of the thin film transistor (TFT) of sub-micron heterojunction structure is provided, substrate will be deposited on
And the degeneracy patterns of material on grid, submicron interstitial layer is formed, then deposit one layer of nondegenerate on substrate and grid and partly lead
Body material simultaneously patterns, and active layer is formed with the nondegenerate semiconductor material filling submicron interstitial layer after patterning, active
Sedimentary origin drain metal layer on layer.
Method includes following steps:
S1: substrate cleans in acetone, ethyl alcohol, water, is dried with nitrogen；
S2: when substrate is Si, it is directly used as Si-gate；When the substrate is glass or flexible substrate, over the substrate first
Deposition a layer thickness is 30~50nm gate electrode；
S3: spin coating or PECVD deposit the insulating layer on substrate and grid, and the thickness of insulating layer is 100~
300nm；
S4: 30nm~80nm degeneracy material is deposited on substrate and grid using DC sputtering method, uses near field photolithography skill
Art patterns degeneracy material to obtain submicron interstitial striated structure；
S5: depositing 40~100nm nondegenerate semiconductor material on substrate and grid, and selective etch goes out to fill covering letter
And the nondegenerate semiconductor patterning of material area, then in vacuum environment hydatogenesis or sputtering 70~120nm metal,
To complete sub-micron heterojunction structure thin film transistor (TFT).
40~100nm nondegenerate semiconductor material, selective etch are deposited on substrate and grid using RF sputtering method
The nondegenerate semiconductor patterning of filling covering degeneracy material area out, then hydatogenesis or sputtering 70 in vacuum environment
~120nm metal, to complete sub-micron heterojunction structure thin film transistor (TFT), the vacuum degree of vacuum environment is greater than 3.8 × 10-3。
In the present embodiment, the channel gap of submicron interstitial layer is 200nm~3um, is filled using nondegenerate semiconductor film
The channel gap of submicron interstitial layer generates the periodical hetero-junctions of collimated source drain directions with degeneracy material, in source electrode and leakage
Current path is established between pole.
In VG<VTHWhen, the electron concentration of nondegenerate semiconductor film is low, space-charge region is formed, at degeneracy/nondegenerate interface
Induction built in field nearby, hinders electron transport, and periodical heterojunction structure further decreases powered-down stream；In VG>VTHWhen, non-letter
And carrier concentration increases in semiconductor, forms the interfringe electron propagation ducts of submicron interstitial layer, periodical hetero-junctions
Structure is further promoted and opens electric current.Therefore, source and drain electrode current mainly regulates and controls nondegenerate semiconductor film by grid and realizes.
Source and drain electrode current mainly regulates and controls nondegenerate semiconductor film by grid and realizes, so channel length or nondegenerate are partly led
Body film fills the change of clearance distance etc., and grid, which regulates and controls it, also to be changed correspondingly.
The following are the specific embodiments of method, as a result such as Fig. 1 and as shown in Figure 2:
S1: Si/SiO is provided2Substrate, SiO2With a thickness of 100nm, by being cleaned by ultrasonic substrate in acetone, ethyl alcohol, water,
It is dried with nitrogen；
S2: it is sputtered on substrate and grid by DC and sputters 50nmITO；
S3: using near field photolithography technology, by photoetching, development, etching, patterns ITO to obtain 200nm~3um or so
Gap striated structure；
S4: being sputtered on substrate and grid by RF and sputter 70nmIGZO, and selective etch goes out to fill the covering region ITO
IGZO patterning, then 3.8 × 10-3Vacuum degree under mask hydatogenesis 100nmAl as source electrode, drain electrode, with complete
Sub-micron heterojunction structure thin film transistor (TFT).
It is illustrated in figure 3 sub-micron heterojunction structure thin film transistor (TFT) transfer characteristic, output characteristics, mobility etc. and common non-
The comparison of sub-micron heterojunction structure thin film transistor (TFT), as can be seen from the figure sub-micron heterostructure transistors are compared to common crystalline substance
Body pipe, maximum current, on-off ratio, mobility are all obviously improved.
Embodiment 2:
The present embodiment provides the production methods of another transistor, include following steps:
S1: Si substrate is used, is cleaned by ultrasonic substrate in acetone, ethyl alcohol, water, is dried with nitrogen；
S2: with the ZrO of 4000rpm/30s 1~4 spin coating 0.2mol/L in glove box2Solution, with 150 after spin coating is complete
DEG C annealing 15min be further continued for spin coating, annealed in air 2 hours after spin coating with 400 DEG C of conditions；
S3: it is sputtered on substrate and grid by DC and sputters 50nmITO；
S4: using near field photolithography technology, by photoetching, development, etching, patterns ITO to obtain the gap of 1um~2um
Striated structure；
S5: the IGZO sputtered with a thickness of 70nm is sputtered on substrate and grid by RF, selective etch goes out to fill covering
The IGZO patterning in the region ITO, then 3.8 × 10-3Vacuum degree under hydatogenesis with a thickness of 100nm Al, with complete
Sub-micron heterojunction structure thin film transistor (TFT).
Embodiment 3:
The present embodiment provides the production methods of another transistor, include following steps:
S1: Si/SiO2 substrate, SiO are provided2With a thickness of 100nm, pass through and be cleaned by ultrasonic lining in acetone, ethyl alcohol, water
Bottom is dried with nitrogen；
S2: it is sputtered on substrate and grid by DC and sputters 50nmITO；
S3: using near field photolithography technology, by photoetching, development, etching, patterns ITO to obtain between 200nm~3um
Gap striated structure；
S4: being sputtered on substrate and grid by RF and sputter 70nmIGZO, and selective etch goes out to fill the covering region ITO
IGZO patterning, then RF sputters 70nmMo as source electrode, drain electrode, to complete sub-micron heterojunction structure thin film transistor (TFT).
Implementation column 4:
The present embodiment provides the production methods of another transistor, include following steps:
S1: glass substrate is provided, is cleaned by ultrasonic substrate in acetone, ethyl alcohol, water, is dried with nitrogen；
S2: it is sputtered on substrate and grid by DC and sputters Mo as grid；
S3: with the ZrO of 4000rpm/30s 1~4 spin coating 0.2mol/L in glove box2Solution, after each spin coating is complete with
150 DEG C of condition annealing 15min are further continued for spin coating, are annealed in air 2 hours after spin coating with 400 DEG C of conditions；
S4: using near field photolithography technology, by photoetching, development, etching, patterns ITO to obtain 200nm~3um or so
Gap striated structure；
S5: being sputtered on substrate and grid by RF and sputter 70nmIGZO, and selective etch goes out to fill the covering region ITO
IGZO patterning, then 3.8 × 10-3Vacuum degree under mask hydatogenesis 100nmAl as source electrode, drain electrode, with complete
Sub-micron heterojunction structure thin film transistor (TFT).
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention
Protection scope within.
Claims (10)
1. a kind of thin film transistor (TFT) of sub-micron heterojunction structure, substrate and the grid connecting with substrate, the substrate and grid connect
Insulating layer is connect, the insulating layer connects active layer, and the active layer connects source-drain electrode metal layer, which is characterized in that described to have
Active layer is the periodical heterojunction structure that is formed after submicron interstitial layer covering material.
2. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 1, which is characterized in that the insulating layer is oxygen
Change insulating layer or polymer insulation layer.
3. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 1, which is characterized in that the active layer is letter
And the submicron interstitial layer filling that material is formed covers the periodical heterojunction structure that nondegenerate semiconductor material is formed.
4. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 3, which is characterized in that the degeneracy material packet
InSnO is included but is not limited to, the nondegenerate semiconductor material includes but is not limited to InGaZnO, GaSnO.
5. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 1, which is characterized in that the source-drain electrode metal
Layer includes but is not limited to Mo, Al, and the material of the substrate includes but is not limited to Si, glass, flexible base board.
6. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 5, which is characterized in that the substrate is Si,
Substrate is directly connected to the insulating layer.
7. the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 5, which is characterized in that the substrate is glass
Or flexible substrate, one layer of gate electrode is deposited on the substrate, gate electrode includes but is not limited to Cr/Au, Al, Mo.
8. a kind of production method of the thin film transistor (TFT) of sub-micron heterojunction structure, which is characterized in that substrate and grid will be deposited on
On degeneracy patterns of material, form submicron interstitial layer, then nondegenerate semiconductor layer and pattern are deposited on substrate and grid
Change, forms active layer with the nondegenerate semiconductor layer filling submicron interstitial layer after patterning, source-drain electrode is deposited on active layer
Metal layer.
9. the production method of the thin film transistor (TFT) of sub-micron heterojunction structure according to claim 8, which is characterized in that including
There are following steps:
S1: substrate is cleaned and is dried up；
S2: when the substrate is Si, it is directly used as Si-gate；When the substrate is glass or flexible substrate, over the substrate first
Deposit one layer of gate electrode；
S3: spin coating or the deposition insulating layer on substrate and grid；
S4: depositing degeneracy material on substrate and grid, using near field photolithography technology, patterns degeneracy material to obtain sub-micron
Clearance layer；
S5: depositing nondegenerate semiconductor layer on substrate and grid, and selective etch goes out to fill the non-of covering degeneracy material area
Degeneracy semiconductor patterning, then hydatogenesis or splash-proofing sputtering metal layer in vacuum environment, to complete sub-micron heterojunction structure
Thin film transistor (TFT).
10. according to claim 8 or the production method of the thin film transistor (TFT) of sub-micron heterojunction structure as claimed in claim 9,
It is characterized in that, the channel gap of the submicron interstitial layer is 200nm~3um, fills sub-micron using nondegenerate semiconductor layer
Clearance layer, with degeneracy material formed submicron interstitial layer generate collimated source drain directions periodical hetero-junctions, source electrode with
Current path is established between drain electrode.
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