CN110456300B - Acquisition unit detection device and method based on self-adaptive comparison analysis technology - Google Patents
Acquisition unit detection device and method based on self-adaptive comparison analysis technology Download PDFInfo
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Abstract
The invention discloses a collecting unit detection device and method based on a self-adaptive comparison analysis technology, wherein the collecting unit detection device comprises an FPGA module, an ARM module, an optical fiber sampling receiving module, an optical fiber synchronous transmitting module, a DA output module, an AD sampling module and an Ethernet receiving and transmitting module, wherein the optical fiber sampling receiving module, the optical fiber synchronous transmitting module, the DA output module and the AD sampling module are connected to the FPGA module, the FPGA module is connected to the ARM module, and the ARM module is connected with a man-machine interaction module and a debugging interface RJ45 through the Ethernet receiving and transmitting module. The detection device can directly output standard differential analog signals to the acquisition unit, simultaneously receive digital sampling signals output by the acquisition unit, realize accurate closed loop comparison test of the acquisition unit and ensure more reliable detection results.
Description
Technical Field
The invention belongs to the field of digital substations of power systems, and particularly relates to a device and a method for detecting an acquisition unit based on a self-adaptive comparison analysis technology.
Background
The electronic transformer has small volume, light weight, no magnetic saturation and no secondary open circuit, can be conveniently assembled with primary high-voltage switch equipment, effectively improves the equipment integration level, reduces the land consumption, is convenient to install and transport, and has wide market application prospect. The electronic transformer consists of a sensing coil and an acquisition unit, current and voltage signals of a primary system are converted into secondary small analog signals after being transmitted by a transformer body coil, and the secondary small analog signals are acquired and converted into digital sampling signals by an on-site acquisition unit and are output to the rear end through optical fibers. The acquisition unit is a core electrical component of the electronic transformer, and the quality of the transmission characteristics of the acquisition unit directly determines the sampling precision of the electronic transformer.
At present, the special detection device of the acquisition unit is less, and an electronic transformer open-loop test technology is mainly adopted. As shown in fig. 1, a standard current/voltage source outputs a primary large current/large voltage analog signal, the primary large current/large voltage analog signal is connected to a sensing coil of an electronic transformer and is converted into a secondary small voltage signal, the secondary small voltage signal is input into an acquisition unit of the electronic transformer and is converted into a digital sampling value, and the digital sampling value is output to an external electronic transformer tester. The tester is used for comparing and testing the sampling output characteristics of the electronic transformer based on standard signals, and acquiring the integral (sensing coil and acquisition unit) precision index of the electronic transformer.
The existing detection technology has defects in the aspects of test accuracy and test methods. Firstly, an open loop test technology is adopted, a test signal received by a tester is manually compared with an external standard signal, the requirements on the precision and stability of the output of the external standard source are higher, and the error of a test result is larger; secondly, the tested product comprises an electronic transformer sensing coil and an acquisition unit, and the test result shows the composite error of the electronic transformer sensing coil and the acquisition unit, so that the characteristic of the acquisition unit cannot be accurately represented; in particular, the digital sampling protocol of the output of the electronic transformer is not unified, the sampling values of the output of the electronic transformer acquisition units produced by various manufacturers are different in the transmission baud rate, the sampling rate, the coding mode and the application layer frame format, and how to efficiently and adaptively receive the sampling values of the output of the acquisition units is also a difficulty in realizing the acquisition unit detection technology.
Disclosure of Invention
The invention aims to solve the technical problems that: the acquisition unit detection device and the acquisition unit detection method based on the self-adaptive comparison analysis technology solve the problems that the existing electronic transformer acquisition unit detection device is insufficient, the standard source requirements are high, the test result errors are large, the characteristics of the acquisition units cannot be independently tested, the self-adaptive sampling access is not available and the like in the existing open loop detection technology.
The technical scheme adopted by the invention is as follows: the acquisition unit detection device based on the self-adaptive comparison analysis technology comprises an FPGA module, an ARM module, an optical fiber sampling receiving module, an optical fiber synchronous transmitting module, a DA output module, an AD sampling module and an Ethernet receiving and transmitting module, wherein the optical fiber sampling receiving module, the optical fiber synchronous transmitting module, the DA output module and the AD sampling module are connected to the FPGA module, the FPGA module is connected to the ARM module, the ARM module is connected with a human-computer interaction module and is connected with a debugging interface RJ45 through the Ethernet receiving and transmitting module, and the FPGA module is used for driving a bottom layer module in parallel and receiving or transmitting test data in real time; the ARM module is used for data processing analysis and man-machine interaction; the optical fiber sampling receiving module is used for receiving the digital sampling value output by the tested acquisition unit; the optical fiber synchronous transmitting module is used for transmitting a synchronous signal to the acquisition unit; the DA output module is used for sending the standard source small voltage analog quantity; the AD sampling module is used for extracting standard source analog quantity in real time.
A detection method of an acquisition unit detection device based on an adaptive comparison analysis technology comprises the following steps: firstly, calculating discrete instantaneous sampling values of a standard source according to configuration, and outputting a small voltage analog quantity to a tested acquisition unit after digital differential calculation, and outputting an original standard source analog quantity which is not subjected to differential calculation; secondly, accessing a standard source analog quantity which is not differentiated through an AD sampling module to be used as a standard comparison signal of the detection device; then, the digital sampling signal output by the tested acquisition unit is adaptively acquired through an optical fiber receiving module and used as a sample comparison signal of the detection device; and finally, automatically performing closed-loop analysis on the test data by using a detection device to obtain sampling transmission indexes of steady-state precision, transient characteristics and time characteristics of the tested acquisition unit, thereby realizing an independent closed-loop test function of the acquisition unit.
The detection method of the acquisition unit detection device based on the self-adaptive comparison analysis technology specifically comprises the following steps:
Step 1, two-way standard output: the ARM module acquires analog quantity parameters configured by a user, calculates analog quantity instantaneous sampling values of sampling rates, and drives the DA module to output analog quantity voltage signals through the FPGA module;
The acquisition unit acquires the voltage signals subjected to differential processing, then an internal hardware integration circuit or a software integration algorithm restores the voltage signals to original samples and outputs the original samples, the detection device needs to synchronously output two groups of homologous standard analog quantity signals, and one path of the standard analog quantity signals is not subjected to digital differential processing and is used as a standard source for comparison by the detection device; the other path is subjected to digital differential processing, and an output signal of the analog electronic transformer is connected to a tested acquisition unit;
After the detection device outputs a standard signal, the step 2 and the step 3 are carried out to recover the signal, so that an automatic closed-loop detection system is realized;
step 2, standard signal stoping: after standard output in the step 1, extracting one standard source signal which is not subjected to differential processing in the step 2;
The FPGA module drives the AD sampling module, analog-to-digital conversion of the input voltage analog quantity is carried out to digital sampling values, the digital sampling values are received to the detection device, each digital sampling value is accurately recorded by the FPGA to correspond to the sampling moment, and the accuracy of the test data analysis in the step 4 is improved.
Step 3, digital sampling self-adaptive receiving: after the standard output of the step 1, synchronously receiving the digital quantity sample signal output by the acquisition unit through the step 3;
The FPGA module drives the optical fiber sampling module to receive the optical fiber digital samples output by the acquisition unit, and each digital sampling value is also recorded with the receiving time accurately by the FPGA, and the sampling value protocol output by the current electronic transformer acquisition unit has more types and needs to be received and analyzed in a self-adaptive manner in a compatible manner;
The FPGA module continuously detects the maximum displacement period of an input digital signal according to the principle of the Manniche code and the non-Manniche code, distinguishes a signal coding mode, simultaneously utilizes the minimum displacement period value to determine the protocol coding baud rate, continuously carries out sampling transmission monitoring according to the baud rate, starts link transmission by a specific data initiator after the sampling link is detected stably, receives data blocks according to fixed bytes, carries out CRC (cyclic redundancy check) at the tail end of each data block, and finishes the reception after the received data blocks reach the maximum CRC;
Step 4, closed loop comparison analysis: acquiring test standard signals through the step 2, acquiring sample signals of the acquisition unit through the step 3, performing error calculation on the two groups of signals in the step 4, and detecting the transmission characteristics of the acquisition unit;
the ARM module collects original standard sampling values acquired by the FPGA module and sampling values of the samples output by the acquisition unit, a closed-loop detection system is realized, and indexes of steady-state transmission precision, transient transmission characteristics and time characteristics of the acquisition unit to be detected are automatically analyzed by adopting interpolation synchronization, fourier calculation, harmonic analysis and waveform comparison methods, so that independent self-adaptive closed-loop detection of the acquisition unit is realized.
The invention has the beneficial effects that: compared with the prior art, the invention has the following effects:
(1) The acquisition unit is independently subjected to closed loop test, the detection device can directly output standard differential analog signals to the acquisition unit, and simultaneously, the detection device receives digital sampling signals output by the acquisition unit, so that accurate closed loop comparison test of the acquisition unit can be realized, and the detection result is more reliable;
(2) The internal integrated small analog quantity standard source, the internal integrated high precision and stable performance small voltage analog quantity output standard source of the detection device can be directly connected to the detected acquisition unit without the support of an electronic transformer body coil and an external standard source device, so that the detection system configuration of the acquisition unit is greatly simplified, and the test efficiency is improved;
(3) The two-way standard signal synchronous output supports the synchronous output of the differential analog quantity and the original analog quantity, one way of unprocessed signal is recovered by the device as a comparison standard, the differential output of one way of digital differential signal analog electronic transformer coil is directly connected to the tested acquisition unit, the two ways of signals are synchronous in a homologous way, and the detection requirement of the integral recovery function of the acquisition unit is met;
(4) The sampling output of the acquisition unit is self-adaptively acquired, the self-adaptive receiving of the digital sampling output of the acquisition unit realized based on the FPGA module is compatible with the current mainstream electronic transformer sampling transmission protocol, and the application range of the detection device is greatly improved;
(5) And (5) temporarily analyzing steady-state characteristics by the acquisition unit. The device can detect performance indexes such as accuracy, frequency characteristic, instantaneous error, compound error, decay time constant, time characteristic, protocol consistency and the like of the acquisition unit. The system has the functions of perfecting transient and steady state characteristic analysis of the acquisition unit.
Drawings
FIG. 1 is an electronic transformer open loop test system;
FIG. 2 is an acquisition unit adaptive detection step;
fig. 3 is a schematic diagram of the principle connection of the acquisition unit detection device.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific examples.
Example 1: as shown in fig. 2-3, the acquisition unit detection device based on the self-adaptive comparison analysis technology comprises an FPGA module, an ARM module, an optical fiber sampling receiving module, an optical fiber synchronous transmitting module, a DA output module, an AD sampling module and an ethernet transceiver module, wherein the optical fiber sampling receiving module, the optical fiber synchronous transmitting module, the DA output module and the AD sampling module are connected to the FPGA module, the FPGA module is connected to the ARM module, the ARM module is connected with a man-machine interaction module and is connected with a debugging interface RJ45 through the ethernet transceiver module, and the FPGA module is used for parallel driving of a bottom module and receiving or transmitting test data in real time; the ARM module is used for data processing analysis and man-machine interaction; the optical fiber sampling receiving module is used for receiving the digital sampling value output by the tested acquisition unit; the optical fiber synchronous transmitting module is used for transmitting a synchronous signal to the acquisition unit; the DA output module is used for sending the standard source small voltage analog quantity; the AD sampling module is used for extracting standard source analog quantity in real time.
1. And an FPGA module: the processor of the FPGA module adopts a Spartan-6 series product XC6SLX150 of Xilinx, is based on a 45nm low-power consumption process, comprises 147443 logic units, a 4824Kb Block RAM special memory and 6 CMT clock management modules, has rich resources and high running speed, and realizes perfect balance of cost performance and power consumption.
The parallel signal processing capability and the instantaneity of the FPGA are utilized to control the optical fiber receiving module to acquire the output digital samples of the tested acquisition unit; the control optical fiber sending module outputs a synchronous pulse signal to the acquisition unit (when the acquisition unit working depending on the synchronous signal is detected); the DA module is controlled to output a standard source analog quantity signal; controlling the AD module to extract standard source analog quantity signals; and meanwhile, the test data are interacted with ARM.
2. ARM module: the ARM module adopts an i.MX 6 series processor of NXP, is based on Cortex-A9 kernel architecture, comprises a four-core platform, has the highest operating frequency of 1.2 GHz, and is provided with 1MB L2 cache, graphics hardware acceleration, 64-bit DDR3 or 2 channels and 32-bit LPDDR2 support. The platform integrates FlexCAN and MLB buses, PCI Express and SATA-2, provides excellent connectivity, integrates a dual-channel MIPI display screen interface, a MIPI camera interface and HDMI v1.4, and is very suitable for automatic industrial application.
The ARM module interacts test data with the FPGA, controls the test flow and analyzes the detection data; meanwhile, man-machine interaction is realized with the outside through the Ethernet, the liquid crystal and the keyboard, configuration parameters are obtained, and a detection result is output.
3. And the optical fiber sampling and receiving module is used for: the optical fiber sampling and receiving module adopts AFBR 2418TZ serial optical fiber receiver of Avago company, and has high-speed optical signal receiving capability. The AFBR 2418TZ optical fiber receiving device adopts an ST interface, has the working temperature of-40 to 85 ℃, receives data with the wavelength of 865nm, and has the maximum data rate of 50MBd, and good data compatibility.
The optical fiber sampling receiving module is used for receiving the digital sampling value output by the tested acquisition unit, converting the optical fiber signal into a level signal, inputting the level signal into the FPGA, and finishing the protocol decoding and the verification of the subsequent sampling value by the FPGA.
4. And the optical fiber synchronous transmitting module is used for: the optical fiber synchronous transmission module adopts an HFBR 1414 serial optical fiber transmitter of Avago company, has high-speed optical signal transmission capability, and can meet the serial data transmission requirement under most baud rates. The HFBR 1414 optical fiber transmitting device adopts a Tube packaging type ST interface, the working temperature is-40 to 85 ℃, the maximum rising time is 6.5 ns, the maximum falling time is 6.5 ns, and the pulse width distortion is 7.56 ns.
The optical fiber synchronous transmitting module can output B code or second pulse synchronous signals, and can be used as an external synchronous source when the tested acquisition unit needs the external synchronous signals to trigger sampling work.
5. DA output module: the module adopts four-channel, 16-bit, serial input and bipolar voltage output DAC AD5764, and can provide high-precision and bipolar data conversion. It uses the precision reference voltage source ADR02 to achieve optimal DAC performance throughout the operating temperature range. The external devices required by the 16-bit precision DAC are only a reference voltage source, a decoupling capacitor on a power pin and a reference input and an optional short circuit current setting resistor, so that cost and circuit board space can be saved. The circuit is very suitable for closed loop servo control and open loop control application.
AD5764 is a high-performance digital-to-analog converter, can ensure monotonicity, has an Integral Nonlinearity (INL) error of + -1 LSB (C-stage device), has low noise and has a build-up time of 10 mu s. And in a wider working voltage range, the rated performance is ensured. The AVDD power supply voltage ranges from +11.4V to +16.5V, the AVSS operating voltage ranges from-11.4V to-16.5V, and the nominal full range output voltage range is + -10V.
In order for the DAC to achieve optimal performance throughout the operating temperature range, a precision reference voltage source must be used. The AD5764 has built-in reference voltage source buffers, thus eliminating the need for external positive and negative reference voltage sources and associated buffers, which further saves cost and circuit board space. Because the voltages applied at the reference inputs (REFAB, REFCD) are used to generate internally buffered positive and negative reference voltages for the DAC core, any error in the external reference voltage is reflected by the output of the device.
6. AD sampling module: the analog-to-digital conversion function with high precision and high sampling rate can be realized by adopting an 18-bit successive approximation type analog-to-digital converter AD7982 and a sampling rate of 1000kSPS at maximum. AD7982 adopts 2.5V single power supply to supply power, and built-in one low-power consumption, high-speed, 18-bit non-missing-code sampling ADC, one internal conversion clock and one multifunctional serial interface port.
Each sampling begins and at the rising edge of the converted signal, the AD7982 samples the voltage difference between the differential input pins. The reference voltage is externally supplied and may be set as a power supply voltage. The power consumption and throughput rate of AD7982 vary linearly. Supporting SPI communication mode and daisy chain link mode and providing an optional busy indication.
7. An Ethernet transceiver module: the Ethernet module is composed of PHY chip, network transformer and RJ45 Ethernet interface, PHY chip adopts LXT971 network communication interface circuit of Intel company, which accords with IEEE standard, directly supports 10Mb/s/100Mb/s twisted pair application, and also supports 100Mb/s optical fiber interface. Is IEEE802.3 compliant, supports 10Base5, 10Base2, 10BaseT, 100BASE-X,100BASE-TX,100BASE-FX, and automatically detects connected media.
The FPGA configures the PHY chip through the MII interface module, is initially in an IDLE state and monitors the state of the bus, automatically enters an SFD state when detecting the preamble of the Ethernet frame, enters a data receiving state if receiving the frame delimiter of the Ethernet data frame, and starts to receive PHY chip data through the MII interface. And after all data transmission is completed and the bus is IDLE, the receiving module reenters the IDLE state and waits for the reception of the next frame data.
Example 2: a detection method of an acquisition unit detection device based on an adaptive comparison analysis technology comprises the following steps: firstly, calculating discrete instantaneous sampling values of a standard source according to configuration, and outputting a small voltage analog quantity to a tested acquisition unit after digital differential calculation, and outputting an original standard source analog quantity which is not subjected to differential calculation; secondly, accessing a standard source analog quantity which is not differentiated through an AD sampling module to be used as a standard comparison signal of the detection device; then, the digital sampling signal output by the tested acquisition unit is adaptively acquired through an optical fiber receiving module and used as a sample comparison signal of the detection device; and finally, automatically performing closed-loop analysis on the test data by using a detection device to obtain sampling transmission indexes of steady-state precision, transient characteristics and time characteristics of the tested acquisition unit, thereby realizing an independent closed-loop test function of the acquisition unit.
The detection method of the acquisition unit detection device based on the self-adaptive comparison analysis technology specifically comprises the following steps:
Step 1, two-way standard output: the ARM module acquires analog quantity parameters configured by a user, calculates analog quantity instantaneous sampling values of sampling rates, and drives the DA module to output analog quantity voltage signals through the FPGA module;
the acquisition unit acquires the small voltage signals subjected to differential processing, then an internal hardware integration circuit or a software integration algorithm restores the small voltage signals to original samples and outputs the original samples, the detection device needs to synchronously output two groups of homologous standard analog quantity signals, and one path of the standard analog quantity signals is not subjected to digital differential processing and is used as a standard source for comparison by the detection device; the other path is subjected to digital differential processing, and an output signal of the analog electronic transformer is connected to a tested acquisition unit;
After the detection device outputs a standard signal, the step 2 and the step 3 are carried out to recover the signal, so that an automatic closed-loop detection system is realized;
step 2, standard signal stoping: after standard output in the step 1, extracting one standard source signal which is not subjected to differential processing in the step 2;
The FPGA module drives the AD sampling module, analog-to-digital conversion of the input voltage analog quantity is carried out to digital sampling values, the digital sampling values are received to the detection device, each digital sampling value is accurately recorded by the FPGA to correspond to the sampling moment, and the accuracy of the test data analysis in the step 4 is improved.
Step 3, digital sampling self-adaptive receiving: after the standard output of the step 1, synchronously receiving the digital quantity sample signal output by the acquisition unit through the step 3;
The FPGA module drives the optical fiber sampling module to receive the optical fiber digital samples output by the acquisition unit, and each digital sampling value is also recorded with the receiving time accurately by the FPGA, and the sampling value protocol output by the current electronic transformer acquisition unit has more types and needs to be received and analyzed in a self-adaptive manner in a compatible manner;
The FPGA module continuously detects the maximum displacement period of an input digital signal according to the principle of the Manniche code and the non-Manniche code, distinguishes a signal coding mode, simultaneously utilizes the minimum displacement period value to determine the protocol coding baud rate, continuously carries out sampling transmission monitoring according to the baud rate, starts link transmission by a specific data initiator after the sampling link is detected stably, receives data blocks according to fixed bytes, carries out CRC (cyclic redundancy check) at the tail end of each data block, and finishes the reception after the received data blocks reach the maximum CRC;
Step 4, closed loop comparison analysis: acquiring test standard signals through the step 2, acquiring sample signals of the acquisition unit through the step 3, performing error calculation on the two groups of signals in the step 4, and detecting the transmission characteristics of the acquisition unit;
the ARM module collects original standard sampling values acquired by the FPGA module and sampling values of the samples output by the acquisition unit, a closed-loop detection system is realized, and indexes of steady-state transmission precision, transient transmission characteristics and time characteristics of the acquisition unit to be detected are automatically analyzed by adopting interpolation synchronization, fourier calculation, harmonic analysis and waveform comparison methods, so that independent self-adaptive closed-loop detection of the acquisition unit is realized.
The foregoing is merely illustrative of the present invention, and the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the scope of the present invention, and therefore, the scope of the present invention shall be defined by the scope of the appended claims.
Claims (1)
1. The detection method of the acquisition unit detection device based on the self-adaptive comparison analysis technology is characterized by comprising the following steps of: the acquisition unit detection device based on the self-adaptive comparison analysis technology comprises an FPGA module, an ARM module, an optical fiber sampling receiving module, an optical fiber synchronous transmitting module, a DA output module, an AD sampling module and an Ethernet receiving and transmitting module, wherein the optical fiber sampling receiving module, the optical fiber synchronous transmitting module, the DA output module and the AD sampling module are connected to the FPGA module, the FPGA module is connected to the ARM module, the ARM module is connected with a man-machine interaction module and is connected with a debugging interface RJ45 through the Ethernet receiving and transmitting module, and the FPGA module is used for driving a bottom layer module in parallel and receiving or transmitting test data in real time; the ARM module is used for data processing analysis and man-machine interaction; the optical fiber sampling receiving module is used for receiving the digital sampling value output by the tested acquisition unit; the optical fiber synchronous transmitting module is used for transmitting a synchronous signal to the acquisition unit; the DA output module is used for sending the standard source small voltage analog quantity; the AD sampling module is used for extracting standard source analog quantity in real time; the detection method of the acquisition unit detection device based on the self-adaptive comparison and analysis technology comprises the following steps: firstly, calculating discrete instantaneous sampling values of a standard source according to configuration, and outputting a small voltage analog quantity to a tested acquisition unit after digital differential calculation, and outputting an original standard source analog quantity which is not subjected to differential calculation; secondly, accessing a standard source analog quantity which is not differentiated through an AD sampling module to be used as a standard comparison signal of the detection device; then, the digital sampling signal output by the tested acquisition unit is adaptively acquired through an optical fiber receiving module and used as a sample comparison signal of the detection device; finally, the test data are automatically and closed-loop analyzed by a detection device, and sampling transmission indexes of steady-state precision, transient characteristics and time characteristics of the tested acquisition unit are obtained; the detection method specifically comprises the following steps:
Step 1, two-way standard output: the ARM module acquires analog quantity parameters configured by a user, calculates analog quantity instantaneous sampling values of sampling rates, and drives the DA output module to output analog quantity voltage signals through the FPGA module;
The acquisition unit acquires the voltage signals subjected to differential processing, then an internal hardware integration circuit or a software integration algorithm restores the voltage signals to original samples and outputs the original samples, the detection device needs to synchronously output two groups of homologous standard analog quantity signals, and one path of the standard analog quantity signals is not subjected to digital differential processing and is used as a standard source for comparison by the detection device; the other path is subjected to digital differential processing, and an output signal of the analog electronic transformer is connected to a tested acquisition unit;
After the detection device outputs a standard signal, the step2 and the step 3 are carried out to recover the signal;
step 2, standard signal stoping: after standard output in the step 1, extracting one standard source signal which is not subjected to differential processing in the step 2;
The FPGA module drives the AD sampling module, analog-to-digital converts the input voltage analog quantity into a digital sampling value, the digital sampling value is received to the detection device, and each digital sampling value is recorded by the FPGA at a corresponding sampling moment;
step 3, digital sampling self-adaptive receiving: after the standard output of the step 1, synchronously receiving the digital quantity sample signal output by the acquisition unit through the step 3;
The FPGA module drives the optical fiber sampling receiving module to receive the optical fiber digital samples output by the acquisition unit, and each digital sampling value is also recorded with the receiving time by the FPGA, and the sampling information is received and analyzed in a self-adaptive mode in a compatible mode;
The FPGA module continuously detects the maximum displacement period of an input digital signal according to the principle of the Manniche code and the non-Manniche code, distinguishes a signal coding mode, simultaneously utilizes the minimum displacement period value to determine the protocol coding baud rate, continuously carries out sampling transmission monitoring according to the baud rate, starts link transmission by a specific data initiator after the sampling link is detected stably, receives data blocks according to fixed bytes, carries out CRC (cyclic redundancy check) at the tail end of each data block, and finishes the reception after the received data blocks reach the maximum CRC;
Step 4, closed loop comparison analysis: acquiring test standard signals through the step 2, acquiring sample signals of the acquisition unit through the step 3, performing error calculation on the two groups of signals in the step 4, and detecting the transmission characteristics of the acquisition unit;
the ARM module collects original standard sampling values acquired by the FPGA module and sampling values of the samples output by the acquisition unit, a closed-loop detection system is realized, and indexes of steady-state transmission precision, transient transmission characteristics and time characteristics of the acquisition unit to be detected are automatically analyzed by adopting interpolation synchronization, fourier calculation, harmonic analysis and waveform comparison methods, so that independent self-adaptive closed-loop detection of the acquisition unit is realized.
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