CN203433064U - Detecting device based on analog quantity input combining unit - Google Patents
Detecting device based on analog quantity input combining unit Download PDFInfo
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- CN203433064U CN203433064U CN201320597926.4U CN201320597926U CN203433064U CN 203433064 U CN203433064 U CN 203433064U CN 201320597926 U CN201320597926 U CN 201320597926U CN 203433064 U CN203433064 U CN 203433064U
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Abstract
The utility model provides a detecting device based on an analog quantity input combining unit, which comprises the following components: an input component which is connected with an ARM chip and is used for transmitting a command signal to the ARM chip; a standard clock component which is connected with the ARM chip and is used for transmitting a standard clock to the ARM chip; the ARM chip which is connected with a signal source and a detected combining unit respectively and is used for transmitting a second pulse to the detected combining unit and transmitting a signal parameter and a digital signal to the signal source; the signal source which is connected with the detected combining unit and is used for receiving the signal parameter and transmitting a standard signal to the combining unit and the ARM chip according to the signal parameter and the digital signal; and a network message analyzer which is connected with the detected combining unit. The detecting device can quickly and accurately realize the following tests: accuracy test of the combining unit, ECT/EVT communication interface test, sampling value output interface performance test, clock synchronizing test and network environment effect test.
Description
Technical field
The utility model, about the detection technique field of intelligent electronic device, particularly about the detection technique of merge cells in intelligent electronic device, is a kind of pick-up unit based on analog input merge cells concretely.
Background technology
Along with the development of intelligent grid rapid technological improvement, digital transformer substation is more and more.Owing to having adopted optical fiber to carry out the transmission of digital quantity, there is not the AD Acquisition Error of secondary voltage drop and simulation electric energy meter in digital transformer substation, this has greatly reduced the error of conventional metered dose secondary circuit, and digitizing is the direction of world today's electric power development.
Electronic mutual inductor is the bridge to digital world as simulated world, occupies very important status in digital transformer substation, can think that electronic mutual inductor is the foundation stone of digital transformer substation.
Merge cells provides electric current and the voltage sample value of one group of time synchronized for intelligent electronic device; its major function is to collect the output signal of a plurality of mutual inductors; obtain electric system electric current and instantaneous voltage, and be transferred to electric system electric testing instrument and relay protection device with established data quality.Its each data channel can transmit the sampled value data of and many electric currents and voltage transformer (VT).
Merge cells should be able to collect the digital quantity signal of electronic type voltage transformer, electronic current mutual inductor output, also can collect and the sample simulating signal of conventional voltage mutual inductor, current transformer output or the simulation small-signal of electronic mutual inductor output, and transmit.Merge cells should be able to be exported the requirement that some groups of digital quantity signals meet respectively the different application such as relay protection, measurement, metering.
Along with the large-scale application of merge cells, its effect is more and more important, concerns quality and safe detection and obviously falls behind, and each large electrical network is carried out testing not yet comprehensively at present.Therefore, be combined the detection data of unit very little, evaluation method needs further perfect.In addition, the relevant criterion of merge cells pick-up unit, vertification regulation are incomplete, and its magnitude tracing is not yet set up with amount biography system, and the manufacturer that manufactures merge cells pick-up unit is less, and year accuracy, reliability have to be tested.
Merge cells tester of the prior art need to contrast with to-be-tested transformer output valve by standard mutual inductor, by the output valve of examination criteria mutual inductor, draws testing result.This merge cells tester is complex operation not only, and cannot the sample conversion precision of combining data detection unit self to signal.
Utility model content
The utility model is for the above-mentioned technical matters existing in prior art, a kind of pick-up unit based on analog input merge cells has been proposed, can realize fast and accurately degree of accuracy test, the test of ECT/EVT communication interface of merge cells, the performance test of sampled value output interface, clock synchronous test, network environment influence test.
The purpose of this utility model is, a kind of pick-up unit based on analog input merge cells is provided, and comprising: input block, be connected with ARM chip, and for the ARM chip to described, send command signal; Standard time clock parts, are connected with described ARM chip, for the ARM chip to described, send standard time clock; Described ARM chip, is connected with signal source, tested merge cells respectively, sends pulse per second (PPS), to described signal source transmitted signal parameter and digital signal for the merge cells to tested; Described signal source, is connected with tested merge cells, for receiving described signal parameter, according to described signal parameter and digital signal, to described merge cells and described ARM chip, sends standard signal; Network message analyser, is connected with tested merge cells, for receiving the network signal of described merge cells output, described network signal is carried out to protocol conversion, and the network signal after protocol conversion is sent to described ARM chip; Described ARM chip, is also connected with described network message analyser, for receiving the network signal after standard signal, protocol conversion, exports the testing result of described merge cells according to the network signal after standard signal, protocol conversion.
Preferably, described input block is button.
Preferably, described standard time clock parts comprise antenna and the GPS chip being connected with described antenna, and described GPS chip is for by described antenna reception satellite-signal, and outputting standard clock.
Preferably, described signal source specifically comprises: fpga chip, is connected with described ARM chip, for receiving described signal parameter, according to described signal parameter output sinusoidal signal; Voltage-type digital to analog converter, is connected with described ARM chip, for receiving described digital signal, adjusts the amplitude of described digital signal, and the digital signal after adjusting is carried out to digital-to-analog conversion obtains simulating signal; Described totalizer, is connected with diode, for receiving described simulating signal, and described simulating signal is sent to multiplication type digital to analog converter; Described multiplication type digital to analog converter, is connected with described totalizer and described fpga chip, and for described sinusoidal signal and simulating signal are multiplied each other, the signal obtaining multiplying each other carries out digital-to-analog conversion and obtains standard signal; Described diode, is connected with described totalizer, multiplication type digital to analog converter respectively, for the standard signal to described, carries out being sent to described totalizer after rectification; Analog to digital converter, is connected with described ARM chip, multiplication type digital to analog converter, for described standard signal is carried out to analog to digital conversion, and the standard signal after analog to digital conversion is sent to described ARM chip.
Preferably, the described pick-up unit based on analog input merge cells also comprises display unit, is connected, for showing the testing result of described merge cells with described ARM chip.
Preferably, described display unit is LCDs.
The beneficial effects of the utility model are, a kind of pick-up unit based on analog input merge cells of proposition, and this pick-up unit does not need standard mutual inductor to detect, easy and simple to handle; Can realize accuracy, ECT/EVT communication interface, sampling value message response time and transmission cycle, to time error and time keeping error and to time the multinomial merge cells performance test such as abnormal signal.
For above and other object of the present utility model, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of the embodiment one of a kind of pick-up unit based on analog input merge cells that Fig. 1 provides for the utility model embodiment;
The structural representation of the embodiment two of a kind of pick-up unit based on analog input merge cells that Fig. 2 provides for the utility model embodiment;
The schematic diagram that Fig. 3 is the detection means measure merge cells applying the utility model in specific embodiment and provide;
The chip figure of ARM chip in the specific embodiment that Fig. 4 provides for the utility model;
The chip figure of FPGA in the specific embodiment that Fig. 5 provides for the utility model.
Reference numeral:
Standard time clock parts 200
ARM chip 300
Network message analyser 500
Merge cells 600
Fpga chip 401
Voltage-type digital to analog converter 402
Multiplication type digital to analog converter 404
Analog to digital converter 406
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
In order to introduce in detail particular content of the present utility model, first sketch abbreviation and Key Term that the utility model relates to below.
Merge cells (Merging Unit, MU)
In order to the electric current to from secondary converter and (or) voltage data carries out the physical location of time correlation combination.Merge cells can be a component parts of mutual inductor, can be also a separate unit.
Mutual inductor (instrument transformer)
The equipment of scaling transformation voltage or electric current.Its function is mainly that high voltage or large electric current scaling transformation are become to standard low-voltage (100V) or the little electric current of standard (5A or 10A all refer to ratings), to realize standardization, the miniaturization of measurement instrument, protection equipment and automatic control equipment.Mutual inductor can also be used to separate high-voltage system simultaneously, to guarantee the safety of the person and equipment.
Electronic mutual inductor
Comprise electronic current mutual inductor (Electronic Current Transformer; ECT), electronic type voltage transformer (Electronic Voltage Transformer; EVT); it is a kind of device; by the one or more curtage sensors that are connected to transmission system and secondary conversion, formed; in order to transmission, be proportional to measured amount, supply with surveying instrument, instrument and relay protection or control device.The in the situation that of digital interface, by one group of electronic mutual inductor, share a merge cells and complete this function.
Intelligent electronic device is Intelligent Electronic Device, IED.
The structural representation of the embodiment one of a kind of pick-up unit based on analog input merge cells that Fig. 1 provides for the utility model embodiment, as shown in Figure 1, the described pick-up unit based on analog input merge cells specifically comprises:
Standard time clock parts 200, are connected with described ARM chip 300, for the ARM chip to described, send standard time clock.Be illustrated in figure 2 the structural representation of the embodiment two of a kind of pick-up unit based on analog input merge cells that the utility model embodiment provides, as shown in Figure 2, standard time clock parts 200 can comprise antenna 201 and the GPS chip 202 being connected with described antenna in concrete embodiment, described GPS chip is for passing through described antenna reception satellite-signal, and outputting standard clock.Standard time clock parts receive satellite time by GPS chip, by optical fiber, export pulse per second (PPS), with the follow-up unit that is combined, carry out time service.
Described ARM chip 300, is connected with signal source 400, tested merge cells 600 respectively, sends pulse per second (PPS), to described signal source transmitted signal parameter and digital signal for the merge cells to tested;
Described signal source 400, is connected with tested merge cells 600, for sending standard signal according to described signal parameter and digital signal to described merge cells and described ARM chip;
Described ARM chip 300, is also connected with described network message analyser, for receiving the network signal after standard signal, protocol conversion, exports the testing result of described merge cells according to the network signal after standard signal, protocol conversion.In concrete embodiment, ARM chip is by the standard signal of the analog to digital converter sampling output in signal source, contrasts the properties of test merge cells with the network message of the output of merge cells.Be mainly used in the network signal after standard of comparison signal, protocol conversion, the two unanimously illustrates that the testing result of described merge cells is qualified, otherwise is defective.
The structural representation of the embodiment two of a kind of pick-up unit based on analog input merge cells that Fig. 2 provides for the utility model embodiment, as shown in Figure 2, signal source specifically comprises:
Programmable logic device fpga chip 401, is connected with described ARM chip, for receiving described signal parameter, according to described signal parameter output sinusoidal signal.According to the signal of signal parameter configuration output respective frequencies and phase place.Fpga chip is realized the function of Direct Digital Synthesizer DDS, the frequency of conditioning signal and phase place.
Voltage-type digital to analog converter 402, is connected with described ARM chip, for receiving described digital signal, adjusts the amplitude of described digital signal, and the digital signal after adjusting is carried out to digital-to-analog conversion obtains simulating signal.
Totalizer 403, is connected with described voltage-type digital to analog converter 402, diode 405 respectively, for receiving described simulating signal, and described simulating signal is sent to multiplication type digital to analog converter;
Described multiplication type digital to analog converter 404, is connected with described totalizer and described fpga chip, and for described sinusoidal signal and simulating signal are multiplied each other, the signal obtaining multiplying each other carries out digital-to-analog conversion and obtains standard signal.Even standard signal amplitude herein, frequency, the AC signal that phase place is adjustable.
Described diode 405, is connected with described totalizer, multiplication type digital to analog converter respectively, for the standard signal to described, carries out being sent to described totalizer after rectification.Diode mainly adopts negative feedback to stablize the standard signal of output.
Analog to digital converter 406, is connected with described ARM chip, multiplication type digital to analog converter, for described standard signal is carried out to analog to digital conversion, and the standard signal after analog to digital conversion is sent to described ARM chip.
As shown in Figure 2, pick-up unit also comprises display unit 700, is connected, for showing the testing result of described merge cells with described ARM chip.In concrete embodiment, display unit, such as being LCDs LCD, shows every test result of merge cells.
The schematic diagram that Fig. 3 is the detection means measure merge cells applying the utility model in specific embodiment and provide, as shown in Figure 3, in this embodiment, display unit is LCD, voltage-type digital to analog converter is realized by DAC1, multiplication type digital to analog converter is realized by DAC2, and analog to digital converter is realized by ADC.Also, signal source realizes DDS function conditioning signal frequency and phase place by fpga chip, by DAC2 output signal, by diode pair signal, carries out rectification, forms negative feedback, reaches the effect of stabilization signal.
The chip figure of ARM chip in the specific embodiment that Fig. 4 provides for the utility model, ARM chip is responsible in pick-up unit: the command signal that receives key-press input; By LCD, show testing result; By DAC1, adjust signal amplitude; To FPGA transmitted signal parameter; Receive signal ADC sample information; Outputting standard clock; Receive pps pulse per second signal and the network signal of merge cells.As shown in Figure 4, ARM is connected with network interface chip by lead-in wires such as ETH_RMII_TX0, by SPIC serial ports, is connected with fpga chip, by serial ports, is connected with GPS module, is connected by pins such as ARM chips with display screen, button simultaneously.
The chip figure of FPGA in the specific embodiment that Fig. 5 provides for the utility model, in specific embodiment, fpga chip is such as the Cyclone III Family that adopts U.S. ALTER company, and it is powerful.As shown in Figure 5, fpga chip main circuit will consist of electronic circuits such as FPGA power circuit, clock, debugging interfaces, major function is to produce three-phase six tunnel Frequency Adjustable, the digital signal of phase modulation, artificial circuit part in conjunction with amplitude modulation forms Frequency Adjustable, amplitude modulation, phase modulation key player on a team signal, can certainly generate other shape waveform signals.Wherein, in Fig. 5 4011 is for being connected to the SPI interface of ARM chip, 4012 generations for digitizing Frequency Adjustable phase modulation (realization of FPGA inside programming), 4013 is FPGA power circuit, 4014 for offering digitizing Frequency Adjustable phase modulation circuit programmable frequency square-wave signal.
In specific embodiment, network message analyser can adopt the BSA-1200 such as the many letters of China's electricity, can directly buy.
The specific works flow process of the detection means measure merge cells based on analog input merge cells that introduction application the utility model provides respectively below.
(1), pick-up unit is combined unit and carries out time service,, to merge cells output pulse per second (PPS), receives the pulse per second (PPS) of merge cells output simultaneously, check with the standard time, with test merge cells to time error and timekeeping performance.
(2), pick-up unit is to merge cells output three-phase six tunnel AC signal, receives the network signal of merge cells output simultaneously, be combined unit and carry out the performance tests such as accuracy, communication.
(3), merge cells accuracy test: the three-phase six road standard signal sources by adjusting detecting device are exported, be input to the input terminal of the simulation small-signal of analog input formula merge cells, instrument internal gathers standard analog amount, with by network interface, read the data of the sampling of merge cells, pick-up unit to merge cells to be measured with exchange the 1min of benchmark in amplitude and the markers of each sampling number certificate analyze relatively, show amplitude and time the distribution curve of target deviation and the statistics of maximum deviation.
(4), ECT/EVT communication interface test: merge cells to be measured receives after ECT/EVT simulator sampling value message, to pick-up unit output sampling value message, pick-up unit receives the message that merge cells sends, and should conform to the value that exchanges of ECT/EVT simulator output afterwards as calculated.
(5), sampled value output interface performance test operation comprises that the test of sampling value message response time and integrity test and sampling value message send the operation of period measuring and the demonstration of test result.
(6), clock synchronous test operation comprise to time error test and time keeping error test and to time abnormal signal situation test operation and test result demonstration.
In sum, the utility model provides a kind of pick-up unit based on analog input merge cells, can realize fast and accurately degree of accuracy test, the test of ECT/EVT communication interface of merge cells, the performance test of sampled value output interface, clock synchronous test, network environment influence test.
The beneficial effect that technical solutions of the utility model are brought is:
(1) pick-up unit, based on analog input merge cells does not need standard mutual inductor to detect, easy and simple to handle;
(2), the pick-up unit based on analog input merge cells can realize accuracy, ECT/EVT communication interface, sampling value message response time and transmission cycle, to time error and time keeping error and to time the multinomial merge cells performance test such as abnormal signal.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment system, can come the hardware that instruction is relevant to complete by computer program, described program can be stored in general computer read/write memory medium, this program, when carrying out, can comprise as the flow process of the embodiment of above-mentioned each system.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
In the utility model, applied specific embodiment principle of the present utility model and embodiment are set forth, the explanation of above embodiment is just for helping to understand of the present utility model and core concept; , for one of ordinary skill in the art, according to thought of the present utility model, all will change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model meanwhile.
Claims (6)
1. the pick-up unit based on analog input merge cells, is characterized in that, the described pick-up unit based on analog input merge cells specifically comprises:
Input block, is connected with ARM chip, for the ARM chip to described, sends command signal;
Standard time clock parts, are connected with described ARM chip, for the ARM chip to described, send standard time clock;
Described ARM chip, is connected with signal source, tested merge cells respectively, sends pulse per second (PPS), to described signal source transmitted signal parameter and digital signal for the merge cells to tested;
Described signal source, is connected with tested merge cells, for sending standard signal according to described signal parameter and digital signal to described merge cells and described ARM chip;
Network message analyser, is connected with tested merge cells, for receiving the network signal of described merge cells output, described network signal is carried out to protocol conversion, and the network signal after protocol conversion is sent to described ARM chip;
Described ARM chip, is also connected with described network message analyser, for receiving the network signal after standard signal, protocol conversion, exports the testing result of described merge cells according to the network signal after standard signal, protocol conversion.
2. the pick-up unit based on analog input merge cells according to claim 1, is characterized in that, described input block is button.
3. the pick-up unit based on analog input merge cells according to claim 1, it is characterized in that, described standard time clock parts comprise antenna and the GPS chip being connected with described antenna, described GPS chip is for passing through described antenna reception satellite-signal, and outputting standard clock.
4. the pick-up unit based on analog input merge cells according to claim 1, is characterized in that, described signal source specifically comprises:
Fpga chip, is connected with described ARM chip, for receiving described signal parameter, according to described signal parameter output sinusoidal signal;
Voltage-type digital to analog converter, is connected with described ARM chip, for receiving described digital signal, adjusts the amplitude of described digital signal, and the digital signal after adjusting is carried out to digital-to-analog conversion obtains simulating signal;
Totalizer, is connected with described voltage-type digital to analog converter, diode respectively, for receiving described simulating signal, and described simulating signal is sent to multiplication type digital to analog converter;
Described multiplication type digital to analog converter, is connected with described totalizer and described fpga chip, and for described sinusoidal signal and simulating signal are multiplied each other, the signal obtaining multiplying each other carries out digital-to-analog conversion and obtains standard signal;
Described diode, is connected with described totalizer, multiplication type digital to analog converter respectively, for the standard signal to described, carries out being sent to described totalizer after rectification;
Analog to digital converter, is connected with described ARM chip, multiplication type digital to analog converter, for described standard signal is carried out to analog to digital conversion, and the standard signal after analog to digital conversion is sent to described ARM chip.
5. the pick-up unit based on analog input merge cells according to claim 1, it is characterized in that, the described pick-up unit based on analog input merge cells also comprises display unit, is connected, for showing the testing result of described merge cells with described ARM chip.
6. the pick-up unit based on analog input merge cells according to claim 5, is characterized in that, described display unit is LCDs.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN104007346A (en) * | 2014-05-28 | 2014-08-27 | 广西电网公司电力科学研究院 | Analog quantity merging unit transient state delay test method based on frequency scanning |
| CN110456300A (en) * | 2019-09-17 | 2019-11-15 | 贵州电网有限责任公司 | A kind of acquisition unit detection device and method based on adaptive comparison analytical technology |
| CN116132343A (en) * | 2023-02-13 | 2023-05-16 | 国网四川省电力公司电力科学研究院 | Online monitoring terminal simulation test system and method for primary equipment of intelligent substation |
| CN110456300B (en) * | 2019-09-17 | 2024-05-03 | 贵州电网有限责任公司 | Acquisition unit detection device and method based on self-adaptive comparison analysis technology |
-
2013
- 2013-09-26 CN CN201320597926.4U patent/CN203433064U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN103487695B (en) * | 2013-09-26 | 2016-05-25 | 国家电网公司 | Based on the checkout gear of analog input merge cells |
| CN104007346A (en) * | 2014-05-28 | 2014-08-27 | 广西电网公司电力科学研究院 | Analog quantity merging unit transient state delay test method based on frequency scanning |
| CN104007346B (en) * | 2014-05-28 | 2017-02-22 | 广西电网公司电力科学研究院 | Analog quantity merging unit transient state delay test method based on frequency scanning |
| CN110456300A (en) * | 2019-09-17 | 2019-11-15 | 贵州电网有限责任公司 | A kind of acquisition unit detection device and method based on adaptive comparison analytical technology |
| CN110456300B (en) * | 2019-09-17 | 2024-05-03 | 贵州电网有限责任公司 | Acquisition unit detection device and method based on self-adaptive comparison analysis technology |
| CN116132343A (en) * | 2023-02-13 | 2023-05-16 | 国网四川省电力公司电力科学研究院 | Online monitoring terminal simulation test system and method for primary equipment of intelligent substation |
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Granted publication date: 20140212 |