CN110429140A - A kind of super node MOSFET structure and preparation method thereof - Google Patents

A kind of super node MOSFET structure and preparation method thereof Download PDF

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Publication number
CN110429140A
CN110429140A CN201910721871.5A CN201910721871A CN110429140A CN 110429140 A CN110429140 A CN 110429140A CN 201910721871 A CN201910721871 A CN 201910721871A CN 110429140 A CN110429140 A CN 110429140A
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inverted trapezoidal
epitaxial layer
area
layer
trapezoidal slot
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黄平
鲍利华
顾海颖
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Shanghai Zhen Xin Microelectronics Science And Technology Ltd
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Shanghai Zhen Xin Microelectronics Science And Technology Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

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Abstract

Super node MOSFET structure disclosed by the invention, including N+ substrate layer, N- epitaxial layer, wherein N- epitaxial layer is located on the upper surface of N+ substrate layer, source, grid are set on N- epitaxial layer, it is characterized in that, it is installed with inverted trapezoidal slot in the area P of the source electrode, ion is injected in the inverted trapezoidal slot in the area P, inverted trapezoidal slot described in the ion pair carries out injection doping and forms an inverted trapezoidal p type island region domain.The invention also discloses the preparation methods of the super node MOSFET structure.Compared with the prior art, the invention has the following advantages: (1) area P opens inverted trapezoidal slot, i.e. size of the upper dimension of slot greater than the small portion of slot；Injection doping is carried out to side wall convenient for ion implanting in this way, to form p type island region domain.(2) depth of the area P fluting can achieve substrate, and groove depth is also adjustable in epitaxial layer.(3) area P is once formed with ion implanting, and implantation dosage can fully control.

Description

A kind of super node MOSFET structure and preparation method thereof
Technical field
The present invention relates to technical field of semiconductor device preparation, in particular to a kind of super node MOSFET structure and its preparation side Method.
Background technique
Referring to Fig. 1, the basic functional principle of super-junction structure is as follows:
1. the area vertical conduction N- is clipped among the area P- on both sides.When shutdown, form the PN junction of two reverse bias: P- and Vertical conduction N-, P- and substrate/epi layers of extension N-.
2.P- and vertical conduction N- forms PN junction reverse bias, and PN junction depletion layer increases, and establishes transversely and horizontally electric field；Together When, P- and substrate/epitaxial layer N- formation PN junction are also reverse bias shape, generate wide depletion layer, and establish vertical electric field.
3. adding reverse bias voltage in drift layer, a transverse electric field will be generated, PN junction is exhausted.When voltage reaches certain When value, drift layer is completely depleted, will play the role of voltage support layer.Therefore, breakdown voltage depends only on the thickness of epitaxial layer Degree, and it is unrelated with doping concentration.
4. when conducting, the electric field of grid and source electrode is by the area the P transoid under grid, and it is conductive to generate N-type for the area P in face under the gate Channel, meanwhile, the electronics of source area enters the vertical area N- by conducting channel, the positive charge hole in the area N- is neutralized, thus extensive The N-type characteristic being depleted again, therefore conducting channel is formed, the vertical area N- doping concentration is high, has lower resistivity, therefore Conducting resistance is low.
Due to N-type to be prepared and the alternatively distributed structure of p-type, there are mainly two types of methods at present: directly by layer Ion implanting+epitaxial growth method (referring to fig. 2)；Second method is then fluting inside and outside prolongs in slot (referring to Fig. 3) again. The former technique is opposite to be easy to control, but the program of technique is more, at high cost；The latter is at low cost, but is not easy to guarantee property in groove The consistency of energy.
The preparation method of existing super node MOSFET structure has the following problems
More than 1. ion implanting+repeatedly (usual extension is primary, is then injected into primary for epitaxy；Circulation is multiple).Technique is multiple It is miscellaneous, at high cost；And the charge balance in the area N and the area P is difficult to control；
2. deep etching+epitaxy (in N-/N+ on piece, fluting, then p-type extension, forms p type island region domain).Epitaxial layer The charge balance in the bad control of concentration, the same area N and the area P is difficult to control.
Just because of the problem of problem for having these many, the especially area N and the area P charge balance control, the present invention proposes new Super node MOSFET structure and new production method.
Summary of the invention
The first technical problem to be solved by the present invention is for above-mentioned technical problem present in the prior art, especially It is the problem of area N and the area P charge balance control and a kind of new super node MOSFET structure is provided.
The second technical problem to be solved by the present invention is to provide the preparation method of above-mentioned new super node MOSFET structure.
As the super node MOSFET structure of first aspect present invention, including N+ substrate layer, N- epitaxial layer, wherein N- epitaxial layer On the upper surface of N+ substrate layer, source, grid are set on N- epitaxial layer, set wherein being opened up in the area P of the source electrode There is inverted trapezoidal slot, ion is injected in the inverted trapezoidal slot in the area P, inverted trapezoidal slot described in the ion pair carries out injection doping Form an inverted trapezoidal p type island region domain.
In a preferred embodiment of the invention, the depth of the inverted trapezoidal slot reaches the N+ substrate layer.
The preparation method of super node MOSFET structure as second aspect of the present invention, includes the following steps:
Step 1: the extension N- epitaxial layer on N+ substrate layer；
Step 2: one first oxide layer is formed on the N- epitaxial layer, and using photoetching or/and engraving method described The area P window is formed in first oxide layer, the area P window exposes the N- epitaxial layer；
Step 3: etching an inverted trapezoidal slot in the N- epitaxial layer in the area every P window；
Step 4: injecting boron ion to each inverted trapezoidal slot, inject boron ion after annealing on the side wall of each inverted trapezoidal slot Form p type island region domain；
Step 6: fill oxide into each inverted trapezoidal slot and in remaining first oxide layer forms one second oxidation Layer；
Step 7: etching or CMP fall the second oxide layer and remaining first oxide layer, expose the N- epitaxial layer but Include the oxide in each inverted trapezoidal slot；
Step 8: the grid and source electrode in power MOSFET are made on the N- epitaxial layer.
In a preferred embodiment of the invention, the inverted trapezoidal slot position is in the N- epitaxial layer.
In a preferred embodiment of the invention, the inverted trapezoidal groove depth just reaches N+ substrate layer.
Due to using technical solution as above, compared with the prior art, the invention has the following advantages:
(1) area P opens inverted trapezoidal slot, i.e. size of the upper dimension of slot greater than the small portion of slot；It is convenient for ion implanting opposite side in this way Wall carries out injection doping, to form p type island region domain.
(2) depth of the area P fluting can achieve substrate, and groove depth is also adjustable in epitaxial layer.
(3) area P is once formed with ion implanting, and implantation dosage can fully control；This is different from repeatedly injection+multiple extension Method (implantation dosage has external diffusion in multiple high temp extension, and exact dose is more difficult to control) and deep trouth+epitaxy (dosage of extension It is accurate to control no ion implanting).
Detailed description of the invention
Fig. 1 is the basic functional principle schematic diagram of super-junction structure.
Fig. 2 is existing directly by the super node MOSFET structure system of ion implanting+epitaxial growth method in layer Standby schematic diagram.
Fig. 3 is then existing fluting inside and outside prolongs again in slot and prepares super node MOSFET structure and prepare schematic diagram.
Fig. 4 is a kind of schematic diagram of super node MOSFET structure of the present invention.
Fig. 5 is the schematic diagram of present invention extension N- epitaxial layer on N+ substrate layer.
Fig. 6 is that the present invention forms one first oxide layer on the N- epitaxial layer and forms the schematic diagram of the area P window.
Fig. 7 is that the present invention etches an inverted trapezoidal slot schematic diagram in the N- epitaxial layer in the area every P window.
Fig. 8 is the present invention to each inverted trapezoidal slot injection boron ion, injects boron ion after annealing in each inverted trapezoidal slot The schematic diagram in p type island region domain is formed on side wall.
Fig. 9 is present invention fill oxide into each inverted trapezoidal slot and in remaining first oxide layer, forms one the Dioxide layer schematic diagram.
Figure 10 is that present invention etching or CMP fall the second oxide layer and remaining first oxide layer, is exposed outside the N- Prolong layer but the schematic diagram including the oxide in each inverted trapezoidal slot.
Figure 11 is grid and source electrode schematic diagram of the present invention on the N- epitaxial layer in production power MOSFET.
Figure 12 is the schematic diagram of another super node MOSFET structure of the present invention.
Specific embodiment
Carry out the present invention is described in detail below in conjunction with the drawings and specific embodiments.
Referring to fig. 4, super node MOSFET structure shown in figure, including N+ substrate layer 100, N- epitaxial layer 200, wherein outside N- Prolong layer 299 to be located on the upper surface of N+ substrate layer 100, source 310, grid 320 are set on N- epitaxial layer 200, wherein The area P of source electrode 310 is installed with inverted trapezoidal slot 210, and ion, ion pair inverted trapezoidal slot are injected in the inverted trapezoidal slot 210 in the area P 210 carry out the p type island region domain 211 that injection doping forms an inverted trapezoidal.The depth of inverted trapezoidal slot 210 reaches N+ substrate layer 200.
The preparation method of above-mentioned super node MOSFET structure includes the following steps:
Step 1: referring to Fig. 5, the extension N- epitaxial layer 200 on N+ substrate layer 100；
Step 2: referring to Fig. 6, one first oxide layer 400 is formed on N- epitaxial layer 200, and use photoetching or/and etching Method forms the area P window 410 in the first oxide layer 400, and the area P window 410 exposes N- epitaxial layer 200；
Step 3: referring to Fig. 7, etching an inverted trapezoidal slot 210 in the N- epitaxial layer 200 in the area every P window 410； 210 depth of dovetail groove just reaches N+ substrate layer 200.
Step 4: referring to Fig. 8, injecting boron ion to each inverted trapezoidal slot 210, injection boron ion after annealing is in each ladder P type island region domain 211 is formed on the side wall of shape slot 210；
Step 6: the fill oxide into each inverted trapezoidal slot 210 and in remaining first oxide layer 420 referring to Fig. 9, Form one second oxide layer 500；,
Step 7: falling the second oxide layer 500 and remaining first oxide layer 420 referring to Figure 10 etching or CMP, expose N- epitaxial layer 200 but include oxide 510 in each inverted trapezoidal slot 210；
Step 8: referring to Figure 11, the grid 320 and source electrode 310 in power MOSFET are made on N- epitaxial layer 200.
Referring to Figure 12, super node MOSFET structure shown in figure, including N+ substrate layer 100, N- epitaxial layer 200, wherein N- Epitaxial layer 299 is located on the upper surface of N+ substrate layer 100, and source 310, grid 320 are arranged on N- epitaxial layer 200, wherein It is installed with inverted trapezoidal slot 210 in the area P of source electrode 310, ion, ion pair inverted trapezoidal are injected in the inverted trapezoidal slot 210 in the area P Slot 210 carries out the p type island region domain 211 that injection doping forms an inverted trapezoidal.The depth of inverted trapezoidal slot 210, which reaches, is located at N+ substrate layer 200 It is interior.

Claims (5)

1. super node MOSFET structure, including N+ substrate layer, N- epitaxial layer, wherein N- epitaxial layer is located at the upper surface of N+ substrate layer On, source, grid are set on N- epitaxial layer, which is characterized in that are installed with inverted trapezoidal slot, In in the area P of the source electrode Ion is injected in the inverted trapezoidal slot in the area P, inverted trapezoidal slot described in the ion pair carries out injection doping and forms an inverted trapezoidal P Type region.
2. super node MOSFET structure as described in claim 1, which is characterized in that the depth of the inverted trapezoidal slot reaches the N+ Substrate layer.
3. the preparation method of super node MOSFET structure, which comprises the steps of:
Step 1: the extension N- epitaxial layer on N+ substrate layer；
Step 2: one first oxide layer is formed on the N- epitaxial layer, and using photoetching or/and engraving method described first The area P window is formed in oxide layer, the area P window exposes the N- epitaxial layer；
Step 3: etching an inverted trapezoidal slot in the N- epitaxial layer in the area every P window；
Step 4: injecting boron ion to each inverted trapezoidal slot, injection boron ion after annealing is formed on the side wall of each inverted trapezoidal slot P type island region domain；
Step 6: fill oxide into each inverted trapezoidal slot and in remaining first oxide layer forms one second oxide layer；
Step 7: etching or CMP fall the second oxide layer and remaining first oxide layer, expose the N- epitaxial layer but include Oxide in each inverted trapezoidal slot；
Step 8: the grid and source electrode in power MOSFET are made on the N- epitaxial layer.
4. the preparation method of super node MOSFET structure as claimed in claim 3, which is characterized in that the inverted trapezoidal slot position is in institute It states in N- epitaxial layer.
5. the preparation method of super node MOSFET structure as claimed in claim 3, which is characterized in that the inverted trapezoidal groove depth is rigid Reach N+ substrate layer well.
CN201910721871.5A 2019-08-06 2019-08-06 A kind of super node MOSFET structure and preparation method thereof Pending CN110429140A (en)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050250257A1 (en) * 2004-05-10 2005-11-10 Semiconductor Components Industries, Llc. Method of forming a super-junction semiconductor device
US20060273384A1 (en) * 2005-06-06 2006-12-07 M-Mos Sdn. Bhd. Structure for avalanche improvement of ultra high density trench MOSFET
US20130043528A1 (en) * 2011-08-19 2013-02-21 Yung-Fa Lin Power transistor device and fabricating method thereof
US20130203229A1 (en) * 2012-02-02 2013-08-08 Yung-Fa Lin Method of reducing surface doping concentration of doped diffusion region, method of manufacturing super junction using the same and method of manufacturing power transistor device
CN103247534A (en) * 2012-02-14 2013-08-14 茂达电子股份有限公司 Method for manufacturing power transistor component with super junction
US20150076594A1 (en) * 2013-09-19 2015-03-19 Force Mos Technology Co., Ltd. Super-junction structures having implanted regions surrounding an n epitaxial layer in deep trench
CN106783620A (en) * 2016-12-05 2017-05-31 西安龙腾新能源科技发展有限公司 Hyperconjugation VDMOS device structure of anti-EMI filter and preparation method thereof
CN107134492A (en) * 2016-02-26 2017-09-05 苏州东微半导体有限公司 Super junction power device and its manufacture method
KR20170122335A (en) * 2016-04-26 2017-11-06 파워큐브세미 (주) SiC Super junction MOSFET using pillar oxide and manufacturing method thereof
CN109427883A (en) * 2017-08-23 2019-03-05 深圳市敦为技术有限公司 A kind of manufacturing method of novel oxidized silicon layer assisted depletion super-junction structure

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050250257A1 (en) * 2004-05-10 2005-11-10 Semiconductor Components Industries, Llc. Method of forming a super-junction semiconductor device
US20060273384A1 (en) * 2005-06-06 2006-12-07 M-Mos Sdn. Bhd. Structure for avalanche improvement of ultra high density trench MOSFET
US20130043528A1 (en) * 2011-08-19 2013-02-21 Yung-Fa Lin Power transistor device and fabricating method thereof
CN102956689A (en) * 2011-08-19 2013-03-06 茂达电子股份有限公司 Power transistor device and manufacturing method thereof
US20130203229A1 (en) * 2012-02-02 2013-08-08 Yung-Fa Lin Method of reducing surface doping concentration of doped diffusion region, method of manufacturing super junction using the same and method of manufacturing power transistor device
CN103247533A (en) * 2012-02-02 2013-08-14 茂达电子股份有限公司 Method for manufacturing power transistor component
CN103247534A (en) * 2012-02-14 2013-08-14 茂达电子股份有限公司 Method for manufacturing power transistor component with super junction
US20150076594A1 (en) * 2013-09-19 2015-03-19 Force Mos Technology Co., Ltd. Super-junction structures having implanted regions surrounding an n epitaxial layer in deep trench
CN107134492A (en) * 2016-02-26 2017-09-05 苏州东微半导体有限公司 Super junction power device and its manufacture method
KR20170122335A (en) * 2016-04-26 2017-11-06 파워큐브세미 (주) SiC Super junction MOSFET using pillar oxide and manufacturing method thereof
CN106783620A (en) * 2016-12-05 2017-05-31 西安龙腾新能源科技发展有限公司 Hyperconjugation VDMOS device structure of anti-EMI filter and preparation method thereof
CN109427883A (en) * 2017-08-23 2019-03-05 深圳市敦为技术有限公司 A kind of manufacturing method of novel oxidized silicon layer assisted depletion super-junction structure

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