CN110400788A - A kind of test structure and test method checking semiconductor device design rule - Google Patents
A kind of test structure and test method checking semiconductor device design rule Download PDFInfo
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- CN110400788A CN110400788A CN201810381493.6A CN201810381493A CN110400788A CN 110400788 A CN110400788 A CN 110400788A CN 201810381493 A CN201810381493 A CN 201810381493A CN 110400788 A CN110400788 A CN 110400788A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The present invention relates to a kind of test structures and test method for checking semiconductor device design rule.The test structure includes several test cells, and the test structure has several test cells, and each test cell includes: at least one doped region；Several first electrical connectors, positioned at the lower section of the doped region；Several second electrical connectors, positioned at the top of the doped region；Each doped region is connected in series with first electrical connector and second electrical connector respectively；Wherein, the size of the doped region of the different test cells is different, by measuring and judging whether the resistance of each test cell is consistent with by resistance expected from semiconductor device design rule, determine that the minimum dimension for the doped region of test cell being consistent with by resistance expected from semiconductor device design rule is the minimum dimension of the semiconductor device design rule.The design rule of doped region minimum dimension can be decided by the test structures and methods.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of survey for checking semiconductor device design rule
Try structure and test method.
Background technique
Ic manufacturing technology is a complicated technique, and technology innovation is quickly.The high-order packaged type of product at present
Unit price is high, if chip testing can be carried out before packaging, finds in the presence of defective products wafer, that is, is marked, until
These defective products marked are given up before back segment encapsulation procedure, unnecessary packaging cost can be saved.
Include for the method for wafer test in the prior art it is a variety of, the method for most common of them is wafer acceptance test
(wafer acceptance test, WAT), the WAT method are to carry out test for special resolution chart (test key) to lead to
Whether cross electrical parameter normal and stable to control each step process.
Other than WAT test, design rule check (DRC, Design usually also will do it in device preparation technology
Rule Check) carry out check pattern, whether closed according to the result that DRC is checked come test design regular (design rule) design
Reason.Regular (rule) fixed excessive, can be safer in technique, but this will sacrifice chip area, if fixed is too small, window in technique
Mouth not enough, finally influences the yield rate of client.In addition, with the technique adjustment of online (inline), some rules may be wanted also
It is corrected with the adjustment of technique, design rule check and technique are used cooperatively, and DRC tests structure will consider in design
To the application different in design.
Currently, many factories of this design rule of N trap (Nwell) minimum area and without check, this give practical application
Potential risks are brought, N trap is poor to photoresist resolution in Lithography, if the smaller of N trap design is possible to develop
When show not open, lead to circuit breaker, thus how efficiently to detect this design rule of N trap (Nwell) minimum area become urgently
Problem to be solved.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of test structure for checking semiconductor device design rule, the test structure has several
Test cell, each test cell include:
At least one doped region；
Several first electrical connectors, positioned at the lower section of the doped region；
Several second electrical connectors, positioned at the top of the doped region；
Each doped region is connected in series with first electrical connector and second electrical connector respectively；
Wherein, the size of the doped region of the different test cells is different, by measuring and judging that each test is single
Whether the resistance of member is consistent with by resistance expected from semiconductor device design rule, determines and pre- by semiconductor device design rule
The minimum dimension of the doped region for the test cell that the resistance of phase is consistent is the minimum dimension of the semiconductor device design rule.
Optionally, the quantity of the doped region of the same test cell is greater than one, and the same test cell is mixed
The size in miscellaneous area is identical.
Optionally, the quantity for the doped region that each test cell includes is all the same.
Optionally, the quantity for the doped region that each test cell includes is even number, and the same test is single
The doped region of member connects the doped region to be formed and be connected two-by-two by first electrical connector, and the doped region connected two-by-two is logical
Second electrical connector is crossed to be connected in series；
Alternatively, the quantity for the doped region that each test cell includes is odd number, the same test cell
Doped region connect to form the doped region connected two-by-two and a residue is unpaired and with by first electrical connector
One electrical connector connection doped region, the doped region connected two-by-two and the residue it is unpaired and with the first electrical connector
The doped region of connection is connected in series by second electrical connector.
Optionally, the quantity for the doped region that each test cell includes is one, several first electrical connectors that
This connection.
Optionally, the doped region of each test cell connects one first electrical connector, first electrical connector jointly
It is connected to one second electrical connector by deriving structure, the doped region of each test cell is also respectively connected with the second different electricity
Connector.
Optionally, the test cell further includes substrate and common end, and the test cell is formed on the substrate, institute
Stating common end is substrate exit, and second electrical connector at the head and the tail both ends of each test cell is separately connected a test point,
The high-end voltage of one test point electric connection of power supply of each test cell, another test point electrical connection of each test cell
The lower terminal voltage of power supply, the common end of each test cell connect reference voltage, and the reference voltage is less than or equal to described
The lower terminal voltage of power supply.
Optionally, it is reduced or increased to the size gradient of the doped region of several test cells.
Optionally, the doped region includes well region；N+ active area is also formed on the surface of the doped region；
First electrical connector includes deep trap, and the deep trap is identical as the conduction type of the doped region；
Second electrical connector includes:
Metal layer is set to the top of two doped regions of electrical connection；
Contact hole, between the metal layer and the doped region.
The present invention also provides a kind of test method using above-mentioned test structure, the test method includes:
The resistance of each test cell is measured respectively；
Judge whether the resistance of each test cell is consistent with by resistance expected from semiconductor device design rule；
The minimum dimension of the doped region for the test cell being consistent with by resistance expected from semiconductor device design rule determines
For the minimum dimension of the semiconductor device design rule.
Optionally, the step of resistance for measuring each test cell respectively includes: according to each test cell
Including doped region quantity, it includes a doped region that the resistance of each test cell is converted into each test cell only respectively
Resistance.
Optionally, the resistance for judging each test cell whether with by semiconductor device design rule expected from electricity
It includes: to judge whether the resistance of each test cell is less than the resistance of resistance value mutation that resistance, which is consistent, is less than resistance value and occurs to dash forward
The resistance of change is consistent with by resistance expected from semiconductor device design rule.
Optionally, the resistance that the resistance value mutates increased dramatically for the resistance value or reduced resistance.
The present invention provides a kind of test structure and method for checking semiconductor device design rule, the test structure packets
Several test cells are included, each test cell includes at least one doped region；Wherein, the doped region of the different test cells
Size is different, by measure and judge each test cell resistance whether with by electricity expected from semiconductor device design rule
Resistance is consistent, and determines that the minimum dimension of the doped region for the test cell being consistent with by resistance expected from semiconductor device design rule is
The minimum dimension of the semiconductor device design rule, can be doped region minimum dimension by the test structures and methods
Design rule is decided.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the schematic top plan view that structure is tested described in one embodiment of the invention；
Fig. 2 is the schematic cross-sectional view that structure is tested described in one embodiment of the invention；
Fig. 3 is the structural schematic diagram of the Blocked portion of test structure described in Fig. 2；
Fig. 4 is the schematic cross-sectional view along the direction A-A1 that structure is tested described in Fig. 1；
Fig. 5 is the process flow chart of test method described in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
The present invention in order to solve the problems in the existing technology, provide it is a kind of inspection semiconductor device design rule
Structure is tested, the test structure has several test cells, and each test cell includes:
At least one doped region；
Several first electrical connectors, positioned at the lower section of the doped region；
Several second electrical connectors, positioned at the top of the doped region；
Each doped region is connected in series with first electrical connector and second electrical connector respectively；
Wherein, the size of the doped region of the different test cells is different, by measuring and judging that each test is single
Whether the resistance of member is consistent with by resistance expected from semiconductor device design rule, determines and pre- by semiconductor device design rule
The minimum dimension of the doped region for the test cell that the resistance of phase is consistent is the minimum dimension of the semiconductor device design rule.
In the test structure, each test cell may include doped region or comprising the identical doping of multiple areas
Area is described further with regard to different embodiments below.
Embodiment one
The test structure is further described with reference to the accompanying drawing.Wherein, Fig. 2 is to test described in the embodiment
The structural schematic diagram of structure.
Specifically, there are three connecting pins for test structure tool in the present invention, and one connects high-end (high), one connect it is low
It holds (low), there are one public termination substrates, and single doped region (such as N trap) is passed through the first electricity in the test structure
Connector (such as deep N-well) combines the second electrical connector (such as the first metal layer) to form test cell, wherein different is described
The size of the doped region of test cell is different, by measure and judge each test cell resistance whether with by semiconductor device
Resistance expected from part design rule is consistent, and determines the test cell being consistent with by resistance expected from semiconductor device design rule
The minimum dimension of doped region is the minimum dimension of the semiconductor device design rule.Wherein, each test of the judgement is single
Whether the resistance of member includes: to judge each test cell with the method being consistent by resistance expected from semiconductor device design rule
Resistance whether be less than resistance value mutation resistance, less than resistance value mutate resistance i.e. and by semiconductor device design advise
Then expected resistance is consistent.
Specifically, Fig. 2 is the schematic cross-sectional view of the test structure, and Fig. 3 is the Blocked portion that structure is tested described in Fig. 2
Structural schematic diagram.
The test structure has several test cells, and each test cell includes:
At least one doped region；
Several first electrical connectors, positioned at the lower section of the doped region；
Several second electrical connectors, positioned at the top of the doped region；
Each doped region is connected in series with first electrical connector and second electrical connector respectively；
Wherein, the size of the doped region of the different test cells is different, by measuring and judging that each test is single
Whether the resistance of member is consistent with by resistance expected from semiconductor device design rule, determines and pre- by semiconductor device design rule
The minimum dimension of the doped region for the test cell that the resistance of phase is consistent is the minimum dimension of the semiconductor device design rule.
In this embodiment, the quantity for the doped region that each test cell includes is one, and described several first are electrically connected
Fitting is connected to each other.
Optionally, the doped region of each test cell connects one first electrical connector, first electrical connector jointly
It is connected to one second electrical connector by deriving structure, the doped region of each test cell is also respectively connected with the second different electricity
Connector.
Optionally, as shown in Fig. 2, the deriving structure 108 includes contact hole or plug or large scale doped region etc.,
And it is confined to a certain kind, details are not described herein.
Specifically, the quantity for the doped region 102 that each test cell includes is one, each doped region respectively with one first
Electrical connector 101 is connected with second electrical connector, and the first electrical connector of each test cell is connected to each other and draws lining
A test point is connected to behind bottom, the doped region of each test cell is individually drawn and is separately connected through the second different electrical connectors
Different test points, as shown in Figure 2.
Wherein, the projected area of the doped region 102 described in different test cells is different, optionally, several surveys
It is reduced or increased with trying the size gradient of the doped region of unit.
In one embodiment of this invention, the projected area of the doped region 102 of different test cells in the horizontal plane
The amplitude being decreased or increased is, for example, 2%, 5%, 8%, 10% etc., it is not limited to a certain numberical range.
Wherein, the doped region, first electrical connector and second electrical connector are located in different layers, from
Under be up followed successively by the first electrical connector, doped region, the second electrical connector.
Optionally, the test structure may include substrate, and substrate can be at least one in the following material being previously mentioned
Kind: silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.
Optionally, the substrate selects p-type polysilicon in this application.
First electrical connector includes deep trap, and the deep trap is identical as the conduction type of the doped region, in the present invention
A specific embodiment in, first electrical connector includes deep N-well, is set in the substrate, wherein the deep N-well
Forming method can select conventional method, the depth of the deep N-well be controlled by controlling the energy of ion implanting, so that institute
It states deep N-well and is located at target depth.
The first electrical connector 101 can be a complete deep trap in the embodiment, and the doped region of each test cell is equal
It is connect with the complete deep trap, as shown in Figure 2.The side of the doped region of each test cell shares first electrical connector 101
And one second electrical connector is connected to by a deriving structure, it is ultimately connected to a test point.The doping of each test cell
The other side in area is separately connected the second different electrical connectors, is finally respectively connected to different test points.So that each survey
Examination unit is provided with the test point at head and the tail both ends.
Wherein, the type of the doped region is not limited to a certain kind, such as the doped region formed by ion implanting, or
Person passes through the doped region etc. diffuseed to form, and the doped region may include various well regions, drift region etc. in the present invention.Wherein,
The doped region is N trap or p-well, it is not limited to a certain.
The doped region is N trap, the test structure including other kinds of doped region in one embodiment of the invention
It is similar with what it is including the N trap with test method.
Wherein, when the doped region of each test cell is N trap, several N traps are spaced apart from each other setting, and in phase
It is provided with p-well between the adjacent N trap, there is N trap and p-well as shown in Figure 3 to be spaced apart from each other the structure being arranged alternately.
Wherein the N trap executes after the deep N-well ion implanting, and is controlled by the energy of control ion implanting
The depth of the N trap is made, so that the N trap is located at target depth.
The deep N-well and N trap can have same or different doping concentration, specifically can according to actual needs into
Row selection.
Optionally, as shown in Fig. 2, second electrical connector includes:
Metal layer 104 is set to the top of two doped regions of electrical connection；
Contact hole 103, between the metal layer and the doped region.
Wherein, the forming method of the metal layer and the contact hole can select method commonly used in the art, herein not
It repeats again.
It should be noted that the contact hole can also be replaced using through-hole or through silicon via, the metal layer can also be used
Other metallization materials replace, and the modification can be applied in the embodiment of the invention.
Optionally, N+ active area 107 is also formed on the surface of the doped region.
Optionally, the test cell further includes substrate and common end 105, and the test cell is formed in the substrate
On, the common end is substrate exit, and second electrical connector at the head and the tail both ends of each test cell is separately connected a survey
Pilot, the high-end voltage of a test point electric connection of power supply of each test cell, another test point of each test cell
The common end of the lower terminal voltage of electric connection of power supply, each test cell connects reference voltage, and the reference voltage is less than or waits
In the lower terminal voltage of the power supply.
Wherein, as shown in Fig. 2, the first electrical connector 101 of each test cell draws substrate and one by deriving structure 108
Second electrical connector connects, the doped region of each test cell is realized respectively each by N+ active area 107 and the second different electricity
The electrical connection of connector.Common end 105 is set in p-well, is realized by P+ active area 106 and is electrically connected with reference voltage.
Optionally, the test structure still further comprises the isolation structure being set in the substrate, for phase to be isolated
The adjacent doped region, wherein the isolation structure can be isolation structure commonly used in the art, such as fleet plough groove isolation structure
Deng.
The present invention provides a kind of test structure for checking semiconductor device design rule, each test cell includes one and mixes
Miscellaneous area；Wherein, the size of the doped region of different test cells is different.Second electrical connector at the head and the tail both ends of each test cell
It is separately connected a test point, the high-end voltage of a test point electric connection of power supply of each test cell, another survey of each test cell
The common end of the lower terminal voltage of pilot electric connection of power supply, each test cell connects reference voltage.
By the test point at the head and the tail both ends by each test cell, the resistance of each test cell is measured respectively.Wherein
There is resistance value to increased dramatically several times or reduce the situation of several times being the situation of resistance value mutation in the resistance of some test cell,
The resistance of the test cell is the resistance that resistance value mutates.
Judge whether the resistance of each test cell is less than the resistance of resistance value mutation, the resistance to mutate less than resistance value
It is consistent with by resistance expected from semiconductor device design rule.
In the test cell being consistent with by resistance expected from semiconductor device design rule, the minimum dimension of doped region is half
The minimum dimension of conductor device design rule.It can be the design rule of doped region most size by the test structures and methods
It decides.
Embodiment two
What is different from the first embodiment is that the quantity of the doped region of each test cell is greater than one in the embodiment, the same institute
The size for stating the doped region of test cell is identical.When a doped region is only arranged as measurement body in each test cell, strictly according to the facts
Example one is applied, not can avoid the architectural difference of the same size doped region as caused by technique unstability, is missed so that data exist
Poor (error is still within tolerance interval).The doped region quantity for increasing same size in example 2, avoid due to
The architectural difference of same size doped region caused by technique unstability, it is ensured that the standard of the resistance of each test cell measured
True property, reduces data error, and measurement result is more accurate, only carries out in this embodiment to the part different from embodiment one
Detailed description, identical part, which does not remake, further to be repeated.
Optionally, the quantity for the doped region that each test cell includes can be same or different.
The quantity for the doped region that the test cell each in this embodiment includes is all the same.
In one embodiment, in the test structure for checking semiconductor device design rule at one, including multiple surveys
Try unit.The quantity for the doped region that each test cell includes is even number, the doping of the same test cell
Area connects the doped region to be formed and be connected two-by-two by first electrical connector, and the doped region connected two-by-two passes through described the
Two electrical connectors are connected in series；Wherein, second electrical connector at the head and the tail both ends of each test cell is separately connected a test point.
In one embodiment, in the test structure for checking semiconductor device design rule at one, including multiple surveys
Try unit.The quantity for the doped region that each test cell includes is odd number, the doping of the same test cell
Area is connected by first electrical connector to form the doped region connected two-by-two and a residue is unpaired and be electrically connected with first
The doped region of fitting connection, the doped region connected two-by-two and the residue are unpaired and connect with the first electrical connector
Doped region is connected in series by second electrical connector, wherein in each test cell, is connected with remaining unpaired doped region
The first electrical connector connect draws substrate by deriving structure and is connected to one second electrical connector, the doped region connected two-by-two,
Remaining unpaired doped region, the first electrical connector connecting with remaining unpaired doped region are connected by the second electrical connector
Connection.Wherein, second electrical connector at the head and the tail both ends of each test cell is separately connected a test point.
In one embodiment, in the test structure for checking semiconductor device design rule at one, including multiple surveys
Try unit.The quantity for the doped region that some test cells include is even number, the quantity for the doped region that some test cells include
For odd number.
Wherein, Fig. 4 shows the example of a test cell comprising multiple doped regions 102, such as the doped region packet
The first doped region, the second doped region, third doped region, the 4th doped region to N doped region are included, one of them first electrical connector
The first doped region, the second doped region are connected, wherein the second doped region and the third doped region are in the first electrical connector institute
Layer on be not connected with each other, but the second doped region and the third doped region are connected by the second electrical connector above it
It connects, then extends the test cell taking the above structure as basic repetitive unit, such as third doped region, the 4th doped region lead to
Cross the connection of another first electrical connector, wherein the 4th doped region and the 5th doped region second are electrically connected by another
Connection, repeats, in the manner described to form complete test cell.
Wherein, the length of the test cell is not limited to a certain numberical range, such as can only mix comprising two
Miscellaneous area, but for the accuracy of the data measured, multiple doped regions are set.
Wherein, the doped region, first electrical connector and second electrical connector are located in different layers, from
Under be up followed successively by the first electrical connector, doped region, the second electrical connector, therefore the test structure is bent in upper and lower different layers
Folding setting, to form the chain test cell of serpentine bend shape, but the curve form is not limited to shape shown in Fig. 4,
It can also be other curved shapes, will not enumerate herein.
Wherein, the top view of each test cell is as shown in Figure 1, the test cell can be to appoint in the horizontal plane
What shape, such as the test cell can also be able to be spiral-shaped, can also be random in the serpentine bend in Fig. 1
Bending, extend shape be not limited to a certain kind, all possible shape can be applied to the application.
Optionally, as shown in figure 4, second electrical connector includes:
Metal layer 104 is set to the top of two doped regions of electrical connection；
Contact hole 103, between the metal layer and the doped region.
Wherein, the forming method of the metal layer and the contact hole can select method commonly used in the art, herein not
It repeats again.
Optionally, the test structure further includes substrate and common end 105, and the test cell is formed in the substrate
On, the common end 105 is substrate exit.Second electrical connector at the head and the tail both ends of each test cell is separately connected a test
Point.The high-end voltage of one test point electric connection of power supply of each test cell, another test point electric connection of power supply of each test cell
Lower terminal voltage, the common end 105 of each test cell connects reference voltage.The reference voltage is less than or equal to the power supply
Lower terminal voltage.
Wherein, the doped region at the head and the tail both ends of the test cell passes through N+ active area respectively and realizes and the second different electricity
The electrical connection of connector, the common end be set in p-well, is realized by P+ active area and is electrically connected with reference voltage.
Specifically, the test cell is formed on the substrate, and the common end is substrate exit, each test
Second electrical connector at the head and the tail both ends of unit is separately connected a test point, and a test point of each test cell is electrically connected electricity
The high-end voltage in source, the lower terminal voltage of another test point electric connection of power supply of each test cell, each test cell
Common end connects reference voltage, and the reference voltage is less than or equal to the lower terminal voltage of the power supply.
The present invention provides a kind of test structures for checking semiconductor device design rule, and each test cell includes multiple mixes
Miscellaneous area, each test cell can form chain structure.Wherein, the size of the doped region of the different test cells is different.
Second electrical connector at the head and the tail both ends of each test cell is separately connected a test point, the test point electrical connection of each test cell
The high-end voltage of power supply, the lower terminal voltage of another test point electric connection of power supply of each test cell, the common end of each test cell
Connect reference voltage.
By the test point at the head and the tail both ends by each test cell, the resistance of each test cell is measured respectively.Wherein
There is resistance value to increased dramatically several times or reduce the situation of several times being the situation of resistance value mutation in the resistance of some test cell,
The resistance of the test cell is the resistance that resistance value mutates.
Judge whether the resistance of each test cell is less than the resistance of resistance value mutation, mutates less than resistance value
Resistance is consistent with by resistance expected from semiconductor device design rule.
In the test cell being consistent with by resistance expected from semiconductor device design rule, the minimum dimension of doped region is institute
The minimum dimension for stating semiconductor device design rule, can be to avoid same as caused by technique unstability by the structure
The architectural difference of size doped region reduces the data error of measurement resistance.
Embodiment three
The present invention also provides a kind of test methods based on the test structure of embodiment one or two, as shown in figure 4, institute
State method the following steps are included:
Step S1: the resistance of each test cell is measured respectively；
Step S2: judge each test cell resistance whether with by semiconductor device design rule expected from resistance phase
Symbol；
Step S3: the minimum ruler of the doped region for the test cell being consistent with by resistance expected from semiconductor device design rule
The very little minimum dimension for being determined as the semiconductor device design rule.
Optionally, the step S1 of the resistance for measuring each test cell respectively includes: single according to each test
The quantity for the doped region that member includes, it includes a doping that the resistance of each test cell is converted into each test cell only respectively
The resistance in area.
Optionally, the resistance for judging each test cell whether with by semiconductor device design rule expected from electricity
Hindering the step S2 being consistent includes: to judge whether the resistance of each test cell is less than the resistance of resistance value mutation, is less than resistance
The resistance that value mutates is consistent with by resistance expected from semiconductor device design rule.
Optionally, the resistance that the resistance value mutates increased dramatically for the resistance value or reduced resistance.
The quantity for testing the doped region of each test cell in structure is one, and the resistance of each test cell measured is i.e.
For the resistance for only including a doped region, the resistance of each test cell directly compares.
The quantity of the doped region of each test cell is greater than the number of one and each test cell doped region for including in test structure
Measure it is all the same, then do not need to be converted into each test cell only include a doped region resistance, directly relatively.
Wherein, there are multiple, these test lists with the test cell being consistent by resistance expected from semiconductor device design rule
Size is different each other for the doped region of member, select doped region minimum dimension be the application semiconductor device design rule minimum
Size.
Although describing example embodiment by reference to attached drawing here, it should be understood that above example embodiment are only exemplary
, and be not intended to limit the scope of the invention to this.Those of ordinary skill in the art can carry out various changes wherein
And modification, it is made without departing from the scope of the present invention and spiritual.All such changes and modifications are intended to be included in appended claims
Within required the scope of the present invention.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that implementation of the invention
Example can be practiced without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this specification.
Similarly, it should be understood that in order to simplify the present invention and help to understand one or more of the various inventive aspects, In
To in the description of exemplary embodiment of the present invention, each feature of the invention be grouped together into sometimes single embodiment, figure,
Or in descriptions thereof.However, the method for the invention should not be construed to reflect an intention that i.e. claimed
The present invention claims features more more than feature expressly recited in each claim.More precisely, such as corresponding power
As sharp claim reflects, inventive point is that the spy of all features less than some disclosed single embodiment can be used
Sign is to solve corresponding technical problem.Therefore, it then follows thus claims of specific embodiment are expressly incorporated in this specific
Embodiment, wherein each, the claims themselves are regarded as separate embodiments of the invention.
It will be understood to those skilled in the art that any combination pair can be used other than mutually exclusive between feature
All features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so disclosed any method
Or all process or units of equipment are combined.Unless expressly stated otherwise, this specification (is wanted including adjoint right
Ask, make a summary and attached drawing) disclosed in each feature can be replaced by providing identical, equivalent, or similar purpose alternative features.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments mean it is of the invention
Within the scope of and form different embodiments.For example, in detail in the claims, embodiment claimed it is one of any
Can in any combination mode come using.
The above description is merely a specific embodiment or to the explanation of specific embodiment, protection of the invention
Range is not limited thereto, and anyone skilled in the art in the technical scope disclosed by the present invention, can be easily
Expect change or replacement, should be covered by the protection scope of the present invention.Protection scope of the present invention should be with claim
Subject to protection scope.
Claims (13)
1. a kind of test structure for checking semiconductor device design rule, which is characterized in that the test structure has several surveys
Unit is tried, each test cell includes:
At least one doped region；
Several first electrical connectors, positioned at the lower section of the doped region；
Several second electrical connectors, positioned at the top of the doped region；
Each doped region is connected in series with first electrical connector and second electrical connector respectively；
Wherein, the size of the doped region of the different test cells is different, by measuring and judging each test cell
Whether resistance is consistent with by resistance expected from semiconductor device design rule, determines and presses expected from semiconductor device design rule
The minimum dimension of the doped region for the test cell that resistance is consistent is the minimum dimension of the semiconductor device design rule.
2. test structure according to claim 1, which is characterized in that the quantity of the doped region of the same test cell
Greater than one, the size of the doped region of the same test cell is identical.
3. test structure according to claim 2, which is characterized in that the quantity for the doped region that each test cell includes
It is all the same.
4. test structure according to claim 3, which is characterized in that the quantity for the doped region that each test cell includes
For even number, the doped region of the same test cell is connected to be formed by first electrical connector and be connected two-by-two
Doped region, the doped region connected two-by-two are connected in series by second electrical connector；
Alternatively, the quantity for the doped region that each test cell includes is odd number, the same test cell is mixed
Miscellaneous area connected by first electrical connector to be formed the doped region connected two-by-two and a residue it is unpaired and with first electricity
The doped region of connector connection, the doped region connected two-by-two and the residue are unpaired and connect with the first electrical connector
Doped region pass through second electrical connector be connected in series.
5. test structure according to claim 1, which is characterized in that the quantity for the doped region that each test cell includes
It is one, several first electrical connectors are connected to each other.
6. test structure according to claim 5, which is characterized in that the doped region of each test cell connects one jointly
First electrical connector, first electrical connector are connected to one second electrical connector, each test cell by deriving structure
Doped region be also respectively connected with the second different electrical connectors.
7. the test structure according to claim 4 or 6, which is characterized in that the test cell further includes substrate and public
End, the test cell are formed on the substrate, and the common end is substrate exit, the head and the tail two of each test cell
Second electrical connector at end is separately connected a test point, the high-end electricity of a test point electric connection of power supply of each test cell
Pressure, the lower terminal voltage of another test point electric connection of power supply of each test cell, the common end connection of each test cell
Reference voltage, the reference voltage are less than or equal to the lower terminal voltage of the power supply.
8. test structure according to claim 1 or 3, which is characterized in that the doped region of several test cells
Size gradient be reduced or increased.
9. test structure according to claim 1 or 3, which is characterized in that the doped region includes well region；In the doping
The surface in area is also formed with N+ active area；
First electrical connector includes deep trap, and the deep trap is identical as the conduction type of the doped region；
Second electrical connector includes:
Metal layer is set to the top of two doped regions of electrical connection；
Contact hole, between the metal layer and the doped region.
10. a kind of test method using test structure described in one of claim 1 to 9, which is characterized in that the test side
Method includes:
The resistance of each test cell is measured respectively；
Judge whether the resistance of each test cell is consistent with by resistance expected from semiconductor device design rule；
The minimum dimension of the doped region for the test cell being consistent with by resistance expected from semiconductor device design rule is determined as institute
State the minimum dimension of semiconductor device design rule.
11. test method according to claim 10, which is characterized in that the electricity for measuring each test cell respectively
The step of resistance includes: the quantity for the doped region for including according to each test cell, and the resistance of each test cell is distinguished
It is converted into each test cell only and includes the resistance of a doped region.
12. test method according to claim 10, which is characterized in that the resistance of each test cell of the judgement is
It is no with by resistance expected from semiconductor device design rule, to be consistent include: to judge whether the resistance of each test cell is less than resistance
It is worth the resistance to mutate, is less than the resistance that resistance value mutates and by resistance phase expected from semiconductor device design rule
Symbol.
13. test method according to claim 12, which is characterized in that the resistance that the resistance value mutates is the resistance
Value increased dramatically or reduced resistance.
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