CN110364447A - The monitoring of structures and monitoring method of the critical size of semiconductor technology - Google Patents
The monitoring of structures and monitoring method of the critical size of semiconductor technology Download PDFInfo
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- CN110364447A CN110364447A CN201810317822.0A CN201810317822A CN110364447A CN 110364447 A CN110364447 A CN 110364447A CN 201810317822 A CN201810317822 A CN 201810317822A CN 110364447 A CN110364447 A CN 110364447A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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Abstract
The present invention relates to a kind of monitoring of structures of the critical size of semiconductor technology and monitoring methods.The test structure includes: the first test block, has the first width, the first length and the first electrical parameter；Second test block, including at least one test-strips, the test-strips have the second width and the second length, second test block has the second electrical parameter, wherein, second width is much smaller than first width, first length, second length, the design size of second width is the critical size of the semiconductor technology, according to the first electrical parameter of the first test block, first width, second electrical parameter of the first length and second test block, second length monitors the actual size of second width, by the way that the actual size of second width is judged whether the critical size of the semiconductor technology changes compared with the design size of second width.It can be monitored by the CD of the structures and methods overwhelming majority key level.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates in a kind of semiconductor technology semiconductor technology pass
The monitoring of structures and monitoring method of key size.
Background technique
Ic manufacturing technology is a complicated technique, and technology innovation is quickly.Characterize ic manufacturing technology
One key parameter is minimum feature size, i.e. critical size (critical dimension, CD), the size of critical size from
Till now 0.13 micron of initial 125 microns, even more small, the reduction just because of critical size just makes each core
On piece is arranged million devices and is possibly realized.
Product is stressed light and short at present, and IC volume is smaller and smaller, function is increasingly stronger, foot number is more and more, in order to drop
Area shared by low chip package and improvement IC efficiency, flip (Flip Chip) mode, which encapsulates, at this stage is generally applied to draw
Figure chip, chipset, memory and CPU etc..Above-mentioned high-order packaged type unit price is high, if chip survey can be carried out before packaging
Examination finds in the presence of defective products wafer, that is, is marked, gives up the defective products of these labels before back segment encapsulation procedure
It abandons, unnecessary packaging cost can be saved.
Include for the method for wafer test in the prior art it is a variety of, the method for most common of them is wafer acceptance test
(wafer acceptance test, WAT), the WAT method are to carry out test for special resolution chart (test key) to lead to
Electrical parameter is crossed to judge whether each step process is normal and stablizes.
In order to improve the reliability and performance of device, WAT is tested in device fabrication process, such as in device critical step
In all can online (Inline) measure the critical size (CD) of the pattern or element that are formed, but each layer can only generally be tested
Subelement or region, such as 1-2 piece film layer, actual process step are complicated, and being also likely to be present between piece and piece
Bigger difference especially will have a direct impact on device such as active area/grid layer (gate, GT) etc. to some very crucial levels
The characteristic of part, a current suitable resolution chart (test key) not yet carry out direct-on-line monitoring (monitor Inline)
The fluctuation of critical size can be locked with the resolution chart (test key) of monitoring critical size in conjunction with the characteristic of device quickly
Whether online critical size generates deviation.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of monitoring of structures of the critical size of semiconductor technology, the monitoring of structures includes:
The monitoring of structures includes:
First test block has the first width, the first length and the first electrical parameter；
Second test block, including at least one test-strips, the test-strips have the second width and the second length, and described the
Two test blocks have the second electrical parameter, wherein second width is much smaller than first width, the first length, the second length
Degree, the design size of second width is the critical size of the semiconductor technology, according to the first of first test block
Electrical parameter, the first width, the first length and the second electrical parameter of second test block, the second length are described to monitor
The actual size of second width, by by the actual size of second width compared with the design size of second width come
Judge whether the critical size of the semiconductor technology changes.
Optionally, the thickness of first test block is identical as the thickness of second test block.
Optionally, second test block includes several test-strips disposed in parallel each other, several surveys
Strip is spaced apart from each other setting.
Optionally, first test block includes the resistor stripe in rectangular parallelepiped structure, and second test block includes in length
The resistor stripe of cube structure；
The material of first test block and second test block includes doped polysilicon.
Optionally, first test block includes:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region with it is described
The second pole plate of the substrate below first grid structure together as first test block；
Wherein, first pole plate and the second pole plate lap have first width and first length
Degree；
First grid dielectric layer, between the substrate and the first grid structure, as first test block
Dielectric medium, first capacitor device is collectively formed with first pole plate and second pole plate.
Optionally, second test block includes:
Second grid structure is located in the substrate, using the first pole plate as second test block, wherein described
Second grid structure includes each of several test-strips for being spaced setting each other and several test-strips of connection
The connector at end；
Second doped region, in the substrate of second grid structure two sides, second doped region with it is described
The second pole plate of the substrate below second grid structure together as second test block, wherein the test-strips exist
There is second width, first pole plate and described on the test-strips extending direction on the connector extending direction
Second pole plate lap has second length；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, the second capacitor is collectively formed with first pole plate and second pole plate with second test block.
Optionally, second test block includes:
Second grid structure is located in the substrate, using the first pole plate as second test block；
Second doped region, in the substrate of second grid structure two sides, second doped region with it is described
The second pole plate of the substrate below second grid structure together as second test block, wherein second doping
Area includes the connector of every one end of several test-strips for being spaced setting each other and the connection test-strips, the test
Item has second width, first pole plate and the second pole plate lap tool on the test-strips extending direction
There is second length；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, the second capacitor is collectively formed with first pole plate of second test block and the second pole plate.
Optionally, if the second grid structure includes several test-strips and connection for being spaced setting each other
Do the connector of every one end of the test-strips.
Optionally, second doped region includes several test-strips for being spaced setting each other and the connection test
The connector of every one end of item.
Optionally, first test block includes third doped region, and the third doped region is located at first test block
The first capacitor device side；
Second test block includes the 4th doped region, and the 4th doped region is located at the side of second capacitor.
Optionally, in first test block, first doped region and the third doped region are grounded, described
First grid structure connects high potential；
In second test block, second doped region and the 4th doped region are grounded, the second gate
Pole structure connects high potential.
The present invention provides a kind of monitoring method of the monitoring of structures of critical size based on semiconductor technology, including it is following
Step:
Step S1, tests the first electrical parameter of the first test block, and first test block has the first width, the first length
Degree；
Step S2 tests the second electrical parameter of the second test block, and second test block includes at least one test-strips,
The test-strips have the second width and the second length, wherein second width is much smaller than first width, the first length
Degree, the second length, the design size of second width are the critical size of the semiconductor technology；
Step S3, according to the first electrical parameter of first test block, the first width, the first length and described second
Second electrical parameter of test block, the second length monitor the actual size of second width；
Step S4, by judging the actual size of second width compared with the design size of second width
Whether the critical size of the semiconductor technology changes.
Optionally, in the step S1, the first electrical parameter of first test block is square resistance R1, described first
Test block is polysilicon resistance item, and the first length of first test block is L1, and the first width is W1, first test block
Unit square resistance are as follows: R1/ (L1/W1)；
In the step S2, the second electrical parameter of second test block is square resistance R2, second test block
For polysilicon resistance item, the second length of the test-strips is L2, and the actual size of second width is W2, and described second surveys
The unit square resistance of test specimen is R2/ (L2/W2)；
In the step S3, according to the unit side of the unit square resistance of first test block and second test block
Block resistance is identical, calculates actual size W2, W2=R1 × W1 × L2/ (L1 × R2) of second width；
In the step S4, the actual size W2 of second width is come compared with the design size of second width
Judge whether the critical size of the semiconductor technology changes.
Optionally, in the step S1, the first electrical parameter of first test block is capacitor C1, first test
Part is first capacitor device, and the first capacitor device includes:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region with it is described
The second pole plate of the substrate below first grid structure together as first test block, wherein first pole plate
There is first width and first length with the second pole plate lap；
First grid dielectric layer, between the substrate and the first grid structure, as first test block
Dielectric medium, first capacitor device is collectively formed with first pole plate and second pole plate；The of first test block
One doped region and first grid structure lap have the first width W1 and the first length L1, first test block
Capacitor C1=L1 × W1 × K of first capacitor device, wherein K is constant；
In the step S2, the second electrical parameter of second test block is capacitor C2, and second test block is the
Two capacitors, second capacitor include:
Second grid structure is located in the substrate, using the first pole plate as second test block, wherein described
Second grid structure includes at least one described test-strips；
Second doped region, in the substrate of second grid structure two sides, second doped region with it is described
The second pole plate of the substrate below second grid structure together as second test block, wherein the test-strips exist
There is second width, first pole plate on the test-strips extending direction on the second grid structure extending direction
There is second length with the second pole plate lap；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, the second capacitor, institute are collectively formed with first pole plate and second pole plate with second test block
Second width for stating the test-strips of the second test block is W2, the first pole plate and the second pole plate of second test block
The size of lap is the second length L2, capacitor C2=L2 × W2 × n2 × K of the second capacitor in second test block,
Wherein, K is constant, and n2 is the number of the test-strips；
Identical according to the numerical value of K in the step S3, the actual size for calculating second width is W2=(C2 × L1
×W1)/(C1×L2×n2)；
In the step S4, the actual size W2 of second width is come compared with the design size of second width
Judge whether the critical size of the semiconductor technology changes.
Optionally, in the step S1, the first electrical parameter of first test block is capacitor C1, first test
Part is first capacitor device, and the first capacitor device includes:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region with it is described
The second pole plate of the substrate below first grid structure together as first test block, wherein first pole plate
There is first width and first length with the second pole plate lap；
First grid dielectric layer, between the substrate and the first grid structure, as first test block
Dielectric medium, first capacitor device is collectively formed with first pole plate and second pole plate；The of first test block
One doped region and first grid structure lap have the first width W1 and the first length L1, first test block
Capacitor C1=L1 × W1 × K of first capacitor device, wherein K is constant；
In the step S2, the second electrical parameter of second test block is capacitor C2, and second test block is the
Two capacitors, second capacitor include:
Second grid structure is located above the substrate, using the first pole plate as second test block；
Second doped region, in the substrate below the second grid structure, second doped region with it is described
The second pole plate of the substrate below second grid structure together as second test block, wherein second doping
Area includes at least one described test-strips, and the test-strips have second width, the institute on the test-strips extending direction
Stating the first pole plate and the second pole plate lap has second length；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, to be collectively formed the second capacitor with first pole plate of second test block and the second pole plate, described
Second width of the test-strips of two test blocks is W2, the first pole plate of second test block and the overlapping of the second pole plate
Partial size is the second length L2, capacitor C2=L2 × W2 × n2 × K of the second capacitor in second test block,
In, K is constant, and n2 is the number of the test-strips；
Identical according to the numerical value of K in the step S3, the actual size for calculating second width is W2=(C2 × L1
×W1)/(C1×L2×n2)；
In the step S4, the actual size W2 of second width is come compared with the design size of second width
Judge whether the critical size of the semiconductor technology changes.
Optionally, in the step S1, by first doped region and third doped region in first test block
It is grounded, the first grid structure is connect into high potential, to measure the capacitor of the first capacitor device, first test block
Third doped region is located at the side of the first capacitor device of first test block；
In the step S2, by second test block second pole plate and the 4th doped region be grounded, will
First pole plate connects high potential, to measure the capacitor of second capacitor, the 4th doping position of second test block
In the side of second capacitor.
The present invention provides a kind of monitoring of structures of the critical size of semiconductor technology and methods, in the monitoring of structures
In, smaller, larger-size first test block is influenced as reference, simultaneous selection by technique by being arranged in monitoring of structures
Lesser second test block of size becomes to monitor technique change on line, such as by CD in the change monitoring technique of resistance or capacitor
Change, can all be monitored by the CD of key levels most on the structures and methods line, further improve monitoring
The Efficiency and accuracy of CD variation, and further improve the performance and yield of device.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 is the process flow chart of monitoring method of the present invention；
Fig. 2A -2C is the structural schematic diagram of monitoring of structures in one embodiment of the invention；
Fig. 3 is the structural schematic diagram of test resistance resistance in one embodiment of the invention；
Fig. 4 A-4C is the structural schematic diagram of monitoring of structures in another two embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
It is used to monitor (monitor) technologic crucial ruler without suitable monitoring of structures (test key) in technique at present
Very little (CD) fluctuation, some technologic exceptions cannot be found in time, bring difficulty to problem analysis, it is therefore desirable to design one
Kind of monitoring of structures can be used to monitor the CD (such as active area TO, polysilicon Poly and metal layer Metal etc.) of committed step, can be with
Discovery process abnormality, the efficiency analyzed problems and solved them will greatly increase in time.
Based on above-mentioned discussion, the present invention provides a kind of monitoring of structures of the critical size of semiconductor technology, the monitoring
Structure includes:
First test block has the first width, the first length and the first electrical parameter；
Second test block, including at least one test-strips, the test-strips have the second width and the second length, and described the
Two test blocks have the second electrical parameter, wherein second width is much smaller than first width, the first length, the second length
Degree, the design size of second width is the critical size of the semiconductor technology, according to the first of first test block
Electrical parameter, the first width, the first length and the second electrical parameter of second test block, the second length are described to monitor
The actual size of second width, by by the actual size of second width compared with the design size of second width come
Judge whether the critical size of the semiconductor technology changes.
In the monitoring of structures, wherein the size of first test block is larger, by work in device fabrication process
The influence of skill step is smaller, therefore the electrical parameter of first test block will not be influenced by critical size variation, can
Using during the test as reference, and the width of the second test block is smaller, is affected by processing step, once become
To change, electrical parameter also will receive very big influence, therefore first test block and second test block are combined,
Technique change on line is monitored by the variation of electrical parameter, such as is become by CD in the change monitoring technique of resistance or capacitor
Change, can all be monitored by the CD of key levels most on line in this way, further improves monitoring CD and become
The Efficiency and accuracy of change, and further improve the performance and yield of device.
The present invention also provides a kind of monitoring methods, include the following steps, as shown in Figure 1:
Step S1, tests the first electrical parameter of the first test block, and first test block has the first width, the first length
Degree；
Step S2 tests the second electrical parameter of the second test block, and second test block includes at least one test-strips,
The test-strips have the second width and the second length, wherein second width is much smaller than first width, the first length
Degree, the second length, the design size of second width are the critical size of the semiconductor technology；
Step S3, according to the first electrical parameter of first test block, the first width, the first length and described second
Second electrical parameter of test block, the second length monitor the actual size of second width；
Step S4, by judging the actual size of second width compared with the design size of second width
Whether the critical size of the semiconductor technology changes.
The electrical parameter may include resistance, capacitor etc., in the following embodiments respectively just according to resistance and capacitor
Change monitoring technique on CD variation monitoring of structures and monitoring method be described in detail.
Embodiment one
In order to solve the problems in the existing technology the present invention, provides a kind of prison of the critical size of semiconductor technology
Geodesic structure is with reference to the accompanying drawing further described the monitoring of structures.Wherein, Fig. 2A -2C is described in the embodiment
The structural schematic diagram of monitoring of structures.
Specifically, critical size is monitored by the variation of resistance in this embodiment, wherein the size of resistance and
Material is spread (Diff) in relation in relation to related with the size at interface, there is polysilicon (Poly) resistance in the semiconductors with length
Resistance and metal (Metal) resistance etc., are illustrated by taking the forming process of polysilicon (Poly) resistance as an example in this embodiment:
Substrate is provided first, deposits one layer of polysilicon on the substrate, then by photoetching and corrosion the more of strip
Crystal silicon resistance pattern, which etches, to be come, and then forms required resistance by doping and annealing again, the size of polysilicon resistance and
The thickness of polysilicon, length and width are related, if in the case that the thickness of polysilicon has determined, polysilicon resistance and length
It is related to width, if it is known that the resistance value and length of polysilicon, so that it may calculate corresponding width, that is to say, that pass through test
The resistance of polysilicon and some known dimensions can calculate the width of polysilicon, by this width and domain
(Layout) width relatively, sees whether exception occur.
Wherein, the deposition of the polysilicon and corrosion can select various techniques commonly used in the art, and details are not described herein.
As shown in Figure 2 A, wherein the first test block is first resistor item 101, wherein what the first resistor item 101 had
First length is L1, and the first width is W1.
Optionally, one is designed than wider first resistor item 101 (such as 10um or more), the first resistor item of wide item
101 critical size be not susceptible to technique influence, have more referential, using in monitoring of structures as reference, when described first
First length of resistor stripe 101 is L1, and when the first width is W1, total square resistance is R1, then unit square resistance
Are as follows: R1/ (L1/W1).
As shown in Figure 2 B, the second test block is second resistance item 102, wherein the length of the second resistance item is L2, institute
The width for stating second resistance item 102 is W2.
Optionally, the length of the second resistance item is identical as the length of the first resistor item 101, preferably to institute
The variation for stating the second width is compared, and the W2 is much smaller than the first width W1 of the first resistor item 101, just because of described
The critical size very little of second width W2, it is easy to be influenced by technique change, and then influence its resistance value.Such as in this hair
Second width W2 described in a bright embodiment is set by minimum design rule, when the second length of second test block is
L2, when the second width is W2, the total square resistance of the second resistance item is R2, then unit square resistance are as follows: R2/ (L2/
W2).Single (ISO) the second test block is set in this embodiment.
Such as in one embodiment of the invention, in first test block first resistor item (wide item) 101 first
Width is 30um or 10um or 5um, and the second width of the second resistance item (fillet) is 0.13um, the first resistor item
101 the first length is 100um, and the second length of the second resistance item is 100um, first length and second length
Degree can also be different, wherein second resistance width is smaller, is affected by technological fluctuation more apparent, wide by monitoring second
The variation of degree would know that the fluctuation of technique, other Length x Widths are larger, be influenced by technological fluctuation smaller, and design value can be directly as
Actual value.
As alternate embodiment, single (ISO) and/or more (Dense) can also be arranged in the test-strips simultaneously
Two resistor stripes.As shown in Figure 2 C, several second resistance items 102 being spaced apart from each other are set in second test block, wherein institute
State that several second resistance items are arranged in parallel and shape is identical, the second of either single setting or more settings
Resistor stripe, test philosophy are identical.
Optionally, wherein first test block and second test block can be formed simultaneously in same technique, by
The thickness of this described first test block and second test block is essentially identical, the differences such as thickness of film be it is smaller, can be with
Influence caused by difference in thickness between the first test block and the second test block is eliminated, it is ensured that unit square resistance is also identical.
Wherein, the shape of first test block and second test block is rectangular parallelepiped structure in the present invention,
It is projected as rectangle in substrate, as seen in figs. 2a-2c, it should be understood that first test block and described second is surveyed
The shape of test specimen is not limited to the cuboid, can also be cylindricality, taper etc. other shapes.
In testing, the monitoring method includes:
Step S1, tests the first electrical parameter of the first test block, and the first electrical parameter of first test block is side
Block resistance R1, the first length of first test block are L1, and the first width is W1, the unit square electricity of first test block
Resistance are as follows: R1/ (L1/W1)；
Step S2, tests the second electrical parameter of the second test block, and the second electrical parameter of second test block is side
Block resistance R2, the second length of the test-strips are L2, and the actual size of second width is W2, second test block
Unit square resistance is R2/ (L2/W2)；
Step S3, according to the unit square resistance of the unit square resistance of first test block and second test block
It is identical, calculate actual size W2, W2=R1 × W1 × L2/ (L1 × R2) of second width；
Step S4, by the actual size W2 of second width to judge compared with the design size of second width
Whether the critical size for stating semiconductor technology changes.
Wherein, the monitoring method of the square resistance can use four-end method, as shown in figure 3, with second resistance item 102
For resistance measurement, wherein the four-end method refers to tetra- end A-D, and wherein L length is the electricity to be monitored in second resistance item 102
Resistance body, leading to fixed electric current at the both ends A, B when test is I, poor in the other 2 ends, that is, end C, D test L or more corresponding voltage, wherein
There is no electric current at the end C, D, so four-end method can be the very accurate of the partial test of the real resistor body of resistor stripe, if with two
Hold-carrying inevitably includes the lead resistance at (or including) resistor body both ends, the dead resistance etc. of the probe of test equipment, and four
Hold-carrying only includes resistor body partial ohmic, and other resistance (there are also contact) outside lead and both ends will not have test result any
It influences, therefore measurement result is more accurate.
Specifically, because unit square resistance is identical under same environment, according to the list of the first test block and the second test block
Position square resistance is identical, and equation below is set up: R1/ (L1/W1)=R2/ (L2/W2) can calculate W2=R1W1L2/
(L1R2), theoretically W2 is identical with the CD of layout design, but due to technologic difference, and W2 is likely lower than or is higher than version
The CD of G- Design can analyze possible reason according to the variation of W2, according further to single (ISO) He Duogen in technique
(Dense) W2 value, it can be deduced that technique influences the CD of single (ISO) He Duogen (Dense).
The present invention provides a kind of monitoring of structures of the critical size of semiconductor technology and methods, in the monitoring of structures
In, smaller larger-size first test block is influenced as reference by technique by being arranged in monitoring of structures, is selected simultaneously
Lesser second test block of size is selected to monitor technique change on line, such as CD changes in the change monitoring technique for passing through resistance,
It can all be monitored by the CD of key levels most on the line in this way, further improve CD variation
Efficiency and accuracy, and further improve the performance and yield of device.
In order to solve the problems in the existing technology the present invention, provides a kind of prison of the critical size of semiconductor technology
Geodesic structure, the example in embodiment one are change by CD in the change monitoring technique of resistance, following embodiments two and implementation
Example is third is that the variation by capacitor is monitored the critical size.
In integrated circuits, semiconductor material can be used, as polysilicon (Poly) and substrate constitute MOS capacitor, capacitor
The thickness for depending mainly on the size of polysilicon (Poly) area and gate dielectric (GOX), it is assumed that gate dielectric (GOX)
Thickness is certain, and the size of capacitor is determined by the area of polysilicon (Poly), in the situation known to polysilicon (Poly) length
Capacitor is only determined by the width of polysilicon (Poly), is said from another angle, if having been known for the big of mos capacitance
It is small, the width of polysilicon (Poly) can also be calculated, can be monitored in this embodiment with the capacitor of MOS online active area or
The variation of person's polysilicon (Poly) CD, the fluctuation of online CD is monitored with the monitoring of structures of WAT.
It is more accurate in order to test, one group of monitoring of structures is designed to be tested (large area and finger-like (finger) or strip
Two kinds of structures), if to test the size of polysilicon CD, polysilicon needs to design into strips, and at this moment doped region (active area) is
Large area pattern, if to test the size of doped region (active area) CD, doped region (active area) needs to design into strips, at this moment
Polysilicon is large area pattern.
Embodiment two
4A-4B is illustrated the monitoring of structures the present invention is based on capacitor with reference to the accompanying drawing.
Firstly, as shown in Figure 4 A, the first test block includes:
Substrate；
First grid structure 204 is located in the substrate, using the first pole plate as first test block；
First doped region 203, in the substrate of first grid structure two sides, first doped region and institute
The substrate below first grid structure is stated together as the second pole plate of first test block, wherein first pole
Plate and the second pole plate lap have first width and first length；
First grid dielectric layer, between the substrate and the first grid structure, as first test block
Dielectric medium, first capacitor device is collectively formed with first pole plate and second pole plate.
Wherein, first doped region has the first width W1, and the first grid structure has the first length L1,
I.e. described first pole plate and the second pole plate lap have the first width W1 and the first length L1.Described first is wide
Degree W1 and the first length L1 is influenced smaller by technological fluctuation, and design value can be directly as actual value.
Optionally, substrate can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator (SOI), insulation
Silicon (SSOI) is laminated on body, SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulation are laminated on insulator
Germanium (GeOI) etc. on body.
As shown in Figure 4 A, optionally, the monitoring of structures further include:
Well region is located in the substrate, and first doped region and the first grid structure are respectively positioned in the well region.
Substrate between first doped region, below the first grid structure is a part of the well region, described
The doping type of first doped region is different from the well region doping type.
Wherein, first doped region is active area in the present invention, is used to form gate structure in monitoring of structures
Source and drain.
First test block includes third doped region 202, and the third doped region of first test block is located at described the
The side of first doped region of one test block, such as positioned at the side of the entire first capacitor device.First doping
Area and the third doped region 202 are spaced apart from each other setting, such as are isolated by fleet plough groove isolation structure.
In first test block, the first grid structure is as the first pole plate, the first doped region combination institute
The substrate below first grid structure is stated as the second pole plate, first between first pole plate and second pole plate
First capacitor device is consequently formed as dielectric medium in gate dielectric, in the first capacitor device, first pole plate and institute
It states the second pole plate and is all made of the biggish plane tabular structure of area, therefore critical size is not susceptible to technique influence, capacitance
With more referential, using in monitoring of structures as reference.
In this embodiment, as shown in Figure 4 B, second test block includes:
Second grid structure 204 ' is located in the substrate, using the first pole plate as second test block, wherein
The second grid structure includes at least one described test-strips, for example, the second grid structure include a test-strips or
The second grid structure includes several test-strips for being spaced setting each other and several test-strips of connection
The connector of every one end；
Second doped region, in the substrate of second grid structure two sides, second doped region with it is described
The substrate below second grid structure together as second test block the second pole plate, wherein the test-strips are in institute
Stating has second width on connector extending direction, first pole plate and described the on the test-strips extending direction
Two pole plate laps have second length；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, the second capacitor is collectively formed with first pole plate and second pole plate with second test block.
As shown in Figure 4 B, the second grid structure includes several test-strips for being spaced apart from each other setting and the connection survey
The connector of every one end of strip, the test-strips have the second width W2 on the connector extending direction, in institute
Stating first pole plate and the size of second pole plate overlapping on test-strips extending direction is the second length L2, wherein
The extending direction of the test-strips is vertical with the extending direction of second doped region；
Second grid dielectric layer, between the substrate and the second grid structure, to be tested as described second
The dielectric medium of part, to form the second capacitor with first pole plate and second pole plate.
Optionally, several test-strips for being spaced apart from each other setting it is arranged in parallel and between gap it is equal.
Wherein, second doped region 203 ' is located at the two sides of the second grid structure, therefore works as the second gate knot
Substrate when structure is multiple test-strips being spaced each other, below second doped region and the second grid structure
It is spaced apart from each other and is arranged alternately, and then form the second pole plate of second test block.Wherein, second doped region is as active
Area is used to form the source and drain of gate structure in monitoring of structures.
Second test block includes the 4th doped region 202 ', and the 4th doped region of second test block is located at described the
The side of second doped region of two test blocks, such as the side of second doped region positioned at outermost end, and it is described
Second doped region and the 4th doped region are spaced apart from each other setting, such as mutually isolated by fleet plough groove isolation structure.
Optionally, second doped region and the 4th doped region are respectively positioned in an other well region, and described second mixes
The doping type in miscellaneous area is different from the well region doping type, the doping type of the 4th doped region and the well region doping type phase
Together.
In the specific embodiment of the present invention, it is formed with p-well in the substrate, is formed in the p-well
The first grid dielectric layer, the first grid structure, first doped region and the third doped region, wherein described
First doped region is N+ doping, and then the source-drain area as the first grid structure, the third doped region are P+ doping.
Optionally, the second grid dielectric layer, the second grid structure, institute are formed in an other p-well
The second doped region and the 4th doped region are stated, wherein second doped region is N+ doping, and then as the second gate
The source-drain area of pole structure, the 4th doped region are P+ doping.
In second test block, the second grid structure is as the first pole plate, second doped region and described
The substrate below second grid structure combines as the second pole plate, between the substrate and the second grid structure
Second grid dielectric layer as dielectric medium, the second capacitor is consequently formed, in second capacitor, the test-strips
Width it is smaller, be affected by technological fluctuation more apparent, the variation by monitoring the second width would know that the fluctuation of technique.
In testing, the monitoring method includes:
Step S1, tests the first electrical parameter of the first test block, and the first electrical parameter of first test block is the
The capacitor C1 of one capacitor, the first doped region of first test block and the first grid structure lap have described
First width W1 and the first length L1, capacitor C1=L1 × W1 × K of the first capacitor device of first test block, wherein K is
Constant；
Step S2, tests the second electrical parameter of the second test block, and the second electrical parameter of second test block is the
The capacitor C2 of two capacitors, second width of the test-strips of second test block are W2, second test block
First pole plate and the size of the second pole plate lap be the second length L2, the second electricity in second test block
Capacitor C2=L2 × W2 × n2 × K of container, wherein K is constant, and n2 is the number of the test-strips；
Step S3, it is identical according to the numerical value of K, calculate second width actual size be W2=(C2 × L1 × W1)/
(C1×L2×n2)；
Step S4, by the actual size W2 of second width to judge compared with the design size of second width
Whether the critical size for stating semiconductor technology changes.
Specifically, which is for testing the CD of gate structure (W2 of Fig. 4 B), according to Fig. 4 A and 4B institute
The structure shown tests mos capacitance with three hold-carryings, such as in first test block, third doped region 202 and the first doped region
Ground connection, the first grid structure connects high potential, at this point, transoid (N-type) and both sides occurs in the channel below first grid structure
The first doped region together as the bottom crown of metal-oxide-semiconductor, first grid structure is as top crown, and first grid dielectric layer is as electricity
Hold medium and form MOS capacitor, the capacitor for measuring first capacitor device is C1=A1K, and same method measures the second test block
In the second capacitor capacitor C2=A2K, wherein K be and gate dielectric layer thickness, dielectric constant, polysilicon doping, voltage
Etc. relevant constant, if the number of the test-strips described in the second test block is n2, the length of gate structure is and described the
The length of the part of two doping area overlappings is L2, and the width of gate structure is W2, then C1=L1W1K, C2=L2W2
N2K, available W2=(C2L1W1)/(C1L2n2) identical according to K, wherein C1 and C2 is the electricity of WAT test
Property capacitor, other numerical value are all and relevant length, width and test-strips number are arranged, therefore can accurately calculate the W2
Numerical value, and by the numerical value of the W2 and domain (Layout) it is wide compared with, see exception whether occur, thus monitor the grid
The width of test-strips in the structure of pole.
Embodiment three
4A and 4C is illustrated the monitoring of structures the present invention is based on capacitor with reference to the accompanying drawing.
In this embodiment, first test block is identical as first test block in embodiment two, such as Fig. 4 A institute
Show, details are not described herein, and the second test block is as shown in Figure 4 C in this embodiment, comprising:
Second grid structure 204 ' is located in the substrate, using the first pole plate as second test block；
Second doped region 203 ', in the substrate below the second grid structure, second doped region with
The second pole plate of the substrate below the second grid structure together as second test block, wherein described second
Doped region includes at least one described test-strips, such as second doped region only includes the test-strips or described second
Doped region includes the connector of every one end of several test-strips for being spaced setting each other and the connection test-strips；It is described
Test-strips have second width, first pole plate and second pole plate overlapping portion on the test-strips extending direction
Dividing has second length；
Second grid dielectric layer, between the substrate and the second grid structure, as second test block
Dielectric medium, the second capacitor is collectively formed with first pole plate of second test block and the second pole plate.
Optionally, several test-strips for being spaced apart from each other setting it is arranged in parallel and between gap it is equal.
Wherein, when second doped region is multiple test-strips being spaced each other, second doped region and described
Substrate, which is spaced apart from each other, to be arranged alternately, and then is formed together the second pole plate of second test block.
Second test block includes the 4th doped region 202 ', and the 4th doped region area of second test block is located at described
The side of second doped region of second test block, such as the side of second doped region positioned at outermost end, and institute
It states the second doped region and the 4th doped region is spaced apart from each other setting, such as is mutually isolated by fleet plough groove isolation structure.
Optionally, the monitoring of structures further include:
Well region is located in the substrate, and second doped region and the 4th doped region are respectively positioned in the well region, described
Second doped region is different from the well region doping type, and the doping type of the 4th doped region is identical as the well region doping type.
In the specific embodiment of the present invention, in the specific embodiment of the present invention, in the substrate
Middle formation p-well is formed with the first grid dielectric layer, the first grid structure, first doped region in the p-well
And the third doped region, wherein first doped region is N+ doping, and then the source and drain as the first grid structure
Area, the third doped region are P+ doping.
Optionally, the second grid dielectric layer, the second grid structure, institute are formed in an other p-well
The second doped region and the 4th doped region are stated, wherein second doped region is N+ doping, and then as the second gate
The source-drain area of pole structure, the 4th doped region are P+ doping.
In second test block, the second grid structure is as the first pole plate, second doped region and described
Substrate is combined as the second pole plate, and the second grid dielectric layer between the substrate and the second grid structure is as dielectric
The second capacitor is consequently formed in matter, and in second capacitor, the width of the test-strips of second doped region is smaller,
It is affected by technological fluctuation more apparent, the variation by monitoring the second width would know that the fluctuation of technique.
In testing, specifically, which is for monitoring the CD of the second doped region (W3 of Fig. 4 C), according to described
Structure shown in Fig. 4 A and 4C tests mos capacitance with three hold-carryings, such as in first test block, the third doped region
202 and first doped region ground connection, the first grid structure connects high potential, at this point, the channel below first grid structure occurs
First doped region on transoid (N-type) and both sides is together as the bottom crown of metal-oxide-semiconductor, and first grid structure is as top crown, and first
Gate dielectric forms MOS capacitor as capacitor dielectric, and the capacitor for measuring first capacitor device is C1=A1K, same side
Method measures the capacitor C2=A2K of the second capacitor in the second test block, wherein K be and gate dielectric layer thickness, dielectric constant,
The relevant constant such as polysilicon doping, voltage, if the number of the test-strips described in the second test block is n2, gate structure
Length L3, the width of test-strips is W3, available W3=(C3L1W1)/(C1 identical according to K in the doped region
L3n3), wherein C1 and C3 be WAT test electrical capacitor, other numerical value are all and relevant length, width and test-strips are arranged
Number, therefore the numerical value of the W3 can be accurately calculated, and by the numerical value of the W3 compared with the width of domain (Layout),
It sees exception whether occur, thus monitors the width of test-strips in the second doped region.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of monitoring of structures of the critical size of semiconductor technology, which is characterized in that the monitoring of structures includes:
First test block has the first width, the first length and the first electrical parameter；
Second test block, including at least one test-strips, the test-strips have the second width and the second length, and described second surveys
Test specimen has the second electrical parameter, wherein second width is much smaller than first width, the first length, the second length, institute
The design size for stating the second width is the critical size of the semiconductor technology, is joined according to the first electricity of first test block
Number, the second electrical parameter of the first width, the first length and second test block, the second length are wide to monitor described second
The actual size of degree, by by the actual size of second width compared with the design size of second width to judge
Whether the critical size for stating semiconductor technology changes.
2. monitoring of structures according to claim 1, which is characterized in that the thickness of first test block and described second is surveyed
The thickness of test specimen is identical.
3. monitoring of structures according to claim 1, which is characterized in that second test block includes setting in parallel each other
Several test-strips set, several test-strips are spaced apart from each other setting.
4. monitoring of structures according to claim 1, which is characterized in that first test block includes in rectangular parallelepiped structure
Resistor stripe, second test block include the resistor stripe in rectangular parallelepiped structure；
The material of first test block and second test block includes doped polysilicon.
5. monitoring of structures according to claim 1, which is characterized in that first test block includes:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region and described first
The second pole plate of the substrate below gate structure together as first test block, wherein first pole plate and institute
The second pole plate lap is stated with first width and first length；
First grid dielectric layer, Jie between the substrate and the first grid structure, as first test block
Electric matter, first capacitor device is collectively formed with first pole plate and second pole plate.
6. monitoring of structures according to claim 5, which is characterized in that second test block includes:
Second grid structure is located in the substrate, using the first pole plate as second test block, wherein described second
Gate structure includes at least one described test-strips；
Second doped region, in the substrate of second grid structure two sides, second doped region and described second
The second pole plate of the substrate below gate structure together as second test block, wherein the test-strips are described
There is second width, first pole plate and institute on the test-strips extending direction on second grid structure extending direction
The second pole plate lap is stated with second length；
Second grid dielectric layer, Jie between the substrate and the second grid structure, as second test block
The second capacitor is collectively formed with first pole plate and second pole plate with second test block in electric matter.
7. monitoring of structures according to claim 5, which is characterized in that second test block includes:
Second grid structure is located above the substrate, using the first pole plate as second test block；
Second doped region, in the substrate below the second grid structure, second doped region and described second
The second pole plate of the substrate below gate structure together as second test block, wherein the second doped region packet
Include at least one described test-strips, the test-strips have second width, described the on the test-strips extending direction
One pole plate and the second pole plate lap have second length；
Second grid dielectric layer, Jie between the substrate and the second grid structure, as second test block
Electric matter, the second capacitor is collectively formed with first pole plate of second test block and the second pole plate.
8. monitoring of structures according to claim 6, which is characterized in that the second grid structure include it is several each other
The connector of every one end of the spaced test-strips and several test-strips of connection.
9. monitoring of structures according to claim 7, which is characterized in that second doped region include it is several each other
Connector every every one end of the test-strips and connection test-strips of setting.
10. monitoring of structures according to claim 6 or 7, which is characterized in that first test block includes third doping
Area, the third doped region are located at the side of the first capacitor device of first test block；
Second test block includes the 4th doped region, and the 4th doped region is located at the side of second capacitor.
11. monitoring of structures according to claim 10, which is characterized in that in first test block, described first mixes
Miscellaneous area and the third doped region are grounded, and the first grid structure connects high potential；
In second test block, second doped region and the 4th doped region are grounded, the second grid knot
Structure connects high potential.
12. a kind of monitoring method of the critical size of semiconductor technology, which comprises the following steps:
Step S1, tests the first electrical parameter of the first test block, and first test block has the first width and the first length；
Step S2 tests the second electrical parameter of the second test block, and second test block includes at least one test-strips, described
Test-strips have the second width and the second length, wherein second width is much smaller than first width, the first length, the
Two length, the design size of second width are the critical size of the semiconductor technology；
Step S3, according to the first electrical parameter of first test block, the first width, the first length and second test
Second electrical parameter of part, the second length monitor the actual size of second width；
Step S4, it is described by judging the actual size of second width compared with the design size of second width
Whether the critical size of semiconductor technology changes.
13. monitoring method according to claim 12, it is characterised in that:
In the step S1, the first electrical parameter of first test block is square resistance R1, and first test block is more
Crystal silicon resistor stripe, the first length of first test block are L1, and the first width is W1, the unit square of first test block
Resistance are as follows: R1/ (L1/W1)；
In the step S2, the second electrical parameter of second test block is square resistance R2, and second test block is more
Crystal silicon resistor stripe, the second length of the test-strips are L2, and the actual size of second width is W2, second test block
Unit square resistance be R2/ (L2/W2)；
In the step S3, according to the unit square electricity of the unit square resistance of first test block and second test block
Hinder identical, actual size W2, W2=R1 × W1 × L2/ (L1 × R2) of calculating second width；
In the step S4, the actual size W2 of second width is judged compared with the design size of second width
Whether the critical size of the semiconductor technology changes.
14. monitoring method according to claim 12, which is characterized in that
In the step S1, the first electrical parameter of first test block is capacitor C1, and first test block is the first electricity
Container, the first capacitor device include:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region and described first
The second pole plate of the substrate below gate structure together as first test block, wherein first pole plate and institute
The second pole plate lap is stated with first width and first length；
First grid dielectric layer, Jie between the substrate and the first grid structure, as first test block
Electric matter, first capacitor device is collectively formed with first pole plate and second pole plate；The first of first test block is mixed
Miscellaneous area and first grid structure lap have a first width W1 and the first length L1, and the first of first test block
Capacitor C1=L1 × W1 × K of capacitor, wherein K is constant；
In the step S2, the second electrical parameter of second test block is capacitor C2, and second test block is the second electricity
Container, second capacitor include:
Second grid structure is located in the substrate, using the first pole plate as second test block, wherein described second
Gate structure includes at least one described test-strips；
Second doped region, in the substrate of second grid structure two sides, second doped region and described second
The second pole plate of the substrate below gate structure together as second test block, wherein the test-strips are described
There is second width, first pole plate and institute on the test-strips extending direction on second grid structure extending direction
The second pole plate lap is stated with second length；
Second grid dielectric layer, Jie between the substrate and the second grid structure, as second test block
The second capacitor is collectively formed with first pole plate and second pole plate with second test block in electric matter, and described
Second width of the test-strips of two test blocks is W2, the first pole plate of second test block and the overlapping of the second pole plate
Partial size is the second length L2, capacitor C2=L2 × W2 × n2 × K of the second capacitor in second test block,
In, K is constant, and n2 is the number of the test-strips；
It is identical according to the numerical value of K in the step S3, calculate second width actual size be W2=(C2 × L1 ×
W1)/(C1×L2×n2)；
In the step S4, the actual size W2 of second width is judged compared with the design size of second width
Whether the critical size of the semiconductor technology changes.
15. monitoring method according to claim 12, which is characterized in that
In the step S1, the first electrical parameter of first test block is capacitor C1, and first test block is the first electricity
Container, the first capacitor device include:
Substrate；
First grid structure is located in the substrate, using the first pole plate as first test block；
First doped region, in the substrate of first grid structure two sides, first doped region and described first
The second pole plate of the substrate below gate structure together as first test block, wherein first pole plate and institute
The second pole plate lap is stated with first width and first length；
First grid dielectric layer, Jie between the substrate and the first grid structure, as first test block
Electric matter, first capacitor device is collectively formed with first pole plate and second pole plate；The first of first test block is mixed
Miscellaneous area and first grid structure lap have a first width W1 and the first length L1, and the first of first test block
Capacitor C1=L1 × W1 × K of capacitor, wherein K is constant；
In the step S2, the second electrical parameter of second test block is capacitor C2, and second test block is the second electricity
Container, second capacitor include:
Second grid structure is located above the substrate, using the first pole plate as second test block；
Second doped region, in the substrate below the second grid structure, second doped region and described second
The second pole plate of the substrate below gate structure together as second test block, wherein the second doped region packet
Include at least one described test-strips, the test-strips have second width, described the on the test-strips extending direction
One pole plate and the second pole plate lap have second length；
Second grid dielectric layer, Jie between the substrate and the second grid structure, as second test block
Electric matter, the second capacitor is collectively formed with first pole plate of second test block and the second pole plate, described second is surveyed
Second width of the test-strips of test specimen is W2, the first pole plate of second test block and the second pole plate lap
Size be the second length L2, capacitor C2=L2 × W2 × n2 × K of the second capacitor in second test block, wherein K is
Constant, n2 are the number of the test-strips；
It is identical according to the numerical value of K in the step S3, calculate second width actual size be W2=(C2 × L1 ×
W1)/(C1×L2×n2)；
In the step S4, the actual size W2 of second width is judged compared with the design size of second width
Whether the critical size of the semiconductor technology changes.
16. monitoring method according to claim 14 or 15, which is characterized in that
In the step S1, by first test block first doped region and third doped region be grounded, by institute
It states first grid structure and connects high potential, to measure the capacitor of the first capacitor device, the third doped region of first test block
Positioned at the side of the first capacitor device of first test block；
In the step S2, by second test block second pole plate and the 4th doped region be grounded, will be described
First pole plate connects high potential, and to measure the capacitor of second capacitor, the 4th doped region of second test block is located at institute
State the side of the second capacitor.
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| CN113109647A (en) * | 2021-04-09 | 2021-07-13 | 长鑫存储技术有限公司 | Method and system for analyzing electrical defects and electrical parameters of conductive structure |
| WO2023159777A1 (en) * | 2022-02-24 | 2023-08-31 | 长鑫存储技术有限公司 | Test arrangement and test method |
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| US20060172447A1 (en) * | 2005-01-28 | 2006-08-03 | Lsi Logic Corporation | Multi-layer registration and dimensional test mark for scatterometrical measurement |
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| CN104716123A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Testing method and testing structure |
| CN105514088A (en) * | 2014-10-16 | 2016-04-20 | 北大方正集团有限公司 | Semiconductor device and measuring method of key size |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113109647A (en) * | 2021-04-09 | 2021-07-13 | 长鑫存储技术有限公司 | Method and system for analyzing electrical defects and electrical parameters of conductive structure |
| CN113109647B (en) * | 2021-04-09 | 2022-04-29 | 长鑫存储技术有限公司 | Method and system for analyzing electrical defects and electrical parameters of conductive structure |
| WO2023159777A1 (en) * | 2022-02-24 | 2023-08-31 | 长鑫存储技术有限公司 | Test arrangement and test method |
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