CN110400788B - Test structure and test method for checking design rule of semiconductor device - Google Patents
Test structure and test method for checking design rule of semiconductor device Download PDFInfo
- Publication number
- CN110400788B CN110400788B CN201810381493.6A CN201810381493A CN110400788B CN 110400788 B CN110400788 B CN 110400788B CN 201810381493 A CN201810381493 A CN 201810381493A CN 110400788 B CN110400788 B CN 110400788B
- Authority
- CN
- China
- Prior art keywords
- test
- test unit
- doped regions
- doped region
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a test structure and a test method for checking design rules of a semiconductor device. The test structure includes a plurality of test units, the test structure has a plurality of test units, each test unit includes: at least one doped region; the first electric connection pieces are positioned below the doped regions; the plurality of second electric connecting pieces are positioned above the doped regions; each doped region is connected with one first electric connecting piece and one second electric connecting piece in series respectively; and determining the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device as the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device. Design rules for minimum size of the doped region may be determined by the test structure and method.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a test structure and a test method for checking design rules of a semiconductor device.
Background
The integrated circuit manufacturing technology is a complex process, and the technology is updated quickly. The high-level packaging method of the current product has high unit price, if the chip test can be carried out before the packaging, and the wafer is marked if the defective products exist in the wafer, the marked defective products are abandoned until the back-end packaging process, and the unnecessary packaging cost can be saved.
In the prior art, methods for wafer testing include various methods, wherein the most common method is Wafer Acceptance Test (WAT), and the WAT method is to test a special test pattern (test key) to control whether each step of process is normal and stable through electrical parameters.
In addition to the WAT test, Design Rule Check (DRC) is generally performed in the device fabrication process to Check the pattern, and whether the Design Rule Design is reasonable is checked according to the result of the DRC Check. Rule (rule) is too large, making the process safer, but this will sacrifice chip area, and if rule is too small, the process window is not enough, ultimately affecting customer yield. In addition, as in-line (inline) processes are adjusted, some rules may also be modified as the processes are adjusted, design rule checking and processes are used in conjunction, and DRC test structures are designed to take into account different applications at the time of design.
At present, a plurality of factories do not check the design rule of the minimum area of the N-well (Nwell), which brings potential risks to practical application, the on-line photoetching of the N-well has poor photo-resistance resolution, and if the N-well is designed to be small and possibly developed, the N-well is not opened, so that a circuit is broken, and therefore the design rule of efficiently detecting the minimum area of the N-well (Nwell) becomes an urgent problem to be solved.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a test structure for checking design rules of a semiconductor device, the test structure is provided with a plurality of test units, and each test unit comprises:
at least one doped region;
the first electric connection pieces are positioned below the doped regions;
the plurality of second electric connecting pieces are positioned above the doped regions;
each doped region is connected with one first electric connecting piece and one second electric connecting piece in series respectively;
and determining the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device as the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device.
Optionally, the number of the doped regions of the same test unit is greater than one, and the doped regions of the same test unit have the same size.
Optionally, each of the test units includes the same number of doped regions.
Optionally, the number of the doped regions included in each test unit is even, the doped regions of the same test unit are connected through the first electric connecting piece to form two-by-two connected doped regions, and the two-by-two connected doped regions are connected in series through the second electric connecting piece;
or the number of the doped regions included in each test unit is odd, the doped regions of the same test unit are connected through the first electric connecting piece to form two-by-two connected doped regions and one remaining unpaired doped region connected with the first electric connecting piece, and the two-by-two connected doped regions and the remaining unpaired doped region connected with the first electric connecting piece are connected in series through the second electric connecting piece.
Optionally, each of the test units includes one doped region, and the first electrical connectors are connected to each other.
Optionally, the doped region of each test unit is commonly connected to a first electrical connector, the first electrical connector is connected to a second electrical connector through a lead-out structure, and the doped region of each test unit is further respectively connected to different second electrical connectors.
Optionally, the test unit further includes a substrate and a common terminal, the test unit is formed on the substrate, the common terminal is a substrate lead-out terminal, the second electrical connectors at the head and tail ends of each test unit are respectively connected to a test point, one test point of each test unit is electrically connected to the high-side voltage of the power supply, the other test point of each test unit is electrically connected to the low-side voltage of the power supply, the common terminal of each test unit is connected to a reference voltage, and the reference voltage is less than or equal to the low-side voltage of the power supply.
Optionally, the doped regions of the number of test cells are reduced or increased in size in a gradient.
Optionally, the doped region comprises a well region; an N + active region is formed on the surface of the doped region;
the first electric connection piece comprises a deep well, and the conductivity type of the deep well is the same as that of the doped region;
the second electrical connector comprises:
the metal layer is arranged above the two electrically connected doped regions;
and the contact hole is positioned between the metal layer and the doped region.
The invention also provides a test method using the test structure, which comprises the following steps:
respectively measuring the resistance of each test unit;
judging whether the resistance of each test unit is consistent with the resistance expected according to the design rule of the semiconductor device;
the minimum size of the doped region of the test cell that conforms to the resistance expected by the semiconductor device design rule is determined as the minimum size of the semiconductor device design rule.
Optionally, the step of measuring the resistance of each test unit respectively includes: and respectively converting the resistance of each test unit into the resistance of each test unit only comprising one doped region according to the number of the doped regions included in each test unit.
Optionally, the determining whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device includes: and judging whether the resistance of each test unit is smaller than the resistance with the sudden change of the resistance value, wherein the resistance smaller than the sudden change of the resistance value conforms to the resistance expected according to the design rule of the semiconductor device.
Alternatively, the resistance having a sudden change in the resistance value is a resistance having a sharp increase or decrease in the resistance value.
The invention provides a test structure and a method for checking design rules of a semiconductor device, wherein the test structure comprises a plurality of test units, and each test unit comprises at least one doped region; the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device is determined to be the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device, and the design rule of the minimum size of the doped region can be determined by the test structure and the test method.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,
FIG. 1 is a schematic top view of a test structure according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of the test structure in an embodiment of the invention;
FIG. 3 is a block diagram of the test structure of FIG. 2;
FIG. 4 is a schematic cross-sectional view of the test structure of FIG. 1 taken along line A-A1;
FIG. 5 is a process flow diagram of the testing method in one embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the problems in the prior art, the present invention provides a test structure for checking design rules of a semiconductor device, the test structure having a plurality of test units, each test unit comprising:
at least one doped region;
the first electric connection pieces are positioned below the doped regions;
the plurality of second electric connecting pieces are positioned above the doped regions;
each doped region is connected with one first electric connecting piece and one second electric connecting piece in series respectively;
and determining the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device as the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device.
In the test structure, each test cell may include one doped region or include a plurality of doped regions having the same area, as described in further detail below with respect to various embodiments.
Example one
The test structure is further described below with reference to the accompanying drawings. Fig. 2 is a schematic structural diagram of the test structure in this embodiment.
Specifically, in the present invention, the test structure has three connection terminals, one connected to a high terminal (high), one connected to a low terminal (low), and a common termination substrate, in which a single doped region (e.g., N-well) is combined with a second electrical connector (e.g., a first metal layer) to form a test unit, wherein the doped regions of different test units have different sizes, and the minimum size of the doped region of the test unit corresponding to the resistance expected by the semiconductor device design rule is determined as the minimum size of the semiconductor device design rule by measuring and judging whether the resistance of each test unit corresponds to the resistance expected by the semiconductor device design rule. The method for judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device comprises the following steps: and judging whether the resistance of each test unit is smaller than the resistance with the sudden change of the resistance value, wherein the resistance smaller than the sudden change of the resistance value conforms to the resistance expected according to the design rule of the semiconductor device.
Specifically, fig. 2 is a schematic cross-sectional view of the test structure, and fig. 3 is a schematic structural view of a block portion of the test structure in fig. 2.
The test structure has a plurality of test units, each test unit including:
at least one doped region;
the first electric connection pieces are positioned below the doped regions;
the plurality of second electric connecting pieces are positioned above the doped regions;
each doped region is connected with one first electric connecting piece and one second electric connecting piece in series respectively;
and determining the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device as the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device.
In this embodiment, each of the test units includes one doped region, and the first electrical connectors are connected to each other.
Optionally, the doped region of each test unit is commonly connected to a first electrical connector, the first electrical connector is connected to a second electrical connector through a lead-out structure, and the doped region of each test unit is further respectively connected to different second electrical connectors.
Optionally, as shown in fig. 2, the extraction structure 108 includes a contact hole or a plug or a large-sized doped region, and is limited to a certain one, and is not described herein again.
Specifically, each test unit includes one doped region 102, each doped region is connected to one first electrical connector 101 and one second electrical connector, the first electrical connectors of each test unit are connected to each other and connected to one test point after leading out the substrate, and the doped regions of each test unit are separately led out through different second electrical connectors and connected to different test points, as shown in fig. 2.
Wherein the projected areas of the doped regions 102 are different in different test cells, and optionally the sizes of the doped regions of the several test cells are reduced or increased in a gradient manner.
In an embodiment of the present invention, the projection area of the doped region 102 of different test cells on the horizontal plane is decreased or increased by, for example, 2%, 5%, 8%, 10%, etc., and is not limited to a certain range of values.
The doped region, the first electric connecting piece and the second electric connecting piece are respectively positioned in different layers and sequentially comprise the first electric connecting piece, the doped region and the second electric connecting piece from bottom to top.
Optionally, the test structure may comprise a substrate, which may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
Optionally, the substrate is made of P-type polysilicon.
In an embodiment of the invention, the first electrical connection member includes a deep well, the deep well is of the same conductivity type as the doped region, and is disposed in the substrate, wherein the deep N well is formed by controlling the depth of the deep N well by controlling the ion implantation energy according to a conventional method, so that the deep N well is located at a target depth.
The first electrical connection 101 in this embodiment may be a complete deep well to which the doped regions of the individual test cells are connected, as shown in fig. 2. One side of the doped region of each test cell shares a first electrical connection 101 and is connected to a second electrical connection through a lead-out structure and finally to a test point. And the other side of the doped region of each test unit is respectively connected with different second electric connectors and finally respectively connected to different test points. Therefore, each test unit is provided with test points at the head end and the tail end.
The kind of the doped region is not limited to a certain kind, for example, a doped region formed by ion implantation, or a doped region formed by diffusion, etc., and the doped region may include various well regions, drift regions, etc. in the present invention. The doped region is an N-well or a P-well, and is not limited to a certain type.
In one embodiment of the invention, the doped region is an N-well, and the test structure and test method including other types of doped regions are similar to those including the N-well.
When the doped region of each test unit is an N-well, a plurality of N-wells are arranged at intervals, and a P-well is arranged between adjacent N-wells, and the structure is shown in fig. 3 in which the N-wells and the P-wells are alternately arranged at intervals.
Wherein the N-well is performed after the deep N-well ion implantation, and a depth of the N-well is controlled by controlling an energy of the ion implantation to locate the N-well at a target depth.
The deep N-well and the N-well may have the same or different doping concentrations, and may be specifically selected according to actual needs.
Optionally, as shown in fig. 2, the second electrical connector comprises:
a metal layer 104 disposed above the two electrically connected doped regions;
and a contact hole 103 between the metal layer and the doped region.
The forming method of the metal layer and the contact hole may be a method commonly used in the art, and is not described herein again.
It should be noted that the contact holes may be replaced by through holes or through silicon vias, and the metal layer may be replaced by other metallization materials, and the variations may be applied to this embodiment of the present invention.
Optionally, an N + active region 107 is further formed on the surface of the doped region.
Optionally, the test unit further includes a substrate and a common terminal 105, the test unit is formed on the substrate, the common terminal is a substrate lead-out terminal, the second electrical connectors at the head and tail ends of each test unit are respectively connected to a test point, one test point of each test unit is electrically connected to the high-side voltage of the power supply, the other test point of each test unit is electrically connected to the low-side voltage of the power supply, the common terminal of each test unit is connected to a reference voltage, and the reference voltage is less than or equal to the low-side voltage of the power supply.
As shown in fig. 2, the first electrical connector 101 of each test unit is connected to a second electrical connector by being led out of the substrate through the lead-out structure 108, and the doped regions of each test unit are electrically connected to different second electrical connectors through the N + active regions 107, respectively. The common terminal 105 is disposed on the P-well and electrically connected to a reference voltage through the P + active region 106.
Optionally, the test structure further includes an isolation structure disposed in the substrate for isolating the adjacent doped regions, where the isolation structure may be an isolation structure commonly used in the art, such as a shallow trench isolation structure.
The invention provides a test structure for checking design rules of a semiconductor device, wherein each test unit comprises a doped region; wherein the doped regions of different test cells have different sizes. The second electric connectors at the head end and the tail end of each test unit are respectively connected with a test point, one test point of each test unit is electrically connected with the high-end voltage of the power supply, the other test point of each test unit is electrically connected with the low-end voltage of the power supply, and the common end of each test unit is connected with the reference voltage.
The resistance of each test unit is respectively measured by the test points at the head end and the tail end of each test unit. The condition that the resistance value of the resistor of a certain test unit is sharply increased or decreased by multiple times is the condition that the resistance value is suddenly changed, and the resistor of the test unit is the resistor with the suddenly changed resistance value.
And judging whether the resistance of each test unit is smaller than the resistance with the sudden change of the resistance value, wherein the resistance with the sudden change of the resistance value is consistent with the resistance expected according to the design rule of the semiconductor device.
In a test cell that conforms to a resistance expected by a semiconductor device design rule, the minimum size of the doped region is the minimum size of the semiconductor device design rule. The design rule for the maximum dimension of the doped region can be determined by the test structure and method.
Example two
The difference between this embodiment and the first embodiment is that the number of doped regions of each test unit is greater than one, and the doped regions of the same test unit have the same size. When only one doped region is disposed as a measurement object in each test cell, as in the first embodiment, the difference in the structure of the doped regions with the same size due to the process instability cannot be avoided, so that the data has an error (the error is still within an acceptable range). In the second embodiment, the number of doped regions with the same size is increased, so that structural differences of doped regions with the same size caused by process instability are avoided, the accuracy of the measured resistance of each test unit is ensured, data errors are reduced, and the measurement result is more accurate.
Optionally, the number of doped regions included in each of the test cells may be the same or different.
In this embodiment, each of the test cells includes the same number of doped regions.
In one embodiment, a test structure for checking design rules of a semiconductor device includes a plurality of test cells. The number of the doped regions included in each test unit is even, the doped regions of the same test unit are connected through the first electric connecting piece to form two-to-two connected doped regions, and the two-to-two connected doped regions are connected in series through the second electric connecting piece; and the second electric connecting pieces at the head end and the tail end of each test unit are respectively connected with one test point.
In one embodiment, a test structure for checking design rules of a semiconductor device includes a plurality of test cells. The number of the doped regions included in each test unit is odd, the doped regions of the same test unit are connected through the first electric connecting piece to form a pairwise connected doped region and a residual unpaired doped region connected with the first electric connecting piece, the pairwise connected doped region and the residual unpaired doped region connected with the first electric connecting piece are connected in series through the second electric connecting piece, in each test unit, the first electric connecting piece connected with the residual unpaired doped region is led out of the substrate through the leading-out structure and is connected to the second electric connecting piece, and the pairwise connected doped region, the residual unpaired doped region and the first electric connecting piece connected with the residual unpaired doped region are connected in series through the second electric connecting piece. And the second electric connecting pieces at the head end and the tail end of each test unit are respectively connected with one test point.
In one embodiment, a test structure for checking design rules of a semiconductor device includes a plurality of test cells. Some test cells include an even number of doped regions, and some test cells include an odd number of doped regions.
In which fig. 4 shows an example of a test cell comprising a plurality of doped regions 102, for example comprising a first doped region, a second doped region, a third doped region, a fourth doped region to an nth doped region, wherein one of the first electrical connections connects the first doped region and the second doped region, wherein the second doped region and the third doped region are not connected to each other on the layer on which the first electrical connection is located, but the second doped region and said third doped region are connected by a second electrical connection there over, then the test unit is extended by taking the structure as a basic repeating unit, for example, the third doped region and the fourth doped region are connected through another first electric connecting piece, wherein the fourth doped region and the fifth doped region are connected by another second electrical connection, repeated in the manner described, to form a complete test cell.
The length of the test unit is not limited to a certain range of values, and may include only two doped regions, but a plurality of doped regions are provided for measuring the accuracy of the obtained data.
The doped region, the first electrical connector and the second electrical connector are respectively located in different layers and sequentially form the first electrical connector, the doped region and the second electrical connector from bottom to top, so that the test structure is arranged in a zigzag bent chain-shaped test unit in different layers, but the bent form is not limited to the shape shown in fig. 4, and can also be other bent shapes, which are not listed here.
The top view of each test unit is shown in fig. 1, the test unit may have any shape in the horizontal plane, for example, the test unit may have a serpentine curve as shown in fig. 1, a spiral shape, or a random curve, and the extending shape is not limited to a certain shape, and all possible shapes may be applied to the present application.
Optionally, as shown in fig. 4, the second electrical connector comprises:
a metal layer 104 disposed above the two electrically connected doped regions;
and a contact hole 103 between the metal layer and the doped region.
The forming method of the metal layer and the contact hole may be a method commonly used in the art, and is not described herein again.
Optionally, the test structure further includes a substrate and a common terminal 105, the test unit is formed on the substrate, and the common terminal 105 is a substrate lead-out terminal. The second electric connectors at the head end and the tail end of each test unit are respectively connected with a test point. One test point of each test cell is electrically connected to the high side voltage of the power supply, another test point of each test cell is electrically connected to the low side voltage of the power supply, and the common terminal 105 of each test cell is connected to a reference voltage. The reference voltage is less than or equal to a low-side voltage of the power supply.
The doped regions at the head end and the tail end of the test unit are electrically connected with different second electric connectors through the N + active regions respectively, the common end is arranged on the P well, and the electric connection with the reference voltage is realized through the P + active regions.
Specifically, the test units are formed on the substrate, the common terminal is a substrate leading-out terminal, the second electric connectors at the head and tail ends of each test unit are respectively connected with a test point, one test point of each test unit is electrically connected with the high-end voltage of a power supply, the other test point of each test unit is electrically connected with the low-end voltage of the power supply, the common terminal of each test unit is connected with a reference voltage, and the reference voltage is less than or equal to the low-end voltage of the power supply.
The invention provides a test structure for checking design rules of a semiconductor device, each test unit comprises a plurality of doped regions, and each test unit can form a chain structure. And the doped regions of different test units have different sizes. The second electric connectors at the head end and the tail end of each test unit are respectively connected with a test point, one test point of each test unit is electrically connected with the high-end voltage of the power supply, the other test point of each test unit is electrically connected with the low-end voltage of the power supply, and the common end of each test unit is connected with the reference voltage.
The resistance of each test unit is respectively measured by the test points at the head end and the tail end of each test unit. The condition that the resistance value of the resistor of a certain test unit is sharply increased or decreased by multiple times is the condition that the resistance value is suddenly changed, and the resistor of the test unit is the resistor with the suddenly changed resistance value.
And judging whether the resistance of each test unit is smaller than the resistance with the sudden change of the resistance value, wherein the resistance smaller than the sudden change of the resistance value conforms to the resistance expected according to the design rule of the semiconductor device.
In the test unit which is consistent with the resistance expected according to the design rule of the semiconductor device, the minimum size of the doped region is the minimum size of the design rule of the semiconductor device, the structure difference of the doped regions with the same size caused by the instability of the process can be avoided through the structure, and the data error of the measured resistance is reduced.
EXAMPLE III
The invention also provides a test method based on the test structure of the first embodiment or the second embodiment, as shown in fig. 4, the method comprises the following steps:
step S1: respectively measuring the resistance of each test unit;
step S2: judging whether the resistance of each test unit is consistent with the resistance expected according to the design rule of the semiconductor device;
step S3: the minimum size of the doped region of the test cell that conforms to the resistance expected by the semiconductor device design rule is determined as the minimum size of the semiconductor device design rule.
Optionally, the step S1 of respectively measuring the resistance of each test unit includes: and respectively converting the resistance of each test unit into the resistance of each test unit only comprising one doped region according to the number of the doped regions included in each test unit.
Optionally, the step S2 of determining whether the resistance of each test cell conforms to the resistance expected according to the design rule of the semiconductor device includes: and judging whether the resistance of each test unit is smaller than the resistance with the sudden change of the resistance value, wherein the resistance smaller than the sudden change of the resistance value conforms to the resistance expected according to the design rule of the semiconductor device.
Alternatively, the resistance having a sudden change in the resistance value is a resistance having a sharp increase or decrease in the resistance value.
The number of the doped regions of each test unit in the test structure is one, the measured resistance of each test unit is the resistance only comprising one doped region, and the resistances of the test units are directly compared.
The number of the doped regions of each test unit in the test structure is greater than one, and the number of the doped regions included in each test unit is the same, so that the test structure does not need to be converted into the resistance of each test unit including only one doped region, and the comparison can be directly carried out.
The minimum size of the doping region is selected as the minimum size of the semiconductor device design rule of the application.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the foregoing illustrative embodiments are merely exemplary and are not intended to limit the scope of the invention thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A test structure for checking design rules of a semiconductor device, the test structure having a plurality of test cells, each test cell comprising:
at least one doped region;
the first electric connection pieces are positioned below the doped regions;
the plurality of second electric connecting pieces are positioned above the doped regions;
each doped region is connected with one first electric connecting piece and one second electric connecting piece in series respectively;
and determining the minimum size of the doped region of the test unit which conforms to the resistance expected according to the design rule of the semiconductor device as the minimum size of the design rule of the semiconductor device by measuring and judging whether the resistance of each test unit conforms to the resistance expected according to the design rule of the semiconductor device.
2. The test structure of claim 1, wherein the number of doped regions of the same test cell is greater than one, and the doped regions of the same test cell are the same size.
3. The test structure of claim 2, wherein each of the test cells comprises the same number of doped regions.
4. The test structure as claimed in claim 3, wherein each of the test cells includes an even number of doped regions, the doped regions of the same test cell are connected by the first electrical connection to form two-by-two connected doped regions, and the two-by-two connected doped regions are connected in series by the second electrical connection;
or the number of the doped regions included in each test unit is odd, the doped regions of the same test unit are connected through the first electric connecting piece to form two-by-two connected doped regions and one remaining unpaired doped region connected with the first electric connecting piece, and the two-by-two connected doped regions and the remaining unpaired doped region connected with the first electric connecting piece are connected in series through the second electric connecting piece.
5. The test structure as claimed in claim 1, wherein each of the test cells includes one doped region, and the plurality of first electrical connections are connected to each other.
6. The test structure of claim 5, wherein the doped regions of the test cells are commonly connected to a first electrical connector, the first electrical connector is connected to a second electrical connector through the lead-out structure, and the doped regions of the test cells are further respectively connected to different second electrical connectors.
7. The test structure of claim 4 or 6, wherein the test unit further comprises a substrate and a common terminal, the test unit is formed on the substrate, the common terminal is a substrate lead-out terminal, the second electrical connectors at the head and tail ends of each test unit are respectively connected with a test point, one test point of each test unit is electrically connected with the high-end voltage of a power supply, the other test point of each test unit is electrically connected with the low-end voltage of the power supply, the common terminal of each test unit is connected with a reference voltage, and the reference voltage is less than or equal to the low-end voltage of the power supply.
8. The test structure of claim 1 or 3, wherein the doped regions of the number of test cells are graded to decrease or increase in size.
9. The test structure of claim 1 or 3, wherein the doped region comprises a well region; an N + active region is formed on the surface of the doped region;
the first electric connection piece comprises a deep well, and the conductivity type of the deep well is the same as that of the doped region;
the second electrical connector comprises:
the metal layer is arranged above the two electrically connected doped regions;
and the contact hole is positioned between the metal layer and the doped region.
10. A method of testing using the test structure of any of claims 1 to 9, the method comprising:
respectively measuring the resistance of each test unit;
judging whether the resistance of each test unit is consistent with the resistance expected according to the design rule of the semiconductor device;
the minimum size of the doped region of the test cell that conforms to the resistance expected by the semiconductor device design rule is determined as the minimum size of the semiconductor device design rule.
11. The method of claim 10, wherein the step of separately measuring the resistance of each of the test cells comprises: and respectively converting the resistance of each test unit into the resistance of each test unit only comprising one doped region according to the number of the doped regions included in each test unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810381493.6A CN110400788B (en) | 2018-04-25 | 2018-04-25 | Test structure and test method for checking design rule of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810381493.6A CN110400788B (en) | 2018-04-25 | 2018-04-25 | Test structure and test method for checking design rule of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110400788A CN110400788A (en) | 2019-11-01 |
| CN110400788B true CN110400788B (en) | 2021-04-09 |
Family
ID=68320337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810381493.6A Active CN110400788B (en) | 2018-04-25 | 2018-04-25 | Test structure and test method for checking design rule of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110400788B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112927746B (en) * | 2019-12-05 | 2023-04-25 | 浙江驰拓科技有限公司 | Magnetic memory test structure and test method |
| CN111081682B (en) * | 2019-12-10 | 2021-09-03 | 上海华力微电子有限公司 | Semiconductor test structure and test method |
| CN113484718A (en) * | 2021-06-09 | 2021-10-08 | 深圳莱宝高科技股份有限公司 | Detection circuit structure and detection method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890195A (en) * | 2011-07-20 | 2013-01-23 | 上海华虹Nec电子有限公司 | Structure and method for testing resistances of contact holes on same type active region with substrate |
| CN102955363A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Optical proximity correction online monitoring method |
| CN105514088A (en) * | 2014-10-16 | 2016-04-20 | 北大方正集团有限公司 | Semiconductor device and measuring method of key size |
| CN107122552A (en) * | 2017-05-02 | 2017-09-01 | 上海华力微电子有限公司 | A kind of method of the regular inspection result of automatic review of design |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834759B (en) * | 2014-02-12 | 2018-04-20 | 台湾积体电路制造股份有限公司 | The implementation method and device of Electronic Design |
-
2018
- 2018-04-25 CN CN201810381493.6A patent/CN110400788B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890195A (en) * | 2011-07-20 | 2013-01-23 | 上海华虹Nec电子有限公司 | Structure and method for testing resistances of contact holes on same type active region with substrate |
| CN102955363A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Optical proximity correction online monitoring method |
| CN105514088A (en) * | 2014-10-16 | 2016-04-20 | 北大方正集团有限公司 | Semiconductor device and measuring method of key size |
| CN107122552A (en) * | 2017-05-02 | 2017-09-01 | 上海华力微电子有限公司 | A kind of method of the regular inspection result of automatic review of design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110400788A (en) | 2019-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110400788B (en) | Test structure and test method for checking design rule of semiconductor device | |
| US20090057664A1 (en) | E-beam inspection structure for leakage analysis | |
| CN203133171U (en) | Testing device for testing wafer of electronic circuit | |
| KR102576210B1 (en) | Semiconductor device | |
| CN102931170B (en) | A kind of detection architecture and formation method and detection method | |
| CN106684008B (en) | The reliability testing structure and its test method of semiconductor devices | |
| CN110335861B (en) | Semiconductor device and manufacturing method thereof | |
| US9704624B2 (en) | Integrated circuit (IC) including semiconductor resistor and resistance compensation circuit and related methods | |
| US10247774B2 (en) | Test key structure and method of measuring resistance of vias | |
| CN110364447B (en) | Monitoring structure and monitoring method for critical dimension of semiconductor process | |
| CN104752247B (en) | The detection structure and preparation method of a kind of metal bridging defect | |
| US7808248B2 (en) | Radio frequency test key structure | |
| US20140346510A1 (en) | Device structure suitable for parallel test | |
| EP1579504A1 (en) | Method of producing semiconductor elements using a test structure | |
| CN115706073A (en) | Semiconductor structure and manufacturing method thereof | |
| CN113791276A (en) | Method for testing resistance value of resistor | |
| CN211980612U (en) | Test structure | |
| CN113097087A (en) | Semiconductor device and test method thereof | |
| CN111341834B (en) | Test structure and semiconductor device | |
| CN114141641A (en) | Semiconductor device and method for manufacturing the same | |
| US10283425B2 (en) | Test key and method for monitoring semiconductor wafer | |
| US11372061B2 (en) | Hall effect sensor devices and methods of forming hall effect sensor devices | |
| CN206697478U (en) | Wafer sort structure | |
| CN105336636A (en) | Test structure and test method | |
| US11854915B2 (en) | Electrical test structure, semiconductor structure and electrical test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |