CN110364562A - 集成电路器件 - Google Patents

集成电路器件 Download PDF

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Publication number
CN110364562A
CN110364562A CN201910125807.0A CN201910125807A CN110364562A CN 110364562 A CN110364562 A CN 110364562A CN 201910125807 A CN201910125807 A CN 201910125807A CN 110364562 A CN110364562 A CN 110364562A
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China
Prior art keywords
fin
isolated insulation
insulation part
area
fin isolated
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CN201910125807.0A
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CN110364562B (zh
Inventor
郑在烨
金一龙
金柱然
金辰昱
吕京奂
郑镛琦
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种集成电路器件包括：多个鳍型有源区从其突出的基板，所述多个鳍型有源区在第一方向上彼此平行地延伸；以及多个栅极结构和多个鳍隔离绝缘部分，在交叉第一方向的第二方向上在基板上延伸并且在第一方向具有恒定的节距，其中所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在所述多个栅极结构当中的一对栅极结构之间，所述多个鳍型有源区包括多个第一鳍型区和多个第二鳍型区。

Description

集成电路器件
技术领域
发明构思涉及集成电路器件，更具体地，涉及包括鳍型有源区的集成电路器件。
背景技术
随着电子技术的发展，集成电路器件迅速缩小尺寸。对于高度集成的电路器件，不仅需要高操作速度，还需要操作精度。因此，需要开发一种集成电路器件，该集成电路器件具有能够将导线和接触占据的面积减小到集成电路器件的相对小的区域并稳定地获得导线和接触之间的绝缘距离的结构。而且，期望一种实现这种集成电路器件的方法。
发明内容
发明构思提供一种具有包括晶体管结构的集成电路器件，即使当元件区域由于集成电路器件的按比例缩小而减小时，该集成电路器件也能够提供改善的性能。
根据发明构思的一些示例实施方式，提供一种集成电路器件，该集成电路器件包括：基板；从基板突出的多个鳍型有源区，所述多个鳍型有源区在第一方向上彼此平行地延伸；和在交叉第一方向的第二方向上在基板上延伸的多个栅极结构和多个鳍隔离绝缘部分，所述多个栅极结构和所述多个鳍隔离绝缘部分沿第一方向具有恒定的节距。多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在一对栅极结构的第一元件与该对栅极结构的第二元件之间，该对栅极结构在所述多个栅极结构当中。多个鳍型有源区包括多个第一鳍型区和多个第二鳍型区，其中所述多个第一鳍型区当中的一对第一鳍型区在第一方向上以直线延伸，并且在其间具有所述一对鳍隔离绝缘部分的情况下彼此间隔开，并且所述多个第二鳍型区中的一个在该对鳍隔离绝缘部分之间。
根据发明构思的一些示例实施方式，提供一种集成电路器件，该集成电路器件包括：基板；从基板突出的多个鳍型有源区，所述多个鳍型有源区具有第一区域和第二区域，所述多个鳍型有源区在第一方向上彼此平行地延伸；和在交叉第一方向的第二方向上在基板上延伸的多个栅极结构和多个鳍隔离绝缘部分，所述多个栅极结构和所述多个鳍隔离绝缘部分在第一方向上具有恒定的节距。所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在所述多个栅极结构当中的一对栅极结构的第一元件和第二元件之间。所述多个鳍隔离绝缘部分包括在第一区域中的第一鳍隔离绝缘部分和在第二区域中的第二鳍隔离绝缘部分，其中第一鳍隔离绝缘部分的至少一部分具有与第二鳍隔离绝缘部分的至少一部分不同的材料。
根据发明构思的一些示例实施方式，提供一种集成电路器件，该集成电路器件包括：基板；从基板突出的多个鳍型有源区，所述多个鳍型有源区具有第一区域和第二区域并且在第一方向上彼此平行地延伸；和多个栅极结构和多个鳍隔离绝缘部分，在交叉第一方向的第二方向上在基板上延伸并在第一方向上具有恒定的节距。所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在所述多个栅极结构当中的在第一区域中的一对栅极结构的第一元件与第二元件之间。所述多个鳍隔离绝缘部分当中的一个鳍隔离绝缘部分在所述多个栅极结构当中的在第二区域中的一对栅极结构之间。
附图说明
通过以下结合附图的详细描述，将更清楚地理解发明构思的一些示例实施方式，其中：
图1是用于描述根据一些示例实施方式的集成电路器件的平面布局图；
图2A是用于描述根据一些示例实施方式的集成电路器件的剖视图；
图2B是用于描述根据一些示例实施方式的集成电路器件的剖视图；
图2C是用于描述根据一些示例实施方式的集成电路器件的剖视图；
图2D是用于描述根据一些示例实施方式的集成电路器件的剖视图；
图3A和图3B至图16A、图16B和图16C是用于描述根据一些示例实施方式的制造集成电路器件的方法的剖视图，该剖视图以该方法的顺序次序示出；
图17A至图17D是用于描述根据一些示例实施方式的制造集成电路器件的方法的剖视图，该剖视图以该方法的顺序次序示出；
图18A至图18C是用于描述根据一些示例实施方式的集成电路器件的剖视图；和
图19是用于描述根据其它实施方式的集成电路器件的平面布局图。
具体实施方式
图1是用于描述根据一些示例实施方式的集成电路器件100的平面布局图，图2A是用于描述根据一些示例实施方式的集成电路器件100的剖视图。图2A是沿图1的线X1-X1'截取的示例剖视图。
参考图1和图2A，集成电路器件100可以包括鳍型场效应晶体管(FinFET)器件。FinFET器件可以包括逻辑单元。逻辑单元可以被各种各样地形成并且包括多个电路元件，诸如晶体管、寄存器等。逻辑单元可以包括例如AND、NAND、OR、NOR、异或(XOR)、异或非(XNOR)、反相器(INV)、加法器(ADD)、缓冲器(BUF)、延迟(DLY)、滤波器(FIL)、多路复用器(MXT/MXIT)、或/和/反相器(OAI)、和/或(AO)、和/或/反相器(AOI)、D触发器、复位触发器、主从触发器、锁存器和/或其它元件，逻辑单元可以包括执行期望的逻辑功能的标准单元，诸如计数器、缓冲器和/或其它元件。
集成电路器件100还可以包括具有元件区RX的基板110以及在元件区RX中从基板110突出的多个鳍型有源区FA和FB。基板110可以具有在水平方向(X-Y平面方向)上在竖直水平LV1处延伸的第一表面110M。基板110可以包括半导体诸如Si或Ge或化合物半导体诸如SiGe、SiC、GaAs、InAs或InP。基板110还可以包括导电区。例如，基板110可以包括掺杂有杂质的阱或掺杂有杂质的结构。
深沟槽(参考图3B的DT)可以形成在元件区RX周围的基板110中，并且元件隔离区DTA可以形成在深沟槽DT上。
多个鳍型有源区FA和FB可以在第一方向(X方向)上彼此平行地延伸。如图3B所示，元件隔离层112可以形成在基板110上在多个鳍型有源区FA和FB之间的区域中以及在元件隔离区DTA中。多个鳍型有源区FA和FB可以在元件区RX中突出到元件隔离层112上方成鳍形状。
元件隔离层112可以包括例如硅氧化物层。然而，发明构思不限于此。在一些示例实施方式中，元件隔离层112可以包括顺序堆叠在基板110上的第一绝缘衬垫、第二绝缘衬垫和掩埋绝缘层。
在一些示例实施方式中，第一绝缘衬垫可以包括第一氧化物层。第一氧化物层可以通过沉积工艺或通过热氧化多个鳍型有源区FA和FB的表面来获得。在一些示例实施方式中，第二绝缘衬垫可以包括硅氮化物(SiN)、硅氮氧化物(SiON)、硼硅氮化物(SiBN)、硅碳化物(SiC)、SiC:H、SiCN、SiCN:H、SiOCN、SiOCN:H、硅碳氧化物(SiOC)、多晶硅或其组合，但是发明构思不限于此。在一些示例实施方式中，掩埋绝缘层可以包括第二氧化物层。第二氧化物层可以包括通过沉积工艺或涂覆工艺形成的层。例如，第二氧化物层可以包括氟硅酸盐玻璃(FSG)、未掺杂硅酸盐玻璃(USG)、硼磷硅酸盐玻璃(BPSG)、磷硅酸盐玻璃(PSG)、可流动氧化物(FOX)、等离子体增强正硅酸乙酯(PE-TEOS)和/或东燃硅氮烷(tonen silazene，TOSZ)，但发明构思不限于此。
多个栅极结构GS可以在与多个鳍型有源区FA和FB交叉的第二方向(Y方向)上在基板110上延伸。多个栅极结构GS可以在第一方向(X方向)上具有相同的宽度，并且可以在第一方向(X方向)上具有恒定的节距PT。多个栅极结构GS中的每一个可以包括栅极绝缘层132和栅极线GL的堆叠。栅极绝缘层132可以覆盖栅极线GL的底表面和两个侧壁。
多个栅极结构GS可以延伸以覆盖多个鳍型有源区FA和FB中的每一个的顶表面和两个侧壁以及元件隔离层112的顶表面。多个金属氧化物半导体(MOS)晶体管可以沿着多个栅极结构GS形成在元件区RX中。多个MOS晶体管中的每一个可以是三维(3d)MOS晶体管，该3d MOS晶体管在多个鳍型有源区FA和FB的顶表面和两个侧壁处具有沟道。
多个栅极结构GS中的一个或更多个可以包括多个虚设栅极结构DGS。多个虚设栅极结构DGS可以包括栅极绝缘层132和栅极线GL的堆叠。然而，虚设栅极结构DGS可以在集成电路器件100的操作期间保持电浮置状态。在一些示例实施方式中，可以省略虚设栅极结构DGS。
多个栅极绝缘层132可以包括硅氧化物层、高k电介质层或其组合。高k电介质层可以包括具有比硅氧化物层的材料高的介电常数的材料。高k电介质层可以包括金属氧化物和/或金属氮氧化物。界面层可以插置在鳍型有源区FA和FB与栅极绝缘层132之间层。界面层可以包括氧化物层、氮化物层或氮氧化物层。
多条栅极线GL可以具有顺序堆叠的金属氮化物层、金属层、导电覆盖层和间隙填充金属层的结构。金属氮化物层和金属层可以包括选自Ti、Ta、W、Ru、Nb、Mo和Hf中的至少一种金属。间隙填充金属层可以包括W层或Al层。多条栅极线GL中的每一条可以包括含功函数金属的层。含功函数金属的层可以包括选自Ti、W、Ru、Nb、Mo、Hf、Ni、Co、Pt、Yb、Tb、Dy、Er和Pd中的至少一种金属。在一些示例实施方式中，多条栅极线GL中的每一条可以包括TiAlC/TiN/W的堆叠、TiN/TaN/TiAlC/TiN/W的堆叠或TiN/TaN/TiN/TiAlC/TiN/W的堆叠，但不限于此。
多个栅极结构GS的顶表面可以被多个栅极绝缘覆盖层140覆盖。多个栅极绝缘覆盖层140可以包括硅氮化物层。
多个鳍隔离绝缘部分FS可以在基板110上在第二方向(Y方向)上彼此平行地延伸。彼此间隔开的一对鳍隔离绝缘部分FS可以在元件区RX中的一对栅极结构GS之间。多个鳍隔离绝缘部分FS可以在元件区RX中在第二方向(Y方向)上延伸得长。两个栅极结构GS和两个鳍隔离绝缘部分FS可以在元件区RX中在第一方向(X方向)上交替。
以直线形式延伸的一对虚设栅极结构DGS可以在元件区RX的在第二方向(Y方向)上的两个外侧处，在该对虚设栅极结构DGS之间具有一个鳍隔离绝缘部分FS。因此，在元件区RX中，多个栅极结构GS和多个鳍隔离绝缘部分FS可以在第一方向(X方向)上具有恒定节距PT，并且两个栅极结构GS和两个鳍隔离绝缘部分FS可以在第一方向(X方向)上交替。
鳍隔离绝缘部分FS可以位于多个MOS晶体管绕其形成的多个栅极结构GS的一侧。鳍隔离绝缘部分FS可以在两个相邻栅极结构GS中的每一个的外侧。鳍隔离绝缘部分FS可以将拉应力或压应力施加到与鳍隔离绝缘部分FS相邻的鳍型有源区FA和FB的沟道区。因此，由于鳍隔离绝缘部分FS引起的应力可以被施加到沿着这两个相邻的栅极结构GS中的每一个形成的多个MOS晶体管，以提升或降低多个MOS晶体管中的每一个的特性。
鳍隔离绝缘部分FS可以包括下部鳍隔离绝缘部分LS和位于下部鳍隔离绝缘部分LS上的上部鳍隔离绝缘部分US。上部鳍隔离绝缘部分US的至少一部分可以具有与下部鳍隔离绝缘部分LS的至少一部分不同的材料。上部鳍隔离绝缘部分US和下部鳍隔离绝缘部分LS可以在垂直方向(Z方向)上相对于彼此对准。下部鳍隔离绝缘部分LS可以从上部鳍隔离绝缘部分US朝向基板110突出。下部鳍隔离绝缘部分LS可以不在元件隔离区DTA中。上部鳍隔离绝缘部分US的底表面和下部鳍隔离绝缘部分LS的顶表面可以彼此接触。栅极结构GS可以不位于下部鳍隔离绝缘部分LS的向上方向(Z方向)上。而是，上部鳍隔离绝缘部分US可以位于下部鳍隔离绝缘部分LS的向上方向(Z方向)上。下部鳍隔离绝缘部分LS可以包括芯绝缘图案LSC以及覆盖芯绝缘图案LSC的侧表面和底表面的外围绝缘图案LSO。芯绝缘图案LSC和外围绝缘图案LSO可以包括彼此不同的材料。
在一些示例实施方式中，外围绝缘图案LSO可以包括氮化物层，并且芯绝缘图案LSC和上部鳍隔离绝缘部分US可以包括氧化物层。芯绝缘图案LSC和上部鳍隔离绝缘部分US可以通过彼此不同的沉积工艺形成。例如，芯绝缘图案LSC可以是或可以包括通过原子层沉积(ALD)工艺形成的氧化物层，并且上部鳍隔离绝缘部分US可以是或可以包括通过化学气相沉积(CVD)工艺形成的氧化物层。
上部鳍隔离绝缘部分US可以形成为包括单一材料的单层结构，例如均质材料，但是发明构思不限于此。在一些示例实施方式中，上部鳍隔离绝缘部分US可以具有在其中多个绝缘图案顺序地堆叠的多层结构。例如，上部鳍隔离绝缘部分US可以具有其中通过彼此不同的沉积方法形成的至少两个硅氧化物图案顺序堆叠的多层结构。例如，上部鳍隔离绝缘部分US可以具有其中通过CVD工艺形成的至少两个硅氧化物图案堆叠在通过ALD工艺形成的硅氧化物图案上的结构。
下部鳍隔离绝缘部分LS可以位于基板110的第一表面110M的竖直水平LV1与栅极结构GS的最上表面的竖直水平LVG之间。下部鳍隔离绝缘部分LS的最下表面的竖直水平LV2可以高于基板110的第一表面110M的竖直水平LV1，并且可以低于鳍型有源区FA和FB的最上表面FT的竖直水平LV3。而且，下部鳍隔离绝缘部分LS的最上表面的竖直水平LVO可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3，并且可以低于栅极结构GS的最上表面的竖直水平LVG。在一些示例实施方式中，下部鳍隔离绝缘部分LS的最上表面的竖直水平LVO可以低于多个第二绝缘间隔物122的最上端的竖直水平。
上部鳍隔离绝缘部分US的最下表面的竖直水平LVO可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3，并可以低于栅极结构GS的最上表面的竖直水平LV3。而且，上部鳍隔离绝缘部分US的最上表面的竖直水平LV4可以高于栅极结构GS的最上表面的竖直水平LVG。在一些示例实施方式中，上部鳍隔离绝缘部分US的最下表面的竖直水平LVO可以低于多个第二绝缘间隔物122的最上端的竖直水平。
在一些示例实施方式中，上部鳍隔离绝缘部分US的顶表面、多个栅极绝缘覆盖层140的顶表面、多个第一绝缘间隔物120的顶表面和栅极间绝缘层128的顶表面可以是共面的。例如，上部鳍隔离绝缘部分US的顶表面、多个栅极绝缘覆盖层140的顶表面、多个第一绝缘间隔物120的顶表面和栅极间绝缘层128的顶表面可以具有基本相同的竖直水平LV4。
鳍隔离绝缘部分FS在第一方向(X方向)上的宽度W1可以大于栅极结构GS的宽度W2。详细地，下部鳍隔离绝缘部分LS的宽度可以与栅极结构GS的宽度W2基本相同或者小于栅极结构GS的宽度W2，而上部鳍隔离绝缘部分US的上部的宽度W1可以大于栅极结构GS的宽度W2。
多个鳍型有源区FA和FB可以包括在两个相邻的鳍隔离绝缘部分FS外部沿第一方向(X方向)彼此平行地延伸的多个第一鳍型区FA和在这两个相邻的鳍隔离绝缘部分FS之间沿第一方向(X方向)彼此平行地延伸的多个第二鳍型区FB。
在形成鳍隔离绝缘部分FS的过程中，多个第一鳍型区FA和多个第二鳍型区FB可以与多个初步鳍型有源区(图3A和图3B的F2)分离。沿第一方向(X方向)以直线延伸的第一鳍型区FA和第二鳍型区FB可以在其间具有鳍隔离绝缘部分FS的情况下彼此间隔开。
多个鳍型有源区FA和FB可以包括在其间具有一对鳍隔离绝缘部分FS的情况下彼此间隔开的一对第一鳍型区FA以及在该对鳍隔离绝缘部分FS之间的一个第二鳍型区FB，该对第一鳍型区FA和第二鳍型区FB在第一方向(X方向)上以直线延伸。
多个栅极结构GS可以不在多个第二鳍型区FB上。因此，MOS晶体管可以不形成在多个第二鳍型区FB上。
多个栅极结构GS可以包括在第二方向(Y方向)上以直线延伸并且在其间有鳍隔离绝缘部分FS的情况下在第二方向(Y方向)上彼此间隔开的一对虚设栅极结构DGS。
多个第一绝缘间隔物120可以覆盖多个栅极结构GS的两个侧壁。多个第一绝缘间隔物120可以与多个栅极结构GS一起在第二方向(Y方向)上以线形延伸。多个第二绝缘间隔物122可以覆盖多个鳍隔离绝缘部分FS的两个侧壁。多个第二绝缘间隔物122可以与多个鳍隔离绝缘部分FS一起在第二方向(Y方向)上以线形延伸。多个第一绝缘间隔物120和多个第二绝缘间隔物122可以包括硅氮化物层、SiOCN层、SiCN层或其组合。
多个第二绝缘间隔物122在垂直方向(Z方向)上的长度(例如，高度)可以与多个第一绝缘间隔物120在垂直方向(Z方向)上的长度不同。在一些示例实施方式中，多个第二绝缘间隔物122在垂直方向(Z方向)上的长度可以小于多个第一绝缘间隔物120在垂直方向(Z方向)上的长度。多个第二绝缘间隔物122的最上表面的竖直水平可以低于多个第一绝缘间隔物120的最上表面的竖直水平。多个第二绝缘间隔物122的最下表面的竖直水平可以等于多个第一绝缘间隔物120的最下表面的竖直水平。
图2A示出了鳍隔离绝缘部分FS的底表面是平坦的。然而，发明构思不限于此。在一些示例实施方式中，鳍隔离绝缘部分FS的底表面可以包括弯曲表面，该弯曲表面包括圆形的一部分或椭圆形的一部分。在其它实施方式中，鳍隔离绝缘部分FS的底表面可以包括非平坦表面，该非平坦表面具有朝向基板110急剧突出的点。
凹槽124R可以形成在栅极结构GS的两侧和在多个鳍型有源区FA和FB中的鳍隔离绝缘部分FS的两侧，并且多个凹槽124R可以形成在多个鳍型有源区FA和FB中的每一个中。多个凹槽124R可以填充有多个源极/漏极区124。多个源极/漏极区124可以位于多个鳍型有源区FA和FB上在栅极结构GS的两侧和鳍隔离绝缘部分FS的两侧。在一些示例实施方式中，多个源极/漏极区124可以具有嵌入的SiGe结构，该SiGe结构包括外延生长的多个SiGe层。多个SiGe层可以各自具有不同的Ge含量。在其它实施方式中，多个源极/漏极区124可以包括外延生长的Si层或外延生长的SiC层。
在一些示例实施方式中，多个源极/漏极区124可以被绝缘衬垫覆盖。绝缘衬垫可以共形地覆盖元件隔离层112、多个第一绝缘间隔物120和多个源极/漏极区124。绝缘衬垫可以包括硅氮化物层。
源极/漏极区124和栅极结构GS可以通过插置在源极/漏极区124与栅极结构GS之间的第一绝缘间隔物120彼此绝缘。源极/漏极区124可以包括从包括在凹槽124R的内壁中的鳍型有源区FA和FB的表面外延生长的半导体层。在一些示例实施方式中，源极/漏极区124可以具有顶表面，其竖直水平近似等于鳍型有源区FA和FB的最上表面FT的竖直水平LV3。然而，不限于此。本说明书中使用的术语“竖直水平”表示在垂直于基板110的第一表面110M的方向(例如，Z方向)上的长度。
栅极间绝缘层128可以插置在多个栅极结构GS之间。多个源极/漏极区124可以被栅极间绝缘层128覆盖。绝缘衬垫可以插置在多个源极/漏极区124与栅极间绝缘层128之间。栅极间绝缘层128可以包括硅氧化物层。
绝缘薄层150可以在基板110上平行于基板110的第一表面110M延伸。绝缘薄层150可以覆盖多个栅极结构GS、多个栅极绝缘覆盖层140、多个第一绝缘间隔物120、多个上部鳍隔离绝缘部分US和栅极间绝缘层128。绝缘薄层150可以包括硅氧化物层、硅氮化物层、多晶硅层或其组合。层间绝缘层160可以形成在绝缘薄层150上。层间绝缘层160可以包括硅氧化物层、硅氮化物层或其组合。
多个接触插塞184可以穿透层间绝缘层160、绝缘薄层150和栅极间绝缘层128，并且可以连接到多个源极/漏极区124。在一些示例实施方式中，多个导电的阻挡层182可以覆盖多个接触插塞184的侧表面和底表面。在一些示例实施方式中，多个导电的阻挡层182和多个接触插塞184可以延伸到多个源极/漏极区124中。
多个接触插塞184可以包括例如金属材料(诸如W、Cu、Ti、Ta、Ru、Mn或Co)、金属氮化物(诸如TiN、TaN、CoN或WN)或金属合金(诸如钴钨磷化物(CoWP)、钴钨硼(CoWB)或钴钨硼磷化物(CoWBP))。多个导电的阻挡层182可以包括例如Ti、Ta、TiN、TaN或其组合。
在一些示例实施方式中，硅化物层可以在导电的阻挡层182与源极/漏极区124之间。硅化物层可以包括例如钨硅化物(WSi)、钛硅化物(TiSi)、钴硅化物(CoSi)或镍硅化物(NiSi)。在一些示例实施方式中，硅化物层可以包括在导电的阻挡层182中包括的金属元素的金属硅化物。例如，当导电的阻挡层182包括Ti、TiN或其组合时，硅化物层可以包括TiSi。
虽然未另外示出，但是可以进一步形成穿透层间绝缘层160、绝缘薄层150和栅极绝缘覆盖层140并且连接到多个栅极线GL的多个栅极接触。在一些示例实施方式中，多个栅极接触的侧表面和底表面可以被多个导电栅极阻挡层覆盖。导电栅极阻挡层和栅极接触可以分别具有与导电的阻挡层182和接触插塞184基本相同的结构。在一些示例实施方式中，导电栅极阻挡层和栅极接触可以分别与导电的阻挡层182和接触插塞184同时形成。然而，不限于此，导电栅极阻挡层和栅极接触可以分别与导电的阻挡层182和接触插塞184分开地形成。
根据发明构思的集成电路器件100可以通过使用鳍隔离绝缘部分FS来增强或降低包括在集成电路器件100中的MOS晶体管的特性，以获得导线和接触之间的绝缘距离。因此，可以在不增加集成电路器件100的面积的情况下实现高操作速度和操作精度。
图2B是用于描述根据一些示例实施方式的集成电路器件100a的剖视图。详细地，图2B是沿图1的线X1-X1'截取的示例剖视图。图1和图2A中相同的附图标记表示图2B中的相同元件，并且将省略它们的详细描述。
参考图2B，集成电路器件100a可以具有与图2A的集成电路器件100基本相同的结构。然而，在集成电路器件100a中，可以不形成连接到填充多个第二鳍型区FB的多个凹槽124R的多个源极/漏极区124的多个导电的阻挡层182和多个接触插塞184。多个导电的阻挡层182和多个接触插塞184可以形成为连接到填充多个第一鳍型区FA的多个凹槽124R的多个源极/漏极区124。
因此，多个导电的阻挡层182和多个接触插塞184可以垂直地交叠多个第一鳍型区FA，而不垂直地交叠多个第二鳍型区FB。
图2C是用于描述根据一些示例实施方式的集成电路器件100b的剖视图。详细地，图2C是沿图1的线X1-X1'截取的示例剖视图。图1和图2A中相同的附图标记表示图2C中的相同元件，因此，将省略它们的详细描述。
参考图2C，集成电路器件100b可以具有与图2A的集成电路器件100基本相同的结构。然而，集成电路器件100b可以包括多个鳍隔离绝缘部分FSa，而不是所述多个鳍隔离绝缘部分FS。
多个鳍隔离绝缘部分FSa可以包括下部鳍隔离绝缘部分LSa和位于下部鳍隔离绝缘部分LSa上的上部鳍隔离绝缘部分US。上部鳍隔离绝缘部分US和下部鳍隔离绝缘部分LSa可以在垂直方向(Z方向)上相对于彼此对准。上部鳍隔离绝缘部分US的底表面和下部鳍隔离绝缘部分LSa的顶表面可以彼此接触。栅极结构GS可以不位于下部鳍隔离绝缘部分LSa的向上方向(Z方向)上，并且上部鳍隔离绝缘部分US可以位于下部鳍隔离绝缘部分LSa的向上方向(Z方向)上。下部鳍隔离绝缘部分LSa可以形成为具有包括单一材料例如均质材料的单层结构。
在一些示例实施方式中，下部鳍隔离绝缘部分LSa可以包括氮化物层，并且上部鳍隔离绝缘部分US可以包括氧化物层。
下部鳍隔离绝缘部分LSa可以位于基板110的第一表面110M的竖直水平LV1与栅极结构GS的最上表面的竖直水平LVG之间。下部鳍隔离绝缘部分LSa的最下表面的竖直水平LV2可以高于基板110的第一表面110M的竖直水平LV1并且低于鳍型有源区FA和FB的最上表面FT的竖直水平LV3。而且，下部鳍隔离绝缘部分LSa的最上表面的竖直水平LVOa可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3并且低于栅极结构GS的最上表面的竖直水平LVG。
上部鳍隔离绝缘部分US的最下表面的竖直水平LVO可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3并且低于栅极结构GS的最上表面的竖直水平LVG。而且，上部鳍隔离绝缘部分US的最上表面的竖直水平LV4可以高于栅极结构GS的最上表面的竖直水平LVG。
图2D是用于描述根据一些示例实施方式的集成电路器件100c的剖视图。详细地，图2D是沿图1的线X1-X1'截取的示例剖视图。图1和图2C中相同的附图标记表示图2D中的相同元件，因此，将省略它们的详细描述。
参考图2D，集成电路器件100c可以具有与图2C的集成电路器件100b基本相同的结构。然而，在集成电路器件100c中，可以不形成连接到填充多个第二鳍型区FB的多个凹槽124R的多个源极/漏极区124的多个导电的阻挡层182和多个接触插塞184。例如，多个导电的阻挡层182和多个接触插塞184可以形成为连接到填充多个第一鳍型区FA的多个凹槽124R的多个源极/漏极区124。
图3A和图3B至图16A、图16B和图16C是用于描述根据一些示例实施方式的制造集成电路器件的方法以工艺次序示出的剖视图。详细地，图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A、图13A、图14A、图15A和图16A是对应于图1的线X1-X1'的部分的剖视图，图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B、图13B、图14B、图15B和图16B是对应于图1的线Y1-Y1'的部分的剖视图，图6C、图7C、图8C、图9C、图10C、图11C、图12C、图13C、图14C、图15C和图16C是对应于图1的线Y2-Y2'的部分的剖视图。
一起参考图3A和图3B，可以通过蚀刻基板110的一部分形成从基板110的第一表面110M朝向上方向(Z方向)突出并在第一方向(X方向)上延伸的多个初级鳍型有源区F2，并且可以形成覆盖多个初级鳍型有源区F2中的每一个的两个下侧壁的元件隔离层112。多个初级鳍型有源区F2可以在元件区RX中突出到元件隔离层12的顶表面之上。
可以通过蚀刻元件隔离层112的一部分和基板110的一部分形成限定元件区RX的深沟槽DT，并且可以通过用绝缘层填充深沟槽DT形成元件隔离区DTA。在一些示例实施方式中，在形成多个初级鳍型有源区F2和深沟槽DT之后，可以一起形成元件隔离层112和元件隔离区DTA。
关于图3A和图3B，对应于图1的线Y2-Y2'的部分可以与图3B基本相同，因此，将不示出该部分。
参考图4A和图4B，延伸以与多个初级鳍型有源区F2交叉的多个虚设栅极结构DGS可以形成在多个初级鳍型有源区F2上。多个虚设栅极结构DGS中的每一个可以包括顺序地堆叠在初级鳍型有源区F2上的虚设栅极绝缘层D12、虚设栅极线D14和虚设栅极绝缘覆盖层D16。虚设栅极绝缘层D12可以包括硅氧化物。虚设栅极线D14可以包括多晶硅。虚设栅极绝缘覆盖层D16可以包括硅氮化物。
第一绝缘间隔物120可以形成在虚设栅极结构DGS的两个侧壁处。第一绝缘间隔物120可以通过使用ALD工艺或CVD工艺形成。
可以通过蚀刻初级鳍型有源区F2的部分在虚设栅极结构DGS的两侧形成多个凹槽124R，并且可以通过在多个凹槽124R中执行外延生长工艺形成半导体层而形成多个源极/漏极区124。
可以形成填充由多个源极/漏极区124、多个虚设栅极结构DGS和第一绝缘间隔物120限定的空间的栅极间绝缘层128。为了形成栅极间绝缘层128，可以形成以足够的厚度覆盖包括多个虚设栅极结构DGS和多个源极/漏极区124的结构的绝缘层，然后，可以平坦化该绝缘层以暴露虚设栅极绝缘覆盖层D16的顶表面。
在一些示例实施方式中，可以首先形成共形地覆盖多个源极/漏极区124、多个虚设栅极结构DGS和第一绝缘间隔物120的绝缘衬垫，然后，可以在绝缘衬垫上形成栅极间绝缘层128。
关于图4A和图4B，对应于图1的线Y2-Y2'的部分可以与图4B基本相同，因此，将不示出该部分。
一起参考图5A和图5B，可以执行平坦化工艺，由此去除第一绝缘间隔物120的一部分、栅极间绝缘层128的一部分和虚设栅极绝缘覆盖层(图4A和4B的D16)，从而暴露虚设栅极线D14的顶表面。在一些示例实施方式中，在图4A和图4B中示出的工艺以及图5A和图5B中示出的工艺可以通过原位工艺顺序地执行。
关于图5A和图5B，对应于图1的线Y2-Y2'的部分可以与图5B基本相同，因此，将不示出该部分。
一起参考图6A至图6C，可以在由参考图5A和图5B描述的方法产生的物体上形成掩模图案M1。掩模图案M1可以具有暴露虚设栅极线D14的一部分的开口OP。开口OP的平面形状可以包括图1中示出的两个相邻的鳍隔离绝缘部分FS，并且可以对应于不包括多个栅极结构GS的平面形状。掩模图案M1可以具有多个硬掩模层的堆叠的多层结构。在一些示例实施方式中，掩模图案M1可以包括硅氮化物层、硅氧化物层、多晶硅层、含碳层或其组合。含碳层可以包括旋涂硬掩模(SOH)材料。SOH材料可以包括烃化合物或其衍生物，该烃具有基于SOH材料的总重量的约85重量百分比至约99重量百分比的相对高的碳含量。
在一些示例实施方式中，两个虚设栅极线D14中的每一个的一部分可以通过开口OP暴露。
一起参考图7A至图7C，可以通过使用参考图6A至图6C描述的方法形成的掩模图案M1作为蚀刻掩模来蚀刻和去除虚设栅极线D14的由开口OP暴露的部分，并且可以去除作为其结果暴露的虚设栅极绝缘层D12。然后，可以蚀刻在去除虚设栅极绝缘层D12之后由开口OP暴露的多个初级鳍型有源区F2，以形成多个鳍隔离空间SS。鳍隔离空间SS可以具有有竖直水平LV2的底表面，该竖直水平LV2高于基板110的第一表面110M的竖直水平LV1。
通过去除一部分初级鳍型有源区F2形成的鳍隔离空间SS，初级鳍型有源区F2可以被划分为第一鳍型区FA和第二鳍型区FB。
在虚设栅极线D14、虚设栅极绝缘层D12和初级鳍型有源区F2被蚀刻以形成鳍隔离空间SS的同时，第一绝缘间隔物120的被开口OP暴露而被一起蚀刻的部分可以被去除。因此，可以形成低于第一绝缘间隔物120的多个第二绝缘间隔物122。
一起参考图8A至图8C，可以形成共形地覆盖鳍隔离空间SS的内表面的第一下部鳍隔离绝缘层172。第一下部鳍隔离绝缘层172还可以覆盖掩模图案M1的顶表面和侧表面。第一下部鳍隔离绝缘层172可以包括例如氮化物层。第一下部鳍隔离绝缘层172可以通过使用ALD工艺形成。
一起参考图9A至图9C，可以形成覆盖第一下部鳍隔离绝缘层172的第二下部鳍隔离绝缘层174。第二下部鳍隔离绝缘层174可以包括例如氧化物层。第二下部鳍隔离绝缘层174可以通过使用ALD工艺或CVD工艺形成。第二下部鳍隔离绝缘层174可以形成为填充鳍隔离空间SS的下部分。第一下部鳍隔离绝缘层172和第二下部鳍隔离绝缘层174可以从鳍隔离空间SS的底表面填充至至少高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3的水平。
一起参考图10A至图10C，可以从由参考图9A至图9C描述的方法产生的物体去除第二下部鳍隔离绝缘层174的上部分和第一下部鳍隔离绝缘层172的上部分，以形成下部鳍隔离绝缘部分LS。为了形成下部鳍隔离绝缘部分LS，可以通过使用湿法蚀刻工艺和干法蚀刻工艺去除第二下部鳍隔离绝缘层174的上部分和第一下部鳍隔离绝缘层172的上部分。
下部鳍隔离绝缘部分LS可以包括芯绝缘图案LSC和覆盖芯绝缘图案LSC的侧表面和底表面的外围绝缘图案LSO。芯绝缘图案LSC和外围绝缘图案LSO可以分别是第二下部鳍隔离绝缘层174的一部分和第一下部鳍隔离绝缘层172的一部分。
下部鳍隔离绝缘部分LS的最上表面的竖直水平LVO可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3，并且可以低于虚设栅极线D14的最上表面的竖直水平。
一起参考图11A至图11C，可以在由参考图10A至图10C描述的方法产生的物体上形成填充所有的鳍隔离空间SS的间隙填充绝缘层192。间隙填充绝缘层192可以填充所有的鳍隔离空间SS，并且可以形成为覆盖掩模图案M1的顶表面和侧表面。
一起参考图12A至图12C，可以平坦化通过参考图11A至图11C描述的方法形成的间隙填充绝缘层192，以暴露虚设栅极线D14的顶表面，以便形成上部鳍隔离绝缘部分US，其是间隙填充绝缘层192的一部分。上部鳍隔离绝缘部分US和下部鳍隔离绝缘部分LS可以被包括在鳍隔离绝缘部分FS中。
一起参考图13A至图13C，可以从由参考图12A至图12C描述的方法产生的物体去除虚设栅极线D14和虚设栅极绝缘层D12，从而形成多个栅极结构空间GA。第一绝缘间隔物120、鳍型有源区FA和FB以及元件隔离层112可以通过栅极结构空间GA暴露。
一起参考图14A至图14C，可以在所述多个栅极结构空间GA中(参考图13A到13C)形成栅极绝缘层132和栅极导电层134。在形成栅极绝缘层132之前，还可以在鳍型有源区FA和FB的表面上形成界面层，该表面被多个栅极结构空间GA暴露。界面层可以通过氧化鳍型有源区FA和FB的一部分来获得，该部分在多个栅极结构空间GA中暴露。
栅极绝缘层132和栅极导电层134可以形成为填充栅极结构空间GA的内部空间并覆盖栅极间绝缘层128的顶表面。栅极绝缘层132和栅极导电层134中的每一个可以通过ALD工艺、CVD工艺、物理气相沉积(PVD)工艺、金属有机ALD(MOALD)工艺或金属有机CVD(MOCVD)形成。
一起参考图15A至图15C，可以去除栅极绝缘层132和栅极导电层134(参考图14A至图14C)的不必要部分以暴露栅极间绝缘层128的顶表面，并且可以进一步去除栅极绝缘层132的上部分和栅极导电层134的上部分，以形成覆盖空间CS。栅极导电层134的保留在栅极结构空间GA(参考图13A至图13C)中的部分可以形成栅极线GL。
为了去除栅极导电层134的该部分，可以使用包括在栅极导电层134中的金属层和/或含金属层与包括在栅极间绝缘层128中的硅氧化物层之间的蚀刻选择性。例如，可以使用含BCl3的蚀刻气体，并且可以控制含有BCl3的蚀刻气体中的BCl3的含量，以抑制硅氧化物层的蚀刻并相对地增加金属层和/或含金属层的蚀刻速度。含有BCl3的蚀刻气体可以包括BCl3或BCl3和SiCl4的组合。在通过蚀刻去除栅极导电层134的同时，可以一起去除具有相对小的厚度的栅极绝缘层132。
参考图16A至图16C，可以形成填充通过参考图15A至图15C描述的方法形成的多个覆盖空间CS的多个栅极绝缘覆盖层140。
为了形成栅极绝缘覆盖层140，可以在基板110上形成具有足以填充多个覆盖空间CS的厚度的覆盖绝缘层，然后，可以去除覆盖绝缘层的不必要部分以暴露栅极间绝缘层128的顶表面。栅极绝缘覆盖层140可以包括硅氮化物层。
此后，如图2A所示，可以在由参考图16A至图16C描述的方法产生的物体上形成绝缘薄层150和覆盖绝缘薄层150的层间绝缘层160，并且可以形成穿透层间绝缘层160、绝缘薄层150和栅极间绝缘层128并连接到多个源极/漏极区124的多个导电的阻挡层182和多个接触插塞184，以形成集成电路器件100。
这里，通过将多个导电的阻挡层182和多个接触插塞184连接到填充多个第一鳍型区FA的多个凹槽124R的多个源极/漏极区124，并且通过不将多个导电的阻挡层182和多个接触插塞184连接到填充多个第二鳍型区FB的多个凹槽124R的多个源极/漏极区124，可以形成图2B中所示的集成电路器件100a。
在一些示例实施方式中，绝缘薄层150可以包括与栅极绝缘覆盖层140不同的材料。例如，当栅极绝缘覆盖层140包括硅氮化物层时，绝缘薄层150可以包括硅氧化物层。然而，发明构思不限于此。例如，绝缘薄层150可以包括硅氧化物层、硅氮化物层、多晶硅层或其组合。层间绝缘层160可以包括硅氧化物层、硅氮化物层或其组合。
图17A至图17D是按照工艺次序示出的剖视图，用于描述根据一些示例实施方式的制造集成电路器件的方法。详细地，图17A至图17D中的每一个是与图1的线X1-X1'对应的部分的剖视图，用于描述制造图2C的集成电路器件100b的方法。
参考图17A，可以形成共形地覆盖通过参考图7A至图7C描述的方法形成的鳍隔离空间SS的内表面的下部鳍隔离绝缘层176。下部鳍隔离绝缘层176可以覆盖掩模图案M1的顶表面和侧表面二者。下部鳍隔离绝缘层176可以包括例如氮化物层或氧化物层。下部鳍隔离绝缘层176可以通过使用ALD工艺形成。下部鳍隔离绝缘层176可以形成为填充鳍隔离空间SS的下部分。下部鳍隔离绝缘层176可以从鳍隔离空间SS的底表面填充至至少高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3的水平。
参考图17B，可以去除通过参考图17A描述的方法形成的下部鳍隔离绝缘层176的上部分，以形成下部鳍隔离绝缘部分LSa。为了形成下部鳍隔离绝缘部分LSa，可以通过使用湿法蚀刻工艺和干法蚀刻工艺去除下部鳍隔离绝缘层176的上部分。
下部鳍隔离绝缘部分LSa的最上表面的竖直水平LVOa可以高于鳍型有源区FA和FB的最上表面FT的竖直水平LV3，并且可以低于虚设栅极线D14的最上表面的竖直水平。
参考图17C，可以在由参考图17B描述的方法得到的物体上形成填充所有的鳍隔离空间SS的间隙填充绝缘层192。间隙填充绝缘层192可以形成为填充所有的鳍隔离空间SS并且覆盖掩模图案M1的顶表面和侧表面。
一起参考图17D，可以平坦化通过参考图17C描述的方法形成的间隙填充绝缘层192，以暴露虚设栅极线D14的顶表面，从而形成上部鳍隔离绝缘部分US。上部鳍隔离绝缘部分US和下部鳍隔离绝缘部分LSa可以一起形成鳍隔离绝缘部分FSa。
此后，可以执行参考图13A至图16C描述的制造方法，以形成图2C所示的集成电路器件100b或图2D所示的集成电路器件100c。
图18A至图18C是用于描述根据一些示例实施方式的集成电路器件的剖视图。图1至图2D中相同的附图标记表示图18A至图18C中的相同的元件，因此，将省略它们的详细描述。
参考图18A，集成电路器件1可以具有第一区域I和第二区域II。
具有其中不同导电类型的沟道沿多个栅极结构GS形成的3d结构的MOS晶体管可以形成于在第一区域I中的多个鳍型有源区FA-I和FB-I以及在第二区域II中的多个鳍型有源区FA-II和FB-II中的每一个中。例如，可以沿着第一区域I中的多个栅极结构GS形成多个pMOS晶体管，并且可以沿着第二区域II中的多个栅极结构GS形成多个nMOS晶体管。或者，例如，可以沿着第一区域I中的多个栅极结构GS形成多个nMOS晶体管，并且可以沿着第二区域II中的多个栅极结构GS形成多个pMOS晶体管。
在一些示例实施方式中，具有其中相同导电类型的沟道沿着多个栅极结构GS形成的3d结构的MOS晶体管(其中相同导电类型沟道具有不同的特性)可以形成在第一区域I中的多个鳍型有源区FA-I和FB-I以及在第二区域II中的多个鳍型有源区FA-II和FB-II中的每一个中。或者，例如，沿着第一区域I中的多个栅极结构GS形成的多个MOS晶体管和沿着第二区域II中的多个栅极结构GS形成的多个MOS晶体管可以具有彼此不同的操作速度和/或彼此不同的工作电压。
形成在第一区域I中的鳍隔离绝缘部分FS的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSa的至少一部分可以具有彼此不同的材料。形成在第一区域I中的鳍隔离绝缘部分FS可以包括下部鳍隔离绝缘部分LS和在下部鳍隔离绝缘部分LS上的上部鳍隔离绝缘部分US。形成在第二区域II中的鳍隔离绝缘部分FSa可以包括下部鳍隔离绝缘部分LSa和在下部鳍隔离绝缘部分LSa上的上部鳍隔离绝缘部分US。
在第一区域I中的鳍隔离绝缘部分FS、下部鳍隔离绝缘部分LS和上部鳍隔离绝缘部分US可以分别被称为第一鳍隔离绝缘部分、第一下部鳍隔离绝缘部分和第一上部鳍隔离绝缘部分。在第二区域II中的鳍隔离绝缘部分FSa、下部鳍隔离绝缘部分LSa和上部鳍隔离绝缘部分US可以分别被称为第二鳍隔离绝缘部分、第二下部鳍隔离绝缘部分和第二上部鳍隔离绝缘部分。
在一些示例实施方式中，在第一区域I和第二区域II的每一个中形成的上部鳍隔离绝缘部分US可以包括氧化物层。
形成在第一区域I中的下部鳍隔离绝缘部分LS可以包括芯绝缘图案LSC和覆盖芯绝缘图案LSC的侧表面和底表面的外围绝缘图案LSO。形成在第一区域I中的芯绝缘图案LSC和外围绝缘图案LSO可以包括彼此不同的材料。在一些示例实施方式中，外围绝缘图案LSO可以包括氮化物层，芯绝缘图案LSC可以包括氧化物层。
形成在第二区域II中的下部鳍隔离绝缘部分LSa可以包括与形成在第一区域I中的外围绝缘图案LSO相同的材料。在一些示例实施方式中，形成在第一区域I中的外围绝缘图案LSO和形成在第二区域II中的下部鳍隔离绝缘部分LSa可以包括氮化物层。
在根据本发明构思的集成电路器件1中，形成在第一区域I中的鳍隔离绝缘部分FS的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSa的至少一部分可以具有彼此不同的材料。因此，集成电路器件1可以分别且精细地控制形成在第一区域I中的MOS晶体管和形成在第二区域II中的MOS晶体管的特性，因此，可以提供改善的性能。
参考图18B，集成电路器件1a可以具有第一区域I和第二区域II。形成在第一区域I中的鳍隔离绝缘部分FS的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSb的至少一部分可以具有彼此不同的材料。
形成在第一区域I中的鳍隔离绝缘部分FS可以包括下部鳍隔离绝缘部分LS和在下部鳍隔离绝缘部分LS上的上部鳍隔离绝缘部分US。形成在第二区域II中的鳍隔离绝缘部分FSb可以包括下部鳍隔离绝缘部分LSb和在下部鳍隔离绝缘部分LSb上的上部鳍隔离绝缘部分US。
在一些示例实施方式中，在第一区域I和第二区域II的每一个中形成的上部鳍隔离绝缘部分US可以包括氧化物层。
形成在第一区域I中的下部鳍隔离绝缘部分LS可以包括芯绝缘图案LSC和覆盖芯绝缘图案LSC的侧表面和底表面的外围绝缘图案LSO。
形成在第二区域II中的下部鳍隔离绝缘部分LSb可以包括与形成在第一区域I中的芯绝缘图案LSC相同的材料。在一些示例实施方式中，形成在第一区域I中的芯绝缘图案LSC和形成在第二区域II中的下部鳍隔离绝缘部分LSb可以包括氧化物层。
在根据发明构思的集成电路器件1a中，形成在第一区域I中的鳍隔离绝缘部分FS的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSb的至少一部分可以具有彼此不同的材料。因此，集成电路器件1a可以分别且精细地控制形成在第一区域I中的MOS晶体管和形成在第二区域II中的MOS晶体管的特性，因此，可以提供改善的性能。
参考图18C，集成电路器件1b可以具有第一区域I和第二区域II。形成在第一区域I中的鳍隔离绝缘部分FSa的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSb的至少一部分可以具有彼此不同的材料。
形成在第一区域I中的鳍隔离绝缘部分FSa可以包括下部鳍隔离绝缘部分LSa和在下部鳍隔离绝缘部分LSa上的上部鳍隔离绝缘部分US。形成在第二区域II中的鳍隔离绝缘部分FSb可以包括下部鳍隔离绝缘部分LSb和在下部鳍隔离绝缘部分LSb上的上部鳍隔离绝缘部分US。
在一些示例实施方式中，形成在第一区域I和第二区域II的每一个中的上部鳍隔离绝缘部分US可以包括氧化物层。
形成在第一区域I中的下部鳍隔离绝缘部分LSa和形成在第二区域II中的下部鳍隔离绝缘部分LSb可以包括彼此不同的材料。在一些示例实施方式中，形成在第一区域I中的下部鳍隔离绝缘部分LSa可以包括氮化物层，形成在第二区域II中的下部鳍隔离绝缘部分LSb可以包括氧化物层。
在根据发明构思的集成电路器件1b中，形成在第一区域I中的鳍隔离绝缘部分FSa的至少一部分和形成在第二区域II中的鳍隔离绝缘部分FSb的至少一部分可以具有彼此不同的材料。因此，集成电路器件1b可以分别且精细地控制形成在第一区域I中的MOS晶体管和形成在第二区域II中的MOS晶体管的特性，因此，可以提供改善的性能。
图18A至图18C示出了多个导电的阻挡层182和多个接触插塞184连接到填充多个第一鳍型区FA的多个凹槽124R的多个源极/漏极区124并且连接到填充多个第二鳍型区FB的多个凹槽124R的多个源极/漏极区124。然而，发明构思不限于此。如图2B和图2D所示，多个导电的阻挡层182和多个接触插塞184可以形成为连接到填充多个第一鳍型区FA的多个凹槽124R的多个源极/漏极区124且形成为不连接到填充多个第二鳍型区FB的多个凹槽124R的多个源极/漏极区124。
图19是用于描述根据一些示例实施方式的集成电路器件2的平面布局图。
参考图19，集成电路器件2可以具有第一区域I和第二区域II。
两个鳍隔离绝缘部分FS-I可以在第一区域I的元件区RX-I中的栅极结构GS之间。两个栅极结构GS和两个鳍隔离绝缘部分FS-I可以在第一方向(X方向)上交替地在第一区域I的元件区RX-I中。
两个鳍隔离绝缘部分FS-II可以在第一区域II的元件区RX-II中的栅极结构GS之间。一个栅极结构GS和一个鳍隔离绝缘部分FS-II可以在第一方向(X方向)上交替地在第二区域II的元件区RX-II中。
第一区域I中的鳍隔离绝缘部分FS-I可以向与鳍隔离绝缘部分FS-I的一侧相邻的鳍型有源区FA-I和FB-I的沟道区施加拉应力或压应力，第二区域II中的鳍隔离绝缘部分FS-II可以向与鳍隔离绝缘部分FS-II的两侧相邻的鳍型有源区FA-II的沟道区施加拉应力或压应力。因此，由鳍隔离绝缘部分FS-I施加到沿第一区域I中的栅极结构GS形成的多个MOS晶体管的应力可以不同于由鳍隔离绝缘部分FS-II施加到沿第二区域II中的栅极结构GS形成的多个MOS晶体管的应力。
因此，集成电路器件2可以分别且精细地控制形成在第一区域I中的MOS晶体管和形成在第二区域II中的MOS晶体管的特性，因此，可以提供改善的性能。
虽然已经参考发明构思的一些示例实施方式具体示出和描述了发明构思，但是将理解，在不脱离权利要求的精神和范围的情况下，可以在形式和细节上进行各种改变。
本申请要求于2018年4月11日在韩国知识产权局提交的韩国专利申请第10-2018-0042197的权益，其公开内容通过引用整体合并于此。

Claims (20)

1.一种集成电路器件，包括：
基板；
从所述基板突出的多个鳍型有源区，所述多个鳍型有源区在第一方向上彼此平行地延伸；和
在交叉所述第一方向的第二方向上在所述基板上延伸的多个栅极结构和多个鳍隔离绝缘部分，所述多个栅极结构和所述多个鳍隔离绝缘部分在所述第一方向上具有恒定的节距，
其中，所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在一对栅极结构的第一元件与所述一对栅极结构的第二元件之间，所述一对栅极结构来自所述多个栅极结构当中，和
所述多个鳍型有源区包括多个第一鳍型区和多个第二鳍型区，其中所述多个第一鳍型区当中的一对第一鳍型区在所述第一方向上以直线延伸，并且在其间具有所述一对鳍隔离绝缘部分的情况下彼此间隔开，并且所述多个第二鳍型区中的一个在所述一对鳍隔离绝缘部分之间。
2.根据权利要求1所述的集成电路器件，其中
所述多个鳍隔离绝缘部分中的每一个包括下部鳍隔离绝缘部分和在所述下部鳍隔离绝缘部分上的上部鳍隔离绝缘部分，其中所述下部鳍隔离绝缘部分在竖直方向上与所述上部鳍隔离绝缘部分对准，并且所述下部鳍隔离绝缘部分的至少一部分和所述上部鳍隔离绝缘部分的至少一部分具有彼此不同的材料，以及
所述上部鳍隔离绝缘部分的至少一部分在所述第一方向上的宽度大于所述多个栅极结构在所述第一方向上的宽度。
3.根据权利要求2所述的集成电路器件，其中所述下部鳍隔离绝缘部分的最下表面的竖直水平低于所述多个鳍型有源区的最上表面的竖直水平，并且所述下部鳍隔离绝缘部分的最上表面的竖直水平低于所述多个栅极结构的最上表面的竖直水平。
4.根据权利要求2所述的集成电路器件，其中所述下部鳍隔离绝缘部分包括：
芯绝缘图案，和
外围绝缘图案，覆盖所述芯绝缘图案的侧表面和底表面。
5.根据权利要求4所述的集成电路器件，其中所述芯绝缘图案包括氧化物层，所述外围绝缘图案包括氮化物层。
6.根据权利要求2所述的集成电路器件，其中所述下部鳍隔离绝缘部分包括单一材料。
7.根据权利要求1所述的集成电路器件，还包括：
多个第一绝缘间隔物，覆盖所述多个栅极结构的两个侧壁；和
多个第二绝缘间隔物，覆盖所述多个鳍隔离绝缘部分的两个侧壁，
其中所述多个第二绝缘间隔物的最上表面在比所述多个第一绝缘间隔物的最上表面低的竖直水平处。
8.根据权利要求1所述的集成电路器件，其中所述多个栅极结构包括在所述第二方向上以直线延伸且其间具有所述多个鳍隔离绝缘部分的一对虚设栅极结构。
9.根据权利要求1所述的集成电路器件，其中所述多个鳍隔离绝缘部分的最上表面在比所述多个栅极结构的最上表面高的竖直水平处。
10.根据权利要求9所述的集成电路器件，还包括：
覆盖所述多个栅极结构的顶表面的多个栅极绝缘覆盖层，
其中所述多个栅极绝缘覆盖层的最上表面和所述多个鳍隔离绝缘部分的最上表面具有相同的竖直水平。
11.根据权利要求1所述的集成电路器件，还包括：
多个源极/漏极区，在所述多个栅极结构的两侧和所述多个鳍隔离绝缘部分的两侧的所述多个鳍型有源区上；和
连接到所述多个源极/漏极区的多个接触插塞。
12.根据权利要求11所述的集成电路器件，其中所述多个接触插塞与所述多个第一鳍型区竖直地交叠，并且不与所述多个第二鳍型区竖直地交叠。
13.一种集成电路器件，包括：
基板；
从所述基板突出的多个鳍型有源区，所述多个鳍型有源区具有第一区域和第二区域，所述多个鳍型有源区在第一方向上彼此平行地延伸；和
在交叉所述第一方向的第二方向上在所述基板上延伸的多个栅极结构和多个鳍隔离绝缘部分，所述多个栅极结构和所述多个鳍隔离绝缘部分在所述第一方向上具有恒定的节距，
其中所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在所述多个栅极结构当中的一对栅极结构的第一元件和第二元件之间，以及
所述多个鳍隔离绝缘部分包括在所述第一区域中的第一鳍隔离绝缘部分和在所述第二区域中的第二鳍隔离绝缘部分，其中所述第一鳍隔离绝缘部分的至少一部分具有与所述第二鳍隔离绝缘部分的至少一部分不同的材料。
14.根据权利要求13的集成电路器件，其中
所述第一鳍隔离绝缘部分包括第一下部鳍隔离绝缘部分和在所述第一下部鳍隔离绝缘部分上的第一上部鳍隔离绝缘部分，
所述第二鳍隔离绝缘部分包括第二下部鳍隔离绝缘部分和在所述第二下部鳍隔离绝缘部分上的第二上部鳍隔离绝缘部分，
所述第一下部鳍隔离绝缘部分和所述第二下部鳍隔离绝缘部分中的每一个的最上表面在比所述多个鳍型有源区的最上表面高的竖直水平处，并且在比所述多个栅极结构低的竖直水平处，
所述第一上部鳍隔离绝缘部分具有与所述第二上部鳍隔离绝缘部分相同的材料，以及
所述第一下部鳍隔离绝缘部分的至少一部分具有与所述第二下部鳍隔离绝缘部分的至少一部分不同的材料。
15.如权利要求14所述的集成电路器件，其中，
所述第一下部鳍隔离绝缘部分包括芯绝缘图案和覆盖所述芯绝缘图案的侧表面和底表面的外围绝缘图案，所述芯绝缘图案具有与所述外围绝缘图案不同的材料，以及
所述第二下部鳍隔离绝缘部分由单一材料构成。
16.根据权利要求15所述的集成电路器件，其中所述外围绝缘图案和所述第二下部鳍隔离绝缘部分包括相同的材料。
17.根据权利要求15所述的集成电路器件，其中所述芯绝缘图案和所述第二下部鳍隔离绝缘部分包括相同的材料。
18.根据权利要求13所述的集成电路器件，还包括：
覆盖所述多个栅极结构的两个侧壁的多个第一绝缘间隔物；和
覆盖所述多个鳍隔离绝缘部分的两个侧壁的多个第二绝缘间隔物，
其中所述多个第二绝缘间隔物的最上表面在比所述多个第一绝缘间隔物的最上表面低的竖直水平处，以及
所述多个鳍隔离绝缘部分的最上表面在比所述多个栅极结构的最上表面高的竖直水平处。
19.一种集成电路器件，包括：
基板；
从所述基板突出的多个鳍型有源区，所述多个鳍型有源区具有第一区域和第二区域并且在第一方向上彼此平行地延伸；和
多个栅极结构和多个鳍隔离绝缘部分，在交叉所述第一方向的第二方向上在所述基板上延伸并在所述第一方向上具有恒定的节距，
其中所述多个鳍隔离绝缘部分当中的一对鳍隔离绝缘部分在所述多个栅极结构当中的在所述第一区域中的一对栅极结构的第一元件与第二元件之间，以及
所述多个鳍隔离绝缘部分当中的一个鳍隔离绝缘部分在所述多个栅极结构当中的在所述第二区域中的一对栅极结构之间。
20.根据权利要求19所述的集成电路器件，其中
所述多个鳍隔离绝缘部分的最下表面在比所述多个鳍型有源区的最上表面低的竖直水平处，以及
所述多个鳍隔离绝缘部分的最上表面在比所述多个栅极结构的最上表面高的竖直水平处。
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