CN110323181B - 一种半导体器件的制造方法 - Google Patents

一种半导体器件的制造方法 Download PDF

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CN110323181B
CN110323181B CN201910647015.XA CN201910647015A CN110323181B CN 110323181 B CN110323181 B CN 110323181B CN 201910647015 A CN201910647015 A CN 201910647015A CN 110323181 B CN110323181 B CN 110323181B
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layer
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hole
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bonding
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CN110323181A (zh
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谢岩
刘选军
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Abstract

本发明提供一种半导体器件的制造方法,提供衬底,衬底上形成有介质材料的覆盖层,覆盖层中形成有连线层,覆盖层上形成有待刻蚀层,待刻蚀层包括粘合层,在粘合层上形成曝光图案化膜层,曝光图案化膜层中形成有第一刻蚀孔图形,以曝光图案化膜层为掩蔽,在待刻蚀层中形成盲孔,对曝光图案化膜层进行修整,以扩大第一刻蚀孔图形而形成第二刻蚀孔图形,以修整后的曝光图案化膜层为掩蔽,进行待刻蚀层的第二刻蚀,以形成键合孔,并在键合孔中形成键合垫。也就是说,只需要进行一次光刻工艺,就可以通过刻蚀形成键合孔,相比于现有技术中的通过两块掩模版进行两次光刻工艺而言,减少光刻工艺的次数,降低了制造成本。

Description

一种半导体器件的制造方法
技术领域
本发明涉及半导体器件及其制造领域,特别涉及一种半导体器件的制造方法。
背景技术
目前,主要采用大马士革工艺形成键合垫(bonding pad),其是在形成键合孔之后,通过填充金属材料,来形成键合垫。在形成键合孔时,需要通过两块掩膜版和两次光刻及刻蚀工艺,来形成键合垫的底部过孔和上部过孔,其制造工艺的成本较高,因此,需要进一步的降低制造成本,提高生产率及生产竞争力。
发明内容
有鉴于此,本发明的目的在于提供一种半导体器件的制造方法,降低了制造成本。
为实现上述目的,本发明有如下技术方案:
本申请实施例提供了一种半导体器件的制造方法,包括:
提供衬底,所述衬底上形成有介质材料的覆盖层,所述覆盖层中形成有连线层,所述覆盖层上还形成有待刻蚀层,所述待刻蚀层包括粘合层;
在所述待刻蚀层上形成曝光图案化膜层并进行光刻工艺,以在所述曝光图案化膜层中形成第一刻蚀孔图形;
以所述曝光图案化膜层为掩蔽,进行所述待刻蚀层的第一刻蚀,以在所述待刻蚀层中形成盲孔;
进行所述曝光图案化膜层的修整,以扩大所述第一刻蚀孔图形而形成第二刻蚀孔图形;
以修整后的所述曝光图案化膜层为掩蔽,进行所述待刻蚀层的第二刻蚀,以形成键合孔,所述键合孔包括利用所述盲孔形成的贯通至所述连线层的底部过孔,以及在所述第二刻蚀孔图形下、所述底部过孔上的部分厚度的待刻蚀层中形成的上部过孔;
在所述键合孔中形成键合垫。
可选的,所述曝光图案化膜层包括无定型碳掩膜层以及其上的光刻胶层。
可选的,所述无定形碳掩膜层的材料为APF、ODC或SOC。
可选的,在所述无定型碳掩膜层以及所述光刻胶层之间还设置有介质抗反射层;还包括:在进行第二刻蚀之前或进行第二刻蚀时,将所述介质抗放射层去除。
可选的,在所述第一刻蚀中,所述光刻胶层一并被去除。
可选的,所述待刻蚀层为叠层结构,所述第二刻蚀包括多个刻蚀步骤。
可选的,所述粘合层包括第一粘合层以及其上的第二粘合层,所述待刻蚀层还包括第二粘合层上的保护层。
可选的,所述第一粘合层的材料为氧化硅,所述第二粘合层的材料为NDC,所述保护层的材料为氧化硅。
可选的,在所述第一刻蚀中,所述盲孔贯穿所述保护层至部分厚度的第二粘合层中。
可选的,所述第一粘合层与所述覆盖层之间还形成有扩散阻挡层,则,所述第二刻蚀的步骤包括:
将所述第二刻蚀孔图形转移至所述保护层中;
进行所述第二粘合层的刻蚀,直至所述盲孔贯穿至所述第一粘合层,并同时在所述盲孔周围部分厚度的第二粘合层中形成上部开口;
进行所述盲孔下第一粘合层的刻蚀,直至所述盲孔贯穿至所述扩散阻挡层;
进行所述上部开口下第二粘合层的刻蚀,以形成所述上部过孔,以及进行所述盲孔下扩散阻挡层的刻蚀,以形成所述底部过孔。
本发明实施例提供的一种半导体器件的制造方法,提供衬底,衬底上形成有介质材料的覆盖层,覆盖层中形成有连线层,覆盖层上形成有待刻蚀层,待刻蚀层包括粘合层,在粘合层上形成曝光图案化膜层,曝光图案化膜层中形成有第一刻蚀孔图形,以曝光图案化膜层为掩蔽,在待刻蚀层中形成盲孔,对曝光图案化膜层进行修整,以扩大第一刻蚀孔图形而形成第二刻蚀孔图形,以修整后的曝光图案化膜层为掩蔽,进行待刻蚀层的第二刻蚀,以形成键合孔,并在键合孔中形成键合垫。也就是说,本申请实施例只需要进行一次光刻工艺,就可以通过刻蚀形成键合孔,相比于现有技术中的通过两块掩模版进行两次光刻工艺而言,减少光刻工艺的次数,降低了制造成本,提高了生产率及生产竞争力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。
图1示出了根据本发明实施例半导体器件的制造方法的流程示意图;
图2-11示出了根据本发明实施例的制造方法形成半导体器件过程中的结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是本发明还可以采用其它不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施例的限制。
其次,本发明结合示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
正如背景技术中的描述,采用大马士革工艺形成键合垫,可以具体为,在形成键合孔后,在键合孔中填充金属材料形成键合垫。其中,键合孔可以包括贯通至连线层的底部过孔和位于底部过孔上方的上部过孔,上部过孔的孔径大于底部过孔,因此在形成键合孔时,需要通过两块掩模版和两次光刻及刻蚀工艺,来分别形成底部过孔和上部过孔,导致制造工艺的成本较高。
为了解决上述技术问题,本申请实施例提供了一种半导体器件的制造方法,提供衬底,衬底上形成有介质材料的覆盖层,覆盖层中形成有连线层,覆盖层上形成有待刻蚀层,待刻蚀层包括粘合层,在粘合层上形成曝光图案化膜层,曝光图案化膜层中形成有第一刻蚀孔图形,以曝光图案化膜层为掩蔽,在待刻蚀层中形成盲孔,对曝光图案化膜层进行修整,以扩大第一刻蚀孔图形而形成第二刻蚀孔图形,以修整后的曝光图案化膜层为掩蔽,进行待刻蚀层的第二刻蚀,以形成键合孔,并在键合孔中形成键合垫。也就是说,本申请实施例只需要进行一次光刻工艺在曝光图案化膜层上形成第一刻蚀孔图形,经过一次修整工艺在曝光图案化膜层上形成第二刻蚀孔图形,就可以通过刻蚀形成键合孔,相比于现有技术中的通过两块掩模版进行两次光刻工艺而言,减少光刻工艺的次数,降低了制造成本,提高了生产率及生产竞争力。
为了更好地理解本申请的技术方案和技术效果,以下将结合流程图1和附图2-11,对具体的实施例进行详细的描述。
参考图1所示,为本申请实施例提供的一种半导体器件的制造方法的流程图,包括以下步骤:
S101,提供衬底100,衬底上形成有介质材料的覆盖层120,所述覆盖层120中形成有连线层122,覆盖层120上还形成有待刻蚀层,待刻蚀层包括粘合层140、142,参考图2所示。
在本申请实施例中,衬底100为半导体衬底,例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅,Silicon On Insulator)或GOI(绝缘体上锗,Germanium OnInsulator)等。在其他实施例中,衬底100还可以为包括其他元素半导体或化合物半导体的衬底,例如GaAs、InP或SiC等,还可以为叠层结构,例如Si/SiGe等,还可以为其他外延结构,例如SGOI(绝缘体上锗硅)等。在本实施例中,该衬底100可以为硅衬底。
该衬底100上可以已经完成键合层之前的所有工艺,例如衬底100上已经形成有器件结构以及电连接器件结构的互连层,器件结构由层间介质层110覆盖,该层间介质层110可以为氧化硅,互连层形成于介质材料中,器件结构可以为MOS器件、存储器件、传感器器件和/或其他无源器件,互连层可以包括多层,互连层包括接触塞、过孔或连接层,互连层可以为金属材料,例如可以为钨、铝、铜等。在本申请实施例的图示中,仅图示出顶层的连线层122,此处仅是为了简化附图,可以理解的是,此处仅为示例,在不同的设计和应用中,可以根据需要形成所需层数的互连层。
本申请实施例中,连线层122为形成键合孔之前的最顶层的互连层,该连线层可以为顶层金属层(top metal),可以由金属材料形成,在本实施例中,连线层122可以为金属铜。连线层122形成于覆盖层120中,覆盖层120为用于隔离该最顶层的连线层122的介质材料,覆盖层120可以为单层或多层结构。在本实施例中,该覆盖层120为单层结构,可以包括氧化硅层,氧化硅层120的厚度例如可以为10000 Å。
在覆盖层120上还形成有待刻蚀层,键合孔将形成于该待刻蚀层中,待刻蚀层由介质材料形成,可以包括有键合用的粘合层,粘合层可以包括第一粘合层140以及其上的第二粘合层142,在一些实施例中,待刻蚀层还可以包括第二粘合层142上的保护层146。待刻蚀层一方面用于与其他晶片键合时的键合材料层,同时,也作为键合孔中金属材料的隔离层。
第一粘合层140和第二粘合层142可以为不同的键合(bonding)材料,第二粘合层142可以选用性能更优的键合材料,本实施例中,第一粘合层140可以为键合用氧化硅(bonding oxide),第二粘合层142可以为NDC(Nitrogen doped Silicon Carbide,掺氮碳化硅),保护层146用于粘合层的保护,该保护层146可以为氧化硅。在一个具体的示例中,第一粘合层140、第二粘合层142和保护层146的厚度分别可以为10000 Å、1000 Å、2000 Å。
本实施例中,在覆盖层120和第一粘合层140之间还可以进一步形成有扩散阻挡层130,该阻挡层130覆盖了覆盖层120以及连线层122,可以避免刻蚀过程中金属材料的连线层122的溅射以及扩散。在一个具体的示例中,扩散阻挡层130的材料可以为氮化硅,厚度可以为750 Å。
S102,在待刻蚀层上形成有曝光图案化膜层150、154并进行光刻工艺,以在所述曝光图案化膜层150、154中形成第一刻蚀孔图形156,参考图2和图3所示。
在待刻蚀层上可以形成有曝光图案化膜层150、154,具体的,可以在第二粘合层142上形成有曝光图案化膜层150、154。若第二粘合层142上形成有保护层146,则曝光图案化膜层150、154形成于保护层146上,参考图2所示。其中,曝光图案化膜层采用可以通过曝光用于图案化工艺的掩膜材料,可以包括单层或叠层结构,在本申请实施例中,至少包括可通过曝光转移图案的掩膜材料,例如光刻胶材料等,在一些实施例中,该曝光图案化膜层可以包括无定形碳掩膜层150以及其上的光刻胶层154,无定形碳掩膜层的材料可以为富碳的有机凝聚态化合物,这些化合物例如可以为先进图膜(APF,Advanced Patterning Film)、有机底膜(ODL ,Organic Under Layer)或旋涂的含碳材料(SoC,Spin on Carbon)等。无定形碳掩膜层150的材料较光刻胶材料具有更硬的材质,同时兼具光刻胶材料可用于掩膜的特性,可以采用修整工艺沿横向进行去除,在用于掩膜的同时,还可以避免刻蚀过程中对其过多消耗。
具体的,可以利用光刻技术,光刻工艺包括烘烤、曝光、显影等步骤,通过光刻工艺将掩模版中的图案转移到光刻胶层154中,从而在光刻胶层154中形成第一刻蚀孔图形156,参考图2所示。而后,可以以光刻胶层154为掩蔽,将光刻胶层中的第一刻蚀孔图形156转移至无定形碳掩膜层150中,从而在曝光图案化膜层中形成贯穿无定形碳掩膜层150以及光刻胶层154的第一刻蚀孔图形156。
在无定形碳掩膜层150和光刻胶层154之间还可以形成有DARC(Dielectric Anti-reflective Coating,介电抗反射涂层)层152,DARC层152可以在后续刻蚀过程中对其下的无定形碳掩膜层150形成保护作用,避免后续工艺中在垂直方向上对无定形碳掩膜层150的消耗。此时,可以以光刻胶层154为掩蔽,将光刻胶层154中的第一刻蚀孔图形156转移至DARC层152和无定形碳掩膜层150中,从而形成贯穿无定形碳掩膜层150、DARC层152、光刻胶层154的第一刻蚀孔图形156,参考图3所示。
S103,以曝光图案化膜层150、154为掩蔽,进行待刻蚀层的第一刻蚀,以在待刻蚀层中形成盲孔147,参考图4所示。
在形成曝光图案化膜层150、154后,可以以曝光图案化膜层150、154为掩蔽,进行待刻蚀层的第一刻蚀,去除第一刻蚀孔图形156下的待刻蚀层,以在待刻蚀层中形成盲孔147,参考图4所示,形成的盲孔147的孔径和第一刻蚀孔图形156的孔径基本一致。
在第一刻蚀中,可以以第二粘合层142为刻蚀停止层,也可以对第二粘合层142进行过刻蚀,从而去除位于第二粘合层142上部的部分第二粘合层材料,参考图4所示。需要说明的是,在第二粘合层142上未形成有保护层146时,可以对第二粘合层142进行过刻蚀,从而去除位于第二粘合层142上部的部分第二粘合层材料,形成第二粘合层142上的凹陷作为盲孔147;在第二粘合层142上形成有保护层146时,可以以第二粘合层142为刻蚀停止层,形成的盲孔147贯穿保护层146,当然,此时也可以对第二粘合层142进行过刻蚀,形成的盲孔147贯穿保护层146至部分厚度的第二粘合层142中,参考图4所示。
在对待刻蚀层的第一刻蚀过程中,光刻胶层154可能同时被消耗而去除,保留的无定形碳掩膜层150以及其上的DARC层152可以作为后续刻蚀过程中的硬掩膜层。至此,仅进行了一次光刻胶层154的光刻工艺。
S104,进行曝光图案化膜层150的修整,以扩大第一刻蚀孔图形156而形成第二刻蚀孔图形157,参考图5所示。
在待刻蚀层中形成盲孔147后,还可以进行曝光图案化膜层150的修整,从而扩大第一刻蚀孔图形156而形成第二刻蚀孔图形157,参考图5所示。对曝光图案化膜层150的修整,在修整工艺中,采用氧气作为主刻蚀气体,实现横向刻蚀,氧气对氧化硅等其他介质材料有无限高的刻蚀选择比,而同时刻蚀碳化物的速率很快,可以实现横向侧壁刻蚀,沿横向去除第一刻蚀孔图形156侧壁的部分曝光图案化膜层150,从而扩大第一刻蚀孔图形156,形成的第二刻蚀孔图形157的孔径大于第一刻蚀孔图形156的孔径。
若无定形碳掩膜层150上形成有DARC层152,则对曝光图案化膜层150的修整包括对无定形碳掩膜层150和DARC层152进行修整,形成的第二刻蚀孔图形157贯穿无定形碳掩膜层150和DARC层152,且孔径大于盲孔147,参考图5所示。
在对曝光图案化膜层150进行修整后,在曝光图案化膜层150中形成有孔径较大的第二刻蚀孔图形157,而在待刻蚀层中形成有盲孔147。由上可知,盲孔可以是位于第二粘合层142中的凹陷,也可以仅贯穿保护层146,还可以贯穿保护层146至部分厚度的第二粘合层142中。
S105,以修整后的曝光图案化膜层150为掩蔽,进行待刻蚀层的第二刻蚀,以形成键合孔,参考图6-11所示。
以修整后的曝光图案化膜层150为掩蔽,可以进行待刻蚀层的第二刻蚀,从而形成待刻蚀层中的键合孔160、162。其中,待刻蚀层中形成有孔径较小的盲孔147,对待刻蚀层进行逐层刻蚀过程中,可以利用该盲孔147,在盲孔147下形成刻蚀孔147’,直至贯穿至互连层122,从而形成与盲孔147的孔径基本一致的底部过孔160,而曝光图案化膜层150中形成有孔径较大的第二刻蚀孔图形157,以曝光图案化膜层150为掩蔽,在刻蚀过程中,可以在待刻蚀层中形成与第二刻蚀孔图形157孔径基本一致的上部过孔162,上部过孔162的孔径大于底部过孔160。也就是说,在本申请实施例中,形成的键合孔可以包括利用盲孔147而形成的贯通至连线层的底部过孔160,以及在第二刻蚀孔图形157下、底部过孔160上部分厚度的待刻蚀层中形成的上部过孔162,参考图11所示。
在具体的应用中,待刻蚀层可以具有不同的结构和材料,盲孔也可以具有不同的深度,在待刻蚀层为叠层结构时,第二刻蚀可以包括多个刻蚀步骤,本领域技术人员可以根据实际需要确定具体的刻蚀步骤。下面以待刻蚀层包括第一粘合层140、第二粘合层142和保护层146为例,第一粘合层140、第二粘合层142和保护层146的材料可以分别为氧化硅、NDC和氧化硅,对第二刻蚀的具体步骤进行详细说明,该示例中,步骤S103中形成的盲孔147贯穿保护层146至第一粘合层140后,过刻蚀至部分厚度的第二粘合层142中,参考图4所示。
首先,可以以修整后的曝光图案化膜层150为掩蔽,进行保护层146的刻蚀,将第二刻蚀孔图形157转移到保护层146中。对保护层146的刻蚀可以通过各向异性的干法刻蚀进行,具体的,可以利用RIE(反应离子刻蚀),刻蚀气体可以包括 C4F8/Ar/O2/CO 等气体,该刻蚀气体对第二粘合层142具有刻蚀选择性,可以以该第二粘合层142为刻蚀停止层,对保护层146进行图案化刻蚀,从而在保护层中形成刻蚀开口148,参考图6所示。
而后,可以继续对第二粘合层142进行刻蚀。具体的,可以以修整后的曝光图案化膜层150为掩蔽,选择对第一粘合层140具有刻蚀选择性的气体,以第一粘合层140为刻蚀停止层,对第二粘合层142进行刻蚀。刻蚀方式可以是各向异性的干法刻蚀,例如可以利用RIE(反应离子刻蚀),刻蚀气体可以包括CF4/CH2F2/CHF3/O2等。
其中,在对第二粘合层142进行刻蚀的过程中,由于第二粘合层142中已形成有盲孔147的图形,盲孔147底部的第二粘合层142较薄,因此较先被刻蚀去除,增加了盲孔147的深度,在盲孔147下形成了刻蚀孔147’,该刻蚀孔147’贯穿至第一粘合层140时,可以停止对第二粘合层142的刻蚀;而盲孔147周围未被曝光图案化膜层150覆盖的其他区域,则会有第二粘合层142保留,去除的第二粘合层142的区域可以构成上部开口149,参考图7所示。
此外,在对第二粘合层142进行刻蚀的过程中,会对盲孔下的第一粘合层140造成一定的损失,使得盲孔147下的第一粘合层140被过刻蚀,从而使得刻蚀孔147’进一步贯穿至部分厚度的第一粘合层140中,参考图7所示。
之后,可以继续进行第一粘合层140的刻蚀,该刻蚀对第二粘合层142具有刻蚀选择性,进一步去除刻蚀孔147’下暴露出的第一粘合层140,以进一步加深盲孔147下的刻蚀孔147’。在覆盖层120和第一粘合层140之间形成有扩散阻挡层130时,加深后的刻蚀孔147’可以贯穿至扩散阻挡层130,参考图8所示。对第一粘合层140的刻蚀方式可以是各向异性的干法刻蚀方式,具体的,可以利用RIE(反应离子刻蚀),刻蚀气体可以包括C4F6/Ar/O2/CO等。
最后,在形成贯穿至扩散阻挡层130的刻蚀孔147’后,还可以继续进行刻蚀孔147’底部的扩散阻挡层130的刻蚀,使得刻蚀孔147’贯穿至互连层122,从而在盲孔147下形成底部过孔160。具体的,可以以第二粘合层142为掩蔽,以互连层122为刻蚀停止层,进行扩散阻挡层130的刻蚀,形成的底部过孔160的孔径与盲孔147基本一致,参考图9所示。
在本申请实施例中,还可以以修整后的曝光图案化膜层150为掩蔽,对第二粘合层142进行刻蚀,即对上部开口149下的第二粘合层142进行刻蚀,从而形成上部开口149下的上部过孔162,上部过孔162位于底部过孔160上,且孔径与第二刻蚀孔图形157基本一致,参考图9所示。为了增加上部过孔162的深度,还可以对上部过孔162底部的第一粘合层140进行刻蚀,作为一种示例,保留的第一粘合层140厚度为4500-5500 Å。
在该示例中,该扩散阻挡层130的材料为氮化硅,所述第二粘合层142和第一粘合层140的材料分别为NDC、氧化硅,通过选择合适的刻蚀气体,在打开盲孔147下的扩散阻挡层130的同时,可以去除上部开口149下的第二粘合层142并进一步过刻蚀至第一粘合层140中,从而,形成的上部过孔162贯穿至部分厚度的第一粘合层140中,下部过孔160贯穿至连线层122,在该刻蚀步骤中,介质抗反射层152以及无定型碳掩膜层150可以一并被消耗而去除。
至此,可以形成贯穿至互连层122的底部过孔160,以及在第二刻蚀孔图形157下、底部过孔160上的待刻蚀层中形成的部分厚度的上部过孔162,底部过孔160和上部过孔162共同构成键合孔,由此,完成了对待刻蚀层的第二刻蚀,形成了键合孔160、162。
可以理解的是,在进行第二刻蚀时,以修整后的曝光图案化膜层150为掩蔽,曝光图案化膜层150中的介质抗反射层152对其下的不定型碳膜层起150到保护作用,刻蚀过程中对介质抗反射层152可以有一定的消耗。在第二刻蚀之前、进行第二刻蚀时或在第二刻蚀之后,可以将介质抗反射层152去除,在进行第二刻蚀后,不再需要掩膜,则可以去除不定型碳膜层150,参考图10所示。
S106,在键合孔160、162中形成键合垫170,参考图11所示。
之后,可以继续完成其他的加工工艺,例如在所述键合孔160、162中填充金属材料,金属材料例如可以为铜,并进行平坦化工艺,例如化学机械平坦化工艺,这样,上部过孔162以及底部过孔160中都将填充有金属材料,填充有金属材料的上部过孔162部分则作为键合及电连接结构使用,而填充有金属材料的底部过孔160则将衬垫与连线层122电连接起来。在平坦化工艺中,可以一并去除待刻蚀层中的保护层146,直至去除部分第二粘合层142,以使得第二粘合层142的表面平整度达到键合工艺要求,参考图11所示。具体的,保留的第二粘合层142的厚度范围可以为600-700 Å,平坦化后表面平整度的误差范围可以在0-100 Å。
本申请实施例提供了一种半导体器件的制造方法,提供衬底,衬底上形成有介质材料的覆盖层,覆盖层中形成有连线层,覆盖层上形成有待刻蚀层,待刻蚀层包括粘合层,在粘合层上形成曝光图案化膜层,曝光图案化膜层中形成有第一刻蚀孔图形,以曝光图案化膜层为掩蔽,在待刻蚀层中形成盲孔,对曝光图案化膜层进行修整,以扩大第一刻蚀孔图形而形成第二刻蚀孔图形,以修整后的曝光图案化膜层为掩蔽,进行待刻蚀层的第二刻蚀,以形成键合孔,并在键合孔中形成键合垫。也就是说,本申请实施例只需要进行一次光刻工艺在曝光图案化膜层上形成第一刻蚀孔图形,经过一次修整工艺在曝光图案化膜层上形成第二刻蚀孔图形,就可以通过刻蚀形成键合孔,相比于现有技术中的通过两块掩模版进行两次光刻工艺而言,减少光刻工艺的次数,降低了制造成本,提高了生产率及生产竞争力。
本说明书中的各个实施例均采用递进的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其它实施例的不同之处。尤其,对于存储器件实施例而言,由于其基本相似于方法实施例,所以描述得比较简单,相关之处参见方法实施例的部分说明即可。
以上所述仅是本发明的优选实施方式,虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。

Claims (8)

1.一种半导体器件的制造方法,其特征在于,包括:
提供衬底,所述衬底上形成有介质材料的覆盖层,所述覆盖层中形成有连线层,所述覆盖层上还形成有待刻蚀层,所述待刻蚀层包括粘合层;
在所述待刻蚀层上形成曝光图案化膜层并进行光刻工艺,以在所述曝光图案化膜层中形成第一刻蚀孔图形,所述曝光图案化膜层包括无定型碳掩膜层以及其上的光刻胶层;
以所述无定型碳掩膜层以及其上的光刻胶层为掩蔽,进行所述待刻蚀层的第一刻蚀,以在所述待刻蚀层中形成盲孔,所述光刻胶层一并被消耗而去除,保留所述无定型碳掩膜层;
进行所述无定型碳掩膜层的修整,以扩大所述第一刻蚀孔图形而形成第二刻蚀孔图形;
以修整后的所述无定型碳掩膜层为掩蔽,进行所述待刻蚀层的第二刻蚀,以形成键合孔,所述无定型碳掩膜层一并被消耗而去除,所述键合孔包括利用所述盲孔形成的贯通至所述连线层的底部过孔,以及在所述第二刻蚀孔图形下、所述底部过孔上的部分厚度的待刻蚀层中形成的上部过孔;
在所述键合孔中形成键合垫。
2.根据权利要求1所述的制造方法,其特征在于,所述无定型碳掩膜层的材料为先进图膜、有机底膜或旋涂的含碳材料。
3.根据权利要求1所述的制造方法,其特征在于,在所述无定型碳掩膜层以及所述光刻胶层之间还设置有介质抗反射层;还包括:在进行第二刻蚀之前或进行第二刻蚀时,将所述介质抗反射层去除。
4.根据权利要求1-3中任一项所述的制造方法,其特征在于,所述待刻蚀层为叠层结构,所述第二刻蚀包括多个刻蚀步骤。
5.根据权利要求4所述的制造方法,其特征在于,所述粘合层包括第一粘合层以及其上的第二粘合层,所述待刻蚀层还包括第二粘合层上的保护层。
6.根据权利要求5所述的制造方法,其特征在于,所述第一粘合层的材料为氧化硅,所述第二粘合层的材料为掺氮碳化硅,所述保护层的材料为氧化硅。
7.根据权利要求5所述的制造方法,其特征在于,在所述第一刻蚀中,所述盲孔贯穿所述保护层至部分厚度的第二粘合层中。
8.根据权利要求7所述的制造方法,其特征在于,所述第一粘合层与所述覆盖层之间还形成有扩散阻挡层,则,所述第二刻蚀的步骤包括:
将所述第二刻蚀孔图形转移至所述保护层中;
进行所述第二粘合层的刻蚀,直至所述盲孔贯穿至所述第一粘合层,并同时在所述盲孔周围部分厚度的第二粘合层中形成上部开口;
进行所述盲孔下第一粘合层的刻蚀,直至所述盲孔贯穿至所述扩散阻挡层;
进行所述上部开口下第二粘合层的刻蚀,以形成所述上部过孔,以及进行所述盲孔下扩散阻挡层的刻蚀,以形成所述底部过孔。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1166055A (zh) * 1996-05-23 1997-11-26 世界先进积体电路股份有限公司 导电体连线的制造方法
WO2004012254A1 (ja) * 2002-07-30 2004-02-05 Sony Corporation 半導体装置の製造方法
CN101123214A (zh) * 2006-08-07 2008-02-13 联华电子股份有限公司 双镶嵌结构的制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101615914B1 (ko) * 2008-02-01 2016-04-27 램 리써치 코포레이션 포토레지스트 스트립핑 동안 로우-k 재료에 대한 손상 감소
US8298935B2 (en) * 2010-11-22 2012-10-30 United Microelectronics Corp. Dual damascene process
US9685404B2 (en) * 2012-01-11 2017-06-20 International Business Machines Corporation Back-end electrically programmable fuse
US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
EP3029724B1 (en) * 2014-12-01 2017-06-07 IMEC vzw Metallization method for semiconductor structures
KR102463893B1 (ko) * 2015-04-03 2022-11-04 삼성전자주식회사 하드마스크 조성물 및 이를 이용한 패턴의 형성방법
US9824920B2 (en) * 2016-04-04 2017-11-21 Globalfoundries Inc. Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices
US9659821B1 (en) * 2016-05-23 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming interconnect structures by self-aligned approach
EP3367428A1 (en) * 2017-02-23 2018-08-29 IMEC vzw Method for blocking a trench portion during patterning of trenches in a dielectric material, and corresponding semiconductor structure
US10680101B2 (en) * 2017-07-31 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Power metal-oxide-semiconductor field-effect transistor
US10312201B1 (en) * 2017-11-30 2019-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring for hybrid-bond
CN109524300B (zh) * 2018-11-28 2021-08-03 上海华力微电子有限公司 一种刻蚀方法及半导体器件
US10748765B2 (en) * 2018-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer mask and method of forming same
US10811309B2 (en) * 2018-12-04 2020-10-20 Nanya Technology Corporation Semiconductor structure and fabrication thereof
US11037947B2 (en) * 2019-04-15 2021-06-15 Macronix International Co., Ltd. Array of pillars located in a uniform pattern

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1166055A (zh) * 1996-05-23 1997-11-26 世界先进积体电路股份有限公司 导电体连线的制造方法
WO2004012254A1 (ja) * 2002-07-30 2004-02-05 Sony Corporation 半導体装置の製造方法
CN101123214A (zh) * 2006-08-07 2008-02-13 联华电子股份有限公司 双镶嵌结构的制作方法

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