CN110299288A - 光学传感器封装系统 - Google Patents

光学传感器封装系统 Download PDF

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Publication number
CN110299288A
CN110299288A CN201910220796.4A CN201910220796A CN110299288A CN 110299288 A CN110299288 A CN 110299288A CN 201910220796 A CN201910220796 A CN 201910220796A CN 110299288 A CN110299288 A CN 110299288A
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CN
China
Prior art keywords
optical sensor
light
embedded
substrate
sensitive material
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CN201910220796.4A
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English (en)
Inventor
S·N·阿它维尔
Y-S·A·孙
Z·王
T·王
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Publication of CN110299288A publication Critical patent/CN110299288A/zh
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Abstract

一种光学传感器封装系统和方法可以包括:提供嵌入式基板,该嵌入式基板包括嵌入式芯片,该嵌入式芯片通过连接在该嵌入式芯片与重新分布焊盘之间的重新分布线联接到该重新分布焊盘;将光学传感器安装到该嵌入式基板,该光学传感器包括形成在该光学传感器的有源光学侧的光敏区域上的光敏材料;通过从该有源光学侧连接到该重新分布焊盘的第一接合引线来将该光学传感器引线接合到该嵌入式基板;以及利用包覆模制件来包封该光学传感器、该第一接合引线和该光敏材料,该包覆模制件形成有与该光敏材料的表面共面的顶表面,该包覆模制件围绕该光敏材料并围绕该光敏区域形成竖直延伸的边界,并且该包覆模制件形成在该第一接合引线上方。

Description

光学传感器封装系统
相关申请的交叉引用
本发明要求2018年3月24日提交的美国临时专利申请号62/647,660的所有共同主题的优先权权益。该申请的内容通过援引以其全文并入本文。
技术领域
本披露内容涉及集成电路封装,更具体地涉及例如利用光敏材料形成光学传感器封装。
背景技术
便携式电子装置(例如,蜂窝电话、膝上型计算机和可穿戴装置)的快速增长市场是现代生活的不可或缺方面。许多便携式装置代表下一代生物传感器封装的最大潜在市场机遇之一。这些装置具有对制造集成产生显著影响的独特属性,因为它们通常必须是小型、轻量且功能丰富的,并且它们必须以相对低的成本大批量生产。
作为半导体行业的扩展,生物传感器行业(例如包括心率监测器和外围氧传感器)已经见证了不断增长的商业竞争压力,以及不断增长的消费者期望和市场中有意义的产品差异化的机会减少。
封装大小和布局是下一代产品的开发路线图中概述的这些下一代电子器件插入策略的核心。有竞争力的下一代产品应当提高信噪比,降低成本,并以提高的传感器性能操作。重要的是,对于包括可穿戴环在内的一些行业分部而言,实现更小的形状因子和降低功率要求是至关重要的。
已经存在许多通过连续几代半导体来解决对微处理器和光学传感器的先进封装要求的方法。许多行业路线图已经标识了当前传感器能力与可用支持电子封装技术之间的显著差距。当前技术的局限性和问题包括大的晶片大小、较高的成本和受损的光学性质。
随着这些封装系统发展为合并更多具有不同环境需求的部件,推动技术发展的压力变得越来越具有挑战性。更重要的是,随着复杂性的不断增加,在制造过程中潜在的错误风险会大大增加。
鉴于不断增长的商业竞争压力以及不断增长的消费者期望和市场中有意义的产品差异化的机会减少,找到这些问题的答案就至关重要。另外,降低成本、减少生产时间、提高效率和性能、以及满足竞争压力的需要使得寻找这些问题的答案的关键必要性甚至更迫切。
因此,仍然需要更小的占用面积、更低的成本和改进的光学性质。长期以来一直在寻求这些问题的解决方案,但是先前的发展并没有教导或建议任何解决方案,并且因此这些问题的解决方案长期以来难倒了本领域技术人员。
附图说明
在附图中示出光学传感器封装系统,这些附图旨在是示例性的而非限制性的,其中相同的附图标记旨在表示相同的部件,并且在附图中:
图1是第一实施例中的封装系统的顶视图。
图2是图1的封装系统沿线2-2的横截面视图。
图3是图1的右光学传感器在光敏材料显影制造阶段之后的平面图。
图4是图3的右光学传感器的沿线4-4的横截面视图。
图5是第二实施例中的封装系统的顶视图。
图6是图5的封装系统沿线6-6的横截面视图。
图7是图5的封装系统在导体电镀制造阶段之后的横截面视图。
图8是图5的封装系统在晶片附接制造阶段之后的横截面视图。
图9是图5的封装系统在导体蚀刻制造阶段之后的横截面视图。
图10是图5的封装系统在装运制造阶段之后的横截面视图。
图11是图5的封装系统在光敏材料图案化制造阶段之后的横截面视图。
图12是图5的封装系统在光学晶片切片制造阶段之后的横截面视图。
图13是图5的封装系统在模制制造阶段之后的横截面视图。
图14是图5的封装系统在封装切片制造阶段之后的横截面视图。
图15是第三实施例中的封装系统在模制制造阶段之后的横截面视图。
图16是图15的封装系统在光敏材料剥离制造阶段之后的横截面视图。
图17是第四实施例中的封装系统在模制制造阶段之后的横截面视图。
图18是图17的封装系统在光敏材料剥离制造阶段之后的横截面视图。
图19是第五实施例中的封装系统的横截面视图。
图20是图19的封装系统在接合焊盘形成制造阶段之后的横截面视图。
图21是图19的封装系统在粘合剂涂覆制造阶段之后的横截面视图。
图22是图19的封装系统在基板晶片放置制造阶段之后的横截面视图。
图23是图19的封装系统在柱形成制造阶段之后的横截面视图。
图24是图19的封装系统在第一基板模具打磨制造阶段之后的横截面视图。
图25是图19的封装系统在通孔形成制造阶段之后的横截面视图。
图26是图19的封装系统在扇出制造阶段之后的横截面视图。
图27是图19的封装系统在第二基板模具打磨制造阶段之后的横截面视图。
图28是图19的封装系统在去掉支架制造阶段之后的横截面视图。
图29是图19的封装系统在焊接掩模制造阶段之后的横截面视图。
图30是图19的封装系统在装运制造阶段之后的横截面视图。
图31是图19的封装系统在引线结合制造阶段之后的横截面视图。
图32是图19的封装系统在包覆模制制造阶段之后的横截面视图。
图33是图19的封装系统在剥离制造阶段之后的横截面视图。
图34是第六实施例中的封装系统的横截面视图。
图35是图34的封装系统在第一支架提供制造阶段之后的横截面视图。
图36是图34的封装系统在晶种层沉积制造阶段之后的横截面视图。
图37是图34的封装系统在通孔形成制造阶段之后的横截面视图。
图38是图34的封装系统在柱电镀制造阶段之后的横截面视图。
图39是图34的封装系统在晶种层蚀刻制造阶段之后的横截面视图。
图40是图34的封装系统在基板芯片放置制造阶段之后的横截面视图。
图41是图34的封装系统在第一基板模制制造阶段之后的横截面视图。
图42是图34的封装系统在扇出图案化制造阶段之后的横截面视图。
图43是图34的封装系统在扇出电镀制造阶段之后的横截面视图。
图44是图34的封装系统在剥离制造阶段之后的横截面视图。
图45是图34的封装系统在电介质沉积制造阶段之后的横截面视图。
图46是图34的封装系统在第二支架附接制造阶段之后的横截面视图。
图47是图34的封装系统在第一支架去除制造阶段之后的横截面视图。
图48是图34的封装系统在光学晶片附接制造阶段之后的横截面视图。
图49是图34的封装系统在包覆模制制造阶段之后的横截面视图。
图50是图34的封装系统在第二支架去除制造阶段之后的横截面视图。
图51是图34的封装系统在剥离制造阶段之后的横截面视图。
图52是图34的封装系统在切片带附接制造阶段之后的横截面视图。
图53是图34的封装系统在切片制造阶段之后的横截面视图。
图54是用于制造封装系统的制造方法的流程图。
具体实施方式
在以下描述中,参考形成该描述的一部分的附图,并且其中通过图示的方式示出了可以实践封装系统的实施例。应当理解,在不脱离封装系统的范围的情况下,可以利用其他实施例并且可以进行结构改变。
当在过程、操作、控制流程或流程图的步骤方面描述封装系统的特征、方面或实施例时,应当理解,在不脱离如本文所述的封装系统的情况下,这些步骤可以组合、以不同的顺序执行、删除或包括附加步骤。
足够详细地描述了封装系统,以使得本领域技术人员能够制造和使用封装系统并提供许多具体细节以便彻底了解封装系统;然而,将显而易见的是,可以在没有这些具体细节的情况下实践该封装系统。
为了避免模糊封装系统,并未详细地披露一些众所周知的系统配置和描述。同样地,示出系统的实施例的附图是半示意性的且不按比例,并且具体地,为了呈现的清晰,一些尺寸在附图中放大地示出。通常,封装系统可以在任何取向上操作。
如本文所使用,术语系统被定义为装置或方法,取决于使用它的上下文。出于说明目的,如本文所使用的术语“水平”被定义为平行于包覆模制件的顶平面或顶表面的平面,而不管其取向如何。术语“垂直”是指垂直于刚才定义的水平的方向。诸如“上方”、“下方”、“底部”、“顶部”、“侧面”、“更高”、“下部”、“上部”、“上面”和“下面”等术语是相对于水平面定义的。
如本文所使用,术语“联接”意指任何物理接触,包括通过中间元件的接触。如本文所使用,术语“共面”意指两个或更多个平坦表面的平面是同一平面。
仅出于清楚的原因,依赖于光学传感器披露并展示了封装系统。本领域普通技术人员应当理解,除非明确声明,否则光学传感器不被认为是封装系统的要求。预期封装系统可以替代性地用压力传感器、流体传感器、化学传感器、指纹传感器、环境传感器或其组合来实施。
现在参考图1,其中示出了第一实施例中的封装系统100的顶视图。封装系统100被示出为具有部分包封光学传感器104的包覆模制件102。
光学传感器104从包覆模制件102的感测窗口106内暴露。感测窗口106可以由竖直延伸的边界108界定,并且可以使光学传感器104在从光学传感器104的有源光学侧110到包覆模制件102的顶表面112的竖直延伸的边界108之间暴露。光学传感器104被描绘为左光学传感器114和右光学传感器116。光学传感器104中的每一个分别从感测窗口106暴露。
现在参考图2,其中示出了图1的封装系统100沿线2-2的横截面视图。封装系统100被描绘为具有形成在嵌入式基板204上方的光学传感器模块202。光学传感器模块202可以包括部分包封光学传感器104的包覆模制件102。
光学传感器104从包覆模制件102的感测窗口106内暴露。感测窗口106可以使光学传感器104在竖直延伸的边界108之间暴露。竖直延伸的边界108可以从光学传感器104的有源光学侧110延伸到包覆模制件102的顶表面112。
包覆模制件102可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件102以形成围绕感测窗口106的竖直延伸的边界108,从而使穿其而过有源光学侧110暴露。
光学传感器104可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。设想右光学传感器116和左光学传感器114是传感器;然而,替代性地设想例如右光学传感器116、左光学传感器114或其组合可以用诸如发光二极管等光源来代替。
有源光学侧110可以是光学传感器104的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧110被描绘为沿与包覆模制件102的顶表面112相同的方向面向上。替代性地设想,例如当光学传感器104被配置用于感测传播通过光学传感器104的主体材料的较长波长时,光学传感器104可以包括朝向嵌入式基板204面向下的有源光学侧110。
顶表面112可以是平行于光学传感器104的有源光学侧110的平坦表面。围绕感测窗口106的竖直延伸的边界108被示例性地描绘为竖直向上背离有源光学侧110延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器104的中心或背离光学传感器104的中心成一定角度延伸的竖直延伸的边界108。感测窗口106被描绘为在左光学传感器114和右光学传感器116两者之上的单独窗口。
竖直延伸的边界108可以形成在光学传感器104的顶部上、与有源光学侧110直接接触。光学传感器104可以通过晶片附接材料220来附连到嵌入式基板204。
晶片附接材料220可以是晶片附接粘合剂(诸如环氧树脂)、具有导热填料的聚合物粘合剂或低共熔晶片附接材料。左光学传感器114和右光学传感器116两者都被描绘为通过晶片附接材料220来附连到嵌入式基板204。
有源光学侧110可以通过接合引线222电联接到嵌入式基板204,该接合引线从光学传感器104的有源光学侧110上的传感器焊盘224延伸到从嵌入式基板204暴露的重新分布焊盘226。说明性地,右光学传感器116和左光学传感器114两者都包括从左光学传感器114和右光学传感器116的有源光学侧110到它们相应的重新分布焊盘226的接合引线连接。
替代性地设想,当光学传感器104具有朝向嵌入式基板204面向下的有源光学侧110时,接合引线222可以用传感器焊盘224与重新分布焊盘226之间的球形接合件来代替。包覆模制件102被示出为将接合引线222、晶片附接材料220和光学传感器104包封在嵌入式基板204上方。
包覆模制件102的顶表面112被示出为在接合引线222上方,这意味着竖直延伸的边界108竖直延伸超过接合引线222的顶部直至顶表面112,以便形成感测窗口106和完全包封接合引线222的包覆模制件102。包覆模制件102被描绘为在左光学传感器114与右光学传感器116之间,从而将左光学传感器114与右光学传感器116隔离。
重新分布焊盘226可以电联接到重新分布线228,它们之间存在导电柱230。导电柱230可以从重新分布焊盘226延伸穿过嵌入式基板204的基板包封件232到达重新分布线228。
基板包封件232可以是类似于上述包覆模制件102的包封件的环氧树脂包封件。如将理解,导电柱230可以沿竖直轴线形成以用于沿竖直轴线在不同点处连接导电部件。重新分布线228可以沿水平轴线形成以用于沿水平轴线在不同点处连接导电部件。
重新分布线228可以从嵌入式芯片238的嵌入式芯片有源侧236扇出密集输入-输出阵列234。嵌入式芯片238可以是用于为光学传感器104提供模拟前端的专用集成电路。
嵌入式芯片238可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片238可以提供可配置且灵活的电子功能块,并且在嵌入式基板204中提供硬件模块化。
嵌入式芯片有源侧236可以是嵌入式芯片238的其上形成有诸如二极管和晶体管等有源部件的一侧。嵌入式芯片有源侧236被示例性地描绘为朝向重新分布线228和嵌入式基板204的底部面向下。
嵌入式芯片238可以附连到晶片焊盘240。晶片焊盘240可以在嵌入式基板204的制造过程期间为嵌入式芯片238提供结构稳定性,以及提供导热散热片以将热量吸出并使其离开嵌入式芯片238。基板包封件232被描绘为包封导电柱230、重新分布线228的顶部部分、嵌入式芯片238和晶片焊盘240。
重新分布线228被示出为从基板包封件232暴露;然而,替代性地设想,基板包封件232能够完全包封重新分布线228而仅使下方凸块材料242从其暴露。下方凸块材料242可以支持外部互连件的形成以用于将封装系统100连接到外部部件。
现在参考图3,其中示出了图1的右光学传感器116在光敏材料显影制造阶段之后的平面图。右光学传感器116的有源光学侧110被描绘为具有传感器焊盘224并在其上具有光敏材料302的保护层。
例如,光敏材料302可以被图案化以覆盖右光学传感器116的光敏区域304。出于本申请的目的,光敏材料302被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料302)涂布基板来开始在光刻工艺过程中涂覆光敏材料302的过程。然后可以将图案化掩模涂覆到光敏材料302的表面以便阻挡光,使得只有光敏材料302的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料302的部分。
光敏材料302通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料302是正性光敏材料时,光敏材料302被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光致抗蚀剂302是负性光敏材料时,光敏材料302通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。
现在参考图4,其中示出了图3的右光学传感器116的沿线4-4的横截面视图。右光学传感器116被示例性地描绘为具有形成在有源光学侧110中的传感器焊盘224。
传感器焊盘224可以联接到图2的接合引线222并支撑该接合引线。可以看到光敏材料302从有源光学侧110向上延伸。
光敏材料302的厚度可以大于从传感器焊盘224向上延伸的接合引线222的高度。如将理解,光敏材料302不完全覆盖右光学传感器116,而是被图案化以覆盖右光学传感器116的光敏区域304。
现在参考图5,其中示出了第二实施例中的封装系统500的顶视图。封装系统500被示出为具有部分包封光学传感器504的包覆模制件502。
光学传感器504从包覆模制件502的感测窗口506内暴露。感测窗口506可以使光学传感器504在从光学传感器504的有源光学侧510到包覆模制件502的顶表面512的竖直延伸的边界508之间暴露。
现在参考图6,其中示出了图5的封装系统500沿线6-6的横截面视图。封装系统500被描绘为具有形成在嵌入式基板604上方的光学传感器模块602。光学传感器模块602可以包括部分包封光学传感器504的包覆模制件502。
光学传感器504从包覆模制件502的感测窗口506内暴露。感测窗口506可以使光学传感器504在竖直延伸的边界508之间暴露。竖直延伸的边界508可以从光学传感器504的有源光学侧510延伸到包覆模制件502的顶表面512。
包覆模制件502可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件502以形成围绕感测窗口506的竖直延伸的边界508,从而使有源光学侧510透过其中暴露。
光学传感器504可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。替代性地设想,例如,在不偏离所披露的封装系统100的情况下,可以实施多个光传感器和光源。
有源光学侧510可以是光学传感器504的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧510被描绘为沿与包覆模制件502的顶表面512相同的方向面向上。替代性地设想,例如当光学传感器504被配置用于感测传播通过光学传感器504的主体材料的较长波长时,光学传感器504可以包括朝向嵌入式基板604面向下的有源光学侧510。
顶表面512可以是平行于光学传感器504的有源光学侧510的平坦表面。围绕感测窗口506的竖直延伸的边界508被示例性地描绘为竖直向上背离有源光学侧510延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器504的中心或背离光学传感器504的中心成一定角度延伸的竖直延伸的边界508。
竖直延伸的边界508可以形成在光学传感器504的顶部上、与有源光学侧510直接接触。光学传感器504可以通过晶片附接材料620来附连到嵌入式基板604。晶片附接材料620可以是晶片附接粘合剂(诸如环氧树脂)、具有导热填料的聚合物粘合剂或低共熔晶片附接材料。
有源光学侧510可以通过接合引线622电联接到嵌入式基板604,该接合引线从光学传感器504的有源光学侧510上的传感器焊盘624延伸到从嵌入式基板604暴露的重新分布焊盘626。
替代性地设想,当光学传感器504具有朝向嵌入式基板604面向下的有源光学侧510时,接合引线622可以用传感器焊盘624与重新分布焊盘626之间的球形接合件来代替。包覆模制件502被示出为将接合引线622、晶片附接材料620和光学传感器504包封在嵌入式基板604上方。
包覆模制件502的顶表面512被示出为在接合引线622上方,这意味着竖直延伸的边界508竖直延伸超过接合引线622的顶部直至顶表面512,以便形成感测窗口506和完全包封接合引线622的包覆模制件502。重新分布焊盘626可以电联接到重新分布线628,它们之间存在导电柱630。导电柱630可以从重新分布焊盘626延伸穿过嵌入式基板604的基板包封件632到达重新分布线628。
基板包封件632可以是类似于上述包覆模制件502的包封件的环氧树脂包封件。如将理解,导电柱630可以沿竖直轴线形成以用于沿竖直轴线在不同点处连接导电部件。重新分布线628可以沿水平轴线形成以用于沿水平轴线在不同点处连接导电部件。
重新分布线628可以从嵌入式芯片638的嵌入式芯片有源侧636扇出密集输入-输出阵列634。嵌入式芯片638可以是用于为光学传感器504提供模拟前端的专用集成电路。
嵌入式芯片638可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片638可以提供可配置且灵活的电子功能块,并且在嵌入式基板604中提供硬件模块化。
嵌入式芯片有源侧636可以是嵌入式芯片638的其上形成有诸如二极管和晶体管等有源部件的一侧。嵌入式芯片有源侧636被示例性地描绘为朝向重新分布线628和嵌入式基板604的底部面向下。
嵌入式芯片638可以通过嵌入式芯片晶片附接材料642来附连到晶片焊盘640。晶片焊盘640可以在嵌入式基板604的制造过程期间为嵌入式芯片638提供结构稳定性,以及提供导热散热片以将热量吸出并使其背离嵌入式芯片638。基板包封件632被描绘为包封导电柱630、重新分布线628、嵌入式芯片638以及晶片焊盘640的部分。
重新分布线628被示出为从基板包封件632完全包封,从而仅使下方凸块材料644从其暴露。下方凸块材料644可以支持外部互连件646的形成以用于将封装系统500连接到外部部件。
现在参考图7,其中示出了图5的封装系统500在导体电镀制造阶段之后的横截面视图。导体电镀制造阶段可以包括导电柱630的形成。
现在参考图8,其中示出了图5的封装系统500在晶片附接制造阶段之后的横截面视图。在晶片附接制造阶段过程中,嵌入式芯片638可以通过嵌入式芯片晶片附接材料642来联接到晶片焊盘640。
现在参考图9,其中示出了图5的封装系统500在导体蚀刻制造阶段之后的横截面视图。如可以看出,已形成将导电柱630与嵌入式芯片638的输入-输出阵列634联接的重新分布线628,已经分离出支架902,并且已经蚀刻铜。
现在参考图10,其中示出了图5的封装系统500在装运制造阶段之后的横截面视图。如将理解,嵌入式基板604可以在这个制造阶段完成,并且可以在稳定状态下装运以进行进一步处理。
现在参考图11,其中示出了图5的封装系统500在光敏材料图案化制造阶段之后的横截面视图。光学传感器504被描绘为与其他光学传感器一起形成和提供。
光学传感器504被描绘为包括经形成以覆盖光学传感器504的无源侧的晶片附接材料620,同时光敏材料1102的图案化层沉积在光学传感器504的有源光学侧510上。光敏材料1102可以沉积在光学传感器504的光学感测区域上,然后利用显影剂从光学感测区域之外的区域去除。出于本申请的目的,光敏材料1102被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料1102)涂布基板来开始在光刻工艺过程中涂覆光敏材料1102的过程。然后可以将图案化掩模涂覆到光敏材料1102的表面以便阻挡光,使得只有光敏材料1102的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料1102的部分。
光敏材料1102通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料1102是正性光敏材料时,光敏材料被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光敏材料1102是负性光敏材料时,光敏材料通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。
现在参考图12,其中示出了图5的封装系统500在光学晶片切片制造阶段之后的横截面视图。在光学传感器504被单独切片时,光学传感器504被示出为具有联接到光学传感器504中的每一个的光敏材料1102和晶片附接材料620。
现在参考图13,其中示出了图5的封装系统500在模制制造阶段之后的横截面视图。封装系统500被描绘为光学传感器504附连并安装到嵌入式基板604,接合引线622形成为将光学传感器504联接到嵌入式基板604,并且包覆模制件502形成为包封光学传感器504、接合引线622和光敏材料1102的侧面部分。包覆模制件502可以形成为从有源光学侧510到包覆模制件502的顶表面512与光敏材料1102直接接触。包覆模制件502可以与光敏材料1102的顶表面共面。
现在参考图14,其中示出了图5的封装系统500在封装切片制造阶段之后的横截面视图。单独封装系统500被示出为切片和分离,在切片之前具有形成在下方凸块材料644上的外部互连件646。
现在参考图15,其中示出了第三实施例中的封装系统1500在模制制造阶段之后的横截面视图。封装系统1500被描绘为具有形成在嵌入式基板1504上方的光学传感器模块1502。光学传感器模块1502可以包括部分包封光学传感器1508的包覆模制件1506。
光学传感器1508从包覆模制件1506的感测窗口1510内暴露。感测窗口1510可以使光学传感器1508在竖直延伸的边界1512之间暴露。竖直延伸的边界1512可以从光学传感器1508的有源光学侧1514延伸到包覆模制件1506的顶表面1516。
包覆模制件1506可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件1506以形成围绕感测窗口1510的竖直延伸的边界1512,从而使有源光学侧1514透过其中暴露。
光学传感器1508可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。替代性地设想,例如,在不偏离所披露的封装系统100的情况下,可以实施多个光传感器和光源。
有源光学侧1514可以是光学传感器1508的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧1514被描绘为沿与包覆模制件1506的顶表面1516相同的方向面向上。替代性地设想,例如当光学传感器1508被配置用于感测传播通过光学传感器1508的主体材料的较长波长时,光学传感器1508可以包括朝向嵌入式基板1504面向下的有源光学侧1514。
顶表面1516可以是平行于光学传感器1508的有源光学侧1514的平坦表面。围绕感测窗口1510的竖直延伸的边界1512被示例性地描绘为竖直向上背离有源光学侧1514延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器1508的中心或背离光学传感器1508的中心成一定角度延伸的竖直延伸的边界1512。
竖直延伸的边界1512可以形成在光学传感器1508的顶部上、与有源光学侧1514直接接触。可以形成与竖直延伸的边界1512和光学传感器1508的有源光学侧1514直接接触的光敏材料保护层1518。
包覆模制件1506可以与光敏材料1518的顶表面共面。例如,光敏材料1518可以被图案化以覆盖光学传感器104的光敏区域。出于本申请的目的,光敏材料1518被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料1518)涂布基板来开始在光刻工艺过程中涂覆光敏材料1518的过程。然后可以将图案化掩模涂覆到光敏材料1518的表面以便阻挡光,使得只有光敏材料的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料1518的部分。
光敏材料1518通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料1518是正性光敏材料时,光敏材料1518被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光敏材料1518是负性光敏材料时,光敏材料1518通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。
光学传感器1508可以通过晶片附接材料1520来附连到嵌入式基板1504。晶片附接材料1520可以是晶片附接粘合剂(诸如环氧树脂)、具有导热填料的聚合物粘合剂或低共熔晶片附接材料。
有源光学侧1514可以通过接合引线1522电联接到嵌入式基板1504,该接合引线从光学传感器1508的有源光学侧1514上的传感器焊盘1524延伸到从嵌入式基板1504暴露的重新分布焊盘1526。
替代性地设想,当光学传感器1508具有朝向嵌入式基板1504面向下的有源光学侧1514时,接合引线1522可以用传感器焊盘1524与重新分布焊盘1526之间的球形接合件来代替。包覆模制件1506被示出为将接合引线1522、晶片附接材料1520和光学传感器1508包封在嵌入式基板1504上方。
包覆模制件1506的顶表面1516被示出为在接合引线1522上方,这意味着竖直延伸的边界1512竖直延伸超过接合引线1522的顶部直至顶表面1516,以便形成感测窗口1510和完全包封接合引线1522的包覆模制件1506。重新分布焊盘1526可以电联接到重新分布线1528和导电柱1530。
导电柱1530可以延伸穿过嵌入式基板1904的基板包封件1532。基板包封件1532可以是类似于上述包覆模制件1506的包封件的环氧树脂包封件。如将理解,导电柱1530可以沿竖直轴线形成以用于沿竖直轴线在不同点处连接导电部件。重新分布线1528可以沿水平轴线形成以用于沿水平轴线在不同点处连接导电部件。
重新分布线1528可以从嵌入式芯片1538的嵌入式芯片有源侧1536扇出密集输入-输出阵列1534。嵌入式芯片1538可以是用于为光学传感器1508提供模拟前端的专用集成电路。
嵌入式芯片1538可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片1538可以提供可配置且灵活的电子功能块,并且在嵌入式基板1504中提供硬件模块化。
嵌入式芯片有源侧1536可以是嵌入式芯片1538的其上形成有诸如二极管和晶体管等有源部件的一侧。嵌入式芯片有源侧1536被示例性地描绘为朝向光学传感器模块1502面向上。
嵌入式芯片1538可以直接接触地附连到晶片焊盘1540。晶片焊盘1540可以在嵌入式基板1504的制造过程期间为嵌入式芯片1538提供结构稳定性,以及提供导热散热片以将热量吸出并使其背离嵌入式芯片1538。基板包封件1532被描绘为包封导电柱1530、重新分布线1528、嵌入式芯片1538以及晶片焊盘1540的部分。
重新分布线1528被示出为从基板包封件1532完全包封,从而仅使下方凸块材料1544从其暴露。下方凸块材料1544可以支持外部互连件的形成以用于将封装系统1500连接到外部部件。
现在参考图16,其中示出了图15的封装系统1500在光敏材料剥离制造阶段之后的横截面视图。图15的光敏材料1518已从光学传感器1508的有源光学侧1514剥离,并且现在被描绘为从包覆模制件1506的竖直延伸的边界1512之间暴露。
现在参考图17,其中示出了第四实施例中的封装系统1700在模制制造阶段之后的横截面视图。封装系统1700被描绘为具有形成在嵌入式基板1704上方的光学传感器模块1702。光学传感器模块1702可以包括部分包封光学传感器1708的包覆模制件1706。
光学传感器1708从包覆模制件1706的感测窗口1710内暴露。感测窗口1710可以使光学传感器1708在竖直延伸的边界1712之间暴露。竖直延伸的边界1712可以从光学传感器1708的有源光学侧1714延伸到包覆模制件1706的顶表面1716。
包覆模制件1706可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件1706以形成围绕感测窗口1710的竖直延伸的边界1712,从而使有源光学侧1714透过其中暴露。
光学传感器1708可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。替代性地设想,例如,在不偏离所披露的封装系统100的情况下,可以实施多个光传感器和光源。
有源光学侧1714可以是光学传感器1708的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧1714被描绘为沿与包覆模制件1706的顶表面1716相同的方向面向上。替代性地设想,例如当光学传感器1708被配置用于感测传播通过光学传感器1708的主体材料的较长波长时,光学传感器1708可以包括朝向嵌入式基板1704面向下的有源光学侧1714。
顶表面1716可以是平行于光学传感器1708的有源光学侧1714的平坦表面。围绕感测窗口1710的竖直延伸的边界1712被示例性地描绘为竖直向上背离有源光学侧1714延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器1708的中心或背离光学传感器1708的中心成一定角度延伸的竖直延伸的边界1712。
竖直延伸的边界1712可以形成在光学传感器1708的顶部上、与有源光学侧1714直接接触。可以形成与竖直延伸的边界108和光学传感器104的有源光学侧110直接接触的光敏材料保护层1718。
例如,光敏材料1718可以被图案化以覆盖光学传感器104的光敏区域。出于本申请的目的,光敏材料1718被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料1718)涂布基板来开始在光刻工艺过程中涂覆光敏材料1718的过程。然后可以将图案化掩模涂覆到光敏材料1718的表面以便阻挡光,使得只有光敏材料的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料1718的部分。
光敏材料1718通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料1718是正性光敏材料时,光敏材料被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光敏材料1718是负性光敏材料时,光敏材料通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。
有源光学侧1714可以通过接合引线1722电联接到嵌入式基板1704,该接合引线从光学传感器1708的有源光学侧1714上的传感器焊盘1724延伸到嵌入式基板1704。有源光学侧1714可以通过接合引线1722电联接到嵌入式基板1704,该接合引线从光学传感器1708的有源光学侧1714上的传感器焊盘1724延伸到嵌入式基板1704。
替代性地设想,当光学传感器1708具有朝向嵌入式基板1704面向下的有源光学侧1714时,接合引线1722可以用球形接合件来代替。光学传感器1708可以通过晶片附接材料1728来附连到嵌入式芯片1726。晶片附接材料1728可以是引线上膜晶片附接粘合剂(film-over-wire die attach adhesive),从而允许嵌入式芯片1726联接到嵌入式基板204,其中嵌入式芯片接合引线1730延伸穿过晶片附接材料1728。
嵌入式芯片1726可以通过嵌入式芯片晶片附接粘合剂1732来附连到嵌入式基板1704。包覆模制件1706被示出为将接合引线1722、嵌入式芯片接合引线1730、嵌入式芯片晶片附接粘合剂1732、晶片附接材料1728和光学传感器1708包封在嵌入式基板1704上方。
包覆模制件1706的顶表面1716被示出为在接合引线1722上方,这意味着竖直延伸的边界1712竖直延伸超过接合引线1722的顶部直至顶表面1716,以便形成感测窗口1710和完全包封接合引线1722的包覆模制件1706。
嵌入式芯片1726可以是用于为光学传感器1708提供模拟前端的专用集成电路。嵌入式芯片1738可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片1726可以提供可配置且灵活的电子功能块,并且在嵌入式基板1704中提供硬件模块化。
现在参考图18,其中示出了图17的封装系统1700在光敏材料剥离制造阶段之后的横截面视图。图17的光敏材料1718已从光学传感器1708的有源光学侧1714剥离,并且现在被描绘为从包覆模制件1706的竖直延伸的边界1712之间暴露。
现在参考图19,其中示出了第五实施例中的封装系统1900的横截面视图。封装系统1900被描绘为具有形成在嵌入式基板1904上方的光学传感器模块1902。光学传感器模块1902可以包括部分包封光学传感器1908的包覆模制件1906。
光学传感器1908从包覆模制件1906的感测窗口1910内暴露。感测窗口1910可以使光学传感器1908在竖直延伸的边界1912之间暴露。竖直延伸的边界1912可以从光学传感器1908的有源光学侧1914延伸到包覆模制件1906的顶表面1916。
包覆模制件1906可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件1906以形成围绕感测窗口1910的竖直延伸的边界1912,从而使有源光学侧1914透过其中暴露。
光学传感器1908可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。替代性地设想,例如,在不偏离所披露的封装系统100的情况下,可以实施多个光传感器和光源。
有源光学侧1914可以是光学传感器1908的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧1914被描绘为沿与包覆模制件1906的顶表面1916相同的方向面向上。替代性地设想,例如当光学传感器1908被配置用于感测传播通过光学传感器1908的主体材料的较长波长时,光学传感器1908可以包括朝向嵌入式基板1904面向下的有源光学侧1914。
顶表面1916可以是平行于光学传感器1908的有源光学侧1914的平坦表面。围绕感测窗口1910的竖直延伸的边界1912被示例性地描绘为竖直向上背离有源光学侧1914延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器1908的中心或背离光学传感器1908的中心成一定角度延伸的竖直延伸的边界1912。竖直延伸的边界1912可以形成在光学传感器1908的顶部上、形成为在有源光学侧1914的拐角边缘处终止并且形成为与有源光学侧1914直接接触。
光学传感器1908的有源光学侧1914可以通过接合引线1922电联接到嵌入式基板1904,该接合引线从光学传感器1908的有源光学侧1914上的传感器焊盘1924延伸到从嵌入式基板1904暴露的重新分布焊盘1926。
替代性地设想,当光学传感器1908具有朝向嵌入式基板1904面向下的有源光学侧1914时,接合引线1922可以用传感器焊盘1924与重新分布焊盘1926之间的球形接合件来代替。包覆模制件1906被示出为将接合引线1922和光学传感器1908包封在嵌入式基板1904上方。
包覆模制件1906的顶表面1916被示出为在接合引线1922上方,这意味着竖直延伸的边界1912竖直延伸超过接合引线1922的顶部直至顶表面1916,以便形成感测窗口1910和完全包封接合引线1922的包覆模制件1906。重新分布焊盘1926可以电联接到重新分布线1928,它们之间存在导电柱1930。导电柱1930可以从重新分布焊盘1926延伸穿过嵌入式基板1904的基板包封件1932到达重新分布线1928。
基板包封件1932可以是类似于上述包覆模制件502的包封件的环氧树脂包封件。如将理解,导电柱1930可以沿竖直轴线形成以用于沿竖直轴线在不同点处连接导电部件。重新分布线1928可以沿水平轴线形成以用于沿水平轴线在不同点处连接导电部件。
重新分布线1928可以从嵌入式芯片1938的嵌入式芯片有源侧1936扇出密集输入-输出阵列1934。嵌入式芯片1938可以是用于为光学传感器1508提供模拟前端的专用集成电路。
嵌入式芯片1938可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片1938可以提供可配置且灵活的电子功能块,并且在嵌入式基板1904中提供硬件模块化。
嵌入式芯片有源侧1936可以是嵌入式芯片1938的其上形成有诸如二极管和晶体管等有源部件的一侧。嵌入式芯片有源侧1936被示例性地描绘为朝向重新分布线1928和嵌入式基板1904的底部面向下。
嵌入式芯片1938可以直接物理接触地附连到晶片焊盘1940。晶片焊盘1940可以从基板包封件1932暴露,从而允许光学传感器1908与晶片焊盘1940直接物理接触。
晶片焊盘1940可以在嵌入式基板1904的制造过程期间为嵌入式芯片1938提供结构稳定性,以及提供导热散热片以将热量吸出并使其背离嵌入式芯片1938和光学传感器1908。基板包封件1932被描绘为包封导电柱1930、重新分布线1928、嵌入式芯片1938以及晶片焊盘1940的部分。
重新分布线1928被示出为由基板包封件1932的两部分完全包封,从而仅使下方凸块材料1944从其暴露。下方凸块材料1944可以支持外部互连件的形成以用于将封装系统1900连接到外部部件。
现在参考图20,其中示出了图19的封装系统1900在接合焊盘形成制造阶段之后的横截面视图。封装系统1900的重新分布焊盘1926被描绘为形成在支架2002的顶部上。设想重新分布焊盘1926可以通过电镀、物理气相沉积、化学气相沉积或其组合形成。
现在参考图21,其中示出了图19的封装系统1900在粘合剂涂覆制造阶段之后的横截面视图。晶片附接材料1920被示出为沉积在支架2002上、在重新分布焊盘1926之间。
现在参考图22,其中示出了图19的封装系统1900在基板晶片放置制造阶段之后的横截面视图。可以看到嵌入式芯片1938安装到晶片附接材料1920。进一步,嵌入式芯片1938的输入-输出阵列1934被描绘为具有形成在其上的导电焊盘2202。
现在参考图23,其中示出了图19的封装系统1900在柱形成制造阶段之后的横截面视图。可以看到导电柱1930从附接到支架2002的重新分布焊盘1926向上且在嵌入式芯片1938之间延伸。
现在参考图24,其中示出了图19的封装系统1900在第一基板模具打磨制造阶段之后的横截面视图。可以看到基板包封件1932包封导电柱1930和嵌入式芯片1938。可以通过将基板包封件1932与导电柱1930一起打磨以形成平坦表面来将基板包封件1932与导电柱1930形成为平坦表面。
现在参考图25,其中示出了图19的封装系统1900在通孔形成制造阶段之后的横截面视图。基板包封件1932可以被示出为包括穿过其形成的通孔2502,从而暴露嵌入式芯片1938的嵌入式芯片有源侧1936上的导电焊盘2202。可以通过激光蚀刻基板包封件1932来形成通孔2502。
现在参考图26,其中示出了图19的封装系统1900在扇出制造阶段之后的横截面视图。图25的通孔2502被示出为与重新分布线1928的形成一起被填充,该重新分布线与导电柱1930直接接触。进一步,下方凸块材料1942被描绘为形成导电柱1930。
现在参考图27,其中示出了图19的封装系统1900在第二基板模具打磨制造阶段之后的横截面视图。可以看到基板包封件1932包封下方凸块材料1942和重新分布线1928。可以通过将基板包封件1932与下方凸块材料1942一起打磨以形成平坦表面来将基板包封件1932与下方凸块材料1942形成为平坦表面。
现在参考图28,其中示出了图19的封装系统1900在去掉支架制造阶段之后的横截面视图。嵌入式基板1904被示出为已从基板包封件1932去除图20的支架2002。
现在参考图29,其中示出了图19的封装系统1900在焊接掩模制造阶段之后的横截面视图。嵌入式基板1904被描绘为具有沉积在其上的焊接掩模2902。焊接掩模2902可以沉积在晶片焊盘1940上、在基板包封件1932上以及在重新分布焊盘1926上。重新分布焊盘1926的部分从焊料掩模2902暴露,使得重新分布焊盘1926的表面可以被完成以用于引线接合。例如,重新分布焊盘1926的表面可以包括通用无电镀镍无电镀钯浸金(ENEPIG)。
现在参考图30,其中示出了图19的封装系统1900在装运制造阶段之后的横截面视图。设想封装系统1900的嵌入式基板1904可以在稳定状态下完成和装运,以便在不同位置处进行后续处理。已发现,可以在装运之前或之后对嵌入式基板1904进行测试,以确保仅使用已知的良好嵌入式基板1904。
现在参考图31,其中示出了图19的封装系统1900在引线接合制造阶段之后的横截面视图。光学传感器1908被描绘为包括沉积在有源光学侧1914上的光敏材料3102。出于本申请的目的,光敏材料3102被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料3102)涂布基板来开始在光刻工艺过程中涂覆光敏材料3102的过程。然后可以将图案化掩模涂覆到光敏材料3102的表面以便阻挡光,使得只有光敏材料的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料3102的部分。
光敏材料3102通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料3102是正性光敏材料时,光敏材料被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光敏材料3102是负性光敏材料时,光敏材料通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。设想光敏材料3102可以是100μm至200μm的干膜,以用于接合引线1922的低回路引线接合。
接合引线1922可以形成为将传感器焊盘1924联接到嵌入式基板1904的重新分布焊盘1926。如将理解,光学传感器1908可以定位成覆盖晶片焊盘1940并且甚至延伸以覆盖重新分布焊盘1926的部分。
现在参考图32,其中示出了图19的封装系统1900在包覆模制制造阶段之后的横截面视图。可以看出包覆模制件1906包封接合引线1922、光学传感器1908以及光敏材料3102的部分。已发现,通过允许使用标准的薄膜辅助传递模制(例如通过利用标准的面板级封装),使用光敏材料3102降低了制造成本、复杂性和工具要求。
现在参考图33,其中示出了图19的封装系统1900在剥离制造阶段之后的横截面视图。图31的光敏材料3102已被剥离,从而显露出从包覆模制件1906的竖直延伸的边界1912暴露的有源光学侧1914。
现在参考图34,其中示出了第六实施例中的封装系统3400的横截面视图。封装系统3400被描绘为具有形成在嵌入式基板3404上方的光学传感器模块3402。光学传感器模块3402可以包括部分包封光学传感器3408的包覆模制件3406。
光学传感器3408从包覆模制件3406的感测窗口3410内暴露。感测窗口3410可以使光学传感器3408在竖直延伸的边界3412之间暴露。竖直延伸的边界3412可以从光学传感器3408的有源光学侧3414延伸到包覆模制件3406的顶表面3416。
包覆模制件3406可以是包括固体环氧树脂、硬化剂、阻燃剂、填料和其他添加剂的混合物的环氧树脂包封件。可以模制包覆模制件3406以形成围绕感测窗口3410的竖直延伸的边界3412,从而使有源光学侧3414透过其中暴露。
光学传感器3408可以是通过电阻变化检测入射光的变化的光导式传感器、通过输出电压变化检测入射光的光伏电池、通过输出电流变化检测入射光量的光电二极管或其组合。替代性地设想,例如,在不偏离所披露的封装系统100的情况下,可以实施多个光传感器和光源。
有源光学侧3414可以是光学传感器3408的其上形成有诸如晶体管和二极管等有源部件的一侧。有源光学侧3414被描绘为沿与包覆模制件3406的顶表面3416相同的方向面向上。替代性地设想,例如当光学传感器3408被配置用于感测传播通过光学传感器3408的主体材料的较长波长时,光学传感器3408可以包括朝向嵌入式基板3404面向下的有源光学侧3414。
顶表面3416可以是平行于光学传感器3408的有源光学侧3414的平坦表面。围绕感测窗口3410的竖直延伸的边界3412被示例性地描绘为竖直向上背离有源光学侧3414延伸。
设想替代性实施例可以包括竖直地但朝向光学传感器3408的中心或背离光学传感器3408的中心成一定角度延伸的竖直延伸的边界3412。竖直延伸的边界3412可以形成在光学传感器3408的顶部上、形成为在有源光学侧3414的拐角边缘处终止并且形成为与有源光学侧3414直接接触。
光学传感器3408的有源光学侧3414可以通过接合引线3422电联接到嵌入式基板3404,该接合引线从光学传感器3408的有源光学侧3414上的传感器焊盘3424延伸到从嵌入式基板3404暴露的重新分布焊盘3426。
替代性地设想,当光学传感器3408具有朝向嵌入式基板3404面向下的有源光学侧3414时,接合引线3422可以用传感器焊盘3424与重新分布焊盘3426之间的球形接合件来代替。包覆模制件3406被示出为将接合引线3422和光学传感器3408包封在嵌入式基板3404上方。
包覆模制件3406的顶表面3416被示出为在接合引线3422上方,这意味着竖直延伸的边界3412竖直延伸超过接合引线3422的顶部直至顶表面3416,以便形成感测窗口3410和完全包封接合引线3422的包覆模制件3406。重新分布焊盘3426可以电联接到重新分布线3428,它们之间存在导电柱3430。导电柱3430可以从重新分布焊盘3426延伸穿过嵌入式基板3404的基板包封件3432到达重新分布线3428。
基板包封件3432可以是类似于上述包覆模制件502的包封件的环氧树脂包封件。如将理解,导电柱3430可以沿竖直轴线形成以用于沿竖直轴线在不同点处连接导电部件。重新分布线3428可以沿水平轴线形成以用于沿水平轴线在不同点处连接导电部件。
重新分布线3428可以从嵌入式芯片3438的嵌入式芯片有源侧3436扇出密集输入-输出阵列3434。嵌入式芯片3438可以是用于为光学传感器1508提供模拟前端的专用集成电路。
嵌入式芯片3438可以包括实施灵敏模拟放大器的模拟信号调节电路系统。如将理解,提供呈ASIC形式的嵌入式芯片3438可以提供可配置且灵活的电子功能块,并且在嵌入式基板3404中提供硬件模块化。
嵌入式芯片有源侧3436可以是嵌入式芯片3438的其上形成有诸如二极管和晶体管等有源部件的一侧。嵌入式芯片有源侧3436被示例性地描绘为朝向重新分布线3428和嵌入式基板3404的底部面向下。
嵌入式芯片3438可以直接物理接触地附连到嵌入式晶片附接材料3440。嵌入式晶片附接材料3440可以从基板包封件3432暴露,从而允许光学传感器3408通过晶片附接材料3420联接到嵌入式晶片附接材料3440,晶片附接材料3420与嵌入式晶片附接材料3440直接物理接触。
嵌入式晶片附接材料3440可以在嵌入式基板3404的制造过程期间为嵌入式芯片3438提供结构稳定性,以及提供导热散热片以将热量吸出并使其背离嵌入式芯片3438和光学传感器3408。基板包封件3432被描绘为包封导电柱3430、重新分布线3428、嵌入式芯片3438以及嵌入式晶片附接材料3440的部分。
重新分布线3428被示出为由基板包封件3432的两部分完全包封,从而仅使下方凸块材料3444从其暴露。下方凸块材料3444可以支持外部互连件的形成以用于将封装系统3400连接到外部部件。
现在参考图35,其中示出了图34的封装系统3400在第一支架提供制造阶段之后的横截面视图。其上沉积有临时材料3504的第一支架3502可以被提供用于制造封装系统3400。
现在参考图36,其中示出了图34的封装系统3400在晶种层沉积制造阶段之后的横截面视图。临时材料3504被描绘为具有形成在其上的晶种层3602。晶种层3602可以是导电层,以用于使得能够构造图34的嵌入式基板3404的导电元件。
现在参考图37,其中示出了图34的封装系统3400在通孔形成制造阶段之后的横截面视图。干膜光敏材料3702可以粘附到晶种层3602、暴露并显影以显露出通孔3704。通孔3704被形成为穿过干膜光敏材料3702以暴露晶种层3602。
现在参考图38,其中示出了图34的封装系统3400在柱电镀制造阶段之后的横截面视图。导电柱3430被示出为形成在干膜光敏材料3702的通孔3704内。导电柱3430可以通过电镀或沉积来形成。
现在参考图39,其中示出了图34的封装系统3400在晶种层蚀刻制造阶段之后的横截面视图。图36的晶种层3602已被蚀刻,并且图37的干膜光敏材料3702已从导电柱3430周围以及临时材料3504和第一支架3502上方剥离。
现在参考图40,其中示出了图34的封装系统3400在基板芯片放置制造阶段之后的横截面视图。嵌入式芯片3438被描绘为通过嵌入式晶片附接粘合剂3440来附接到临时材料3504。嵌入式芯片3438进一步被描绘为具有形成在嵌入式芯片3438的输入-输出阵列3434上的导电支柱4002。
现在参考图41,其中示出了图34的封装系统3400在第一基板模制制造阶段之后的横截面视图。基板包封件3432的一部分可以被示出为包封导电柱3430和嵌入式芯片3438。
现在参考图42,其中示出了图34的封装系统3400在扇出图案化制造阶段之后的横截面视图。基板包封件3432已被打磨以确保基板包封件3432与导电柱3430共面。
第二晶种层4202已作为平坦层沉积在基板包封件3432的顶部上、在导电柱3430的顶部上以及在导电支柱4002的顶部上。第二干膜光敏材料4204已被沉积、暴露和显影,以便在第二晶种层4202的顶部上形成图案,并且在导电柱3430与导电支柱4002之间暴露第二晶种层4202的部分。
现在参考图43,其中示出了图34的封装系统3400在扇出电镀制造阶段之后的横截面视图。重新分布线3428被示出为从导电柱3430延伸到导电支柱4002,其中第二干膜光敏材料4204在它们之间。
现在参考图44,其中示出了图34的封装系统3400在剥离制造阶段之后的横截面视图。图42的第二干膜光敏材料4204已从重新分布线3428之间剥离,并且图42的第二晶种层4202已从基板包封件3432的顶部蚀刻掉。
现在参考图45,其中示出了图34的封装系统3400在电介质沉积制造阶段之后的横截面视图。电介质聚酰亚胺4502可以形成在重新分布线3428和基板包封件3432之上,并且可以使重新分布线3428的部分从其暴露。
现在参考图46,其中示出了图34的封装系统3400在第二支架附接制造阶段之后的横截面视图。第二支架4602被示出为通过第二支架临时材料4604附接到电介质聚酰亚胺4502。
现在参考图47,其中示出了图34的封装系统3400在第一支架去除制造阶段之后的横截面视图。图35的第一支架3502以及图35的临时材料3504已被去除,从而暴露嵌入式晶片附接材料3440、导电柱3430的部分以及基板包封件3432。
现在参考图48,其中示出了图34的封装系统3400在光学晶片附接制造阶段之后的横截面视图。光学传感器3408已通过晶片附接材料3420安装到嵌入式基板3404,该晶片附接材料与嵌入式晶片附接材料3440直接接触。
光学传感器3408进一步被描绘为包括沉积在有源光学侧3414上的光敏材料4802。出于本申请的目的,光敏材料4802被限定为双态光敏材料,诸如光致抗蚀剂或干膜光致抗蚀剂。
例如,可以通过用光敏有机材料(光敏材料4802)涂布基板来开始在光刻工艺过程中涂覆光敏材料4802的过程。然后可以将图案化掩模涂覆到光敏材料4802的表面以便阻挡光,使得只有光敏材料的未掩蔽区域才会暴露于光。然后可以使用被称为显影剂的溶剂来去除光敏材料4802的部分。
光敏材料4802通常可以具有两种类型,即正性光敏材料和负性光敏材料。当光敏材料4802是正性光敏材料时,光敏材料被光降解并且显影剂将溶解掉暴露于光的区域,从而留下放置有掩模的涂层。
当光敏材料4802是负性光敏材料时,光敏材料通过光、通过聚合或交联来增强,并且显影剂将仅溶解掉未暴露于光的区域,从而在未放置有掩模的区域留下涂层。
现在参考图49,其中示出了图34的封装系统3400在包覆模制制造阶段之后的横截面视图。包覆模制件3406被描绘为形成在接合引线3422、光敏材料4802和光学传感器3408之上。
现在参考图50,其中示出了图34的封装系统3400在第二支架去除制造阶段之后的横截面视图。第二支架4602以及第二支架临时材料4604被示出为与电介质聚酰亚胺4502分离。
现在参考图51,其中示出了图34的封装系统3400在剥离制造阶段之后的横截面视图。图48的光敏材料4802已从感测窗口3410内剥离,从而使光学传感器3408的有源光学侧3414从竖直延伸的边界3412之间暴露。背侧保护带5102已涂覆到嵌入式基板3404的底部。
现在参考图52,其中示出了图34的封装系统3400在切片带附接制造阶段之后的横截面视图。图51的背侧保护带5102已被去除并用嵌入式基板3404下方的切片带5202代替。
现在参考图53,其中示出了图34的封装系统3400在切片制造阶段之后的横截面视图。封装系统3400被示出为单独地切片穿过包覆模制件3406、基板包封件3432、并切到切片带5202中。
现在参考图54,其中示出了用于制造封装系统的制造方法的流程图5400。该制造方法可以包括:在框5402中,提供嵌入式基板,该嵌入式基板包括基板包封件和嵌入式芯片,该嵌入式芯片通过连接在嵌入式芯片与重新分布焊盘之间的重新分布线联接到重新分布焊盘,该基板包封件包封嵌入式芯片和重新分布线;在框5404中,将光敏材料沉积在光学传感器上;在框5406中,使光敏材料的部分暴露于光;在框5408中,使光敏材料显影以去除未覆盖光学传感器的有源光学侧的光敏区域的光敏材料;在框5410中,将光学传感器安装到嵌入式基板;在框5412中,通过从有源光学侧上的传感器焊盘连接到重新分布焊盘的接合引线来将光学传感器引线接合到嵌入式基板;在框5414中,利用包覆模制件来包封光学传感器、接合引线和光敏材料,该包覆模制件形成有与光敏材料的表面共面的顶表面,该包覆模制件围绕光敏材料并围绕光敏区域形成竖直延伸的边界,该包覆模制件形成在接合引线上方,并且该包覆模制件形成为覆盖有源光学侧的部分;在框5416中,将光敏材料从有源光学侧并从竖直延伸的边界之间剥离,从而使有源光学侧从感测窗口内暴露,该感测窗口由竖直延伸的边界定界;以及在框5418中,将包覆模制件和基板包封件切片。
因此,已发现光学传感器封装系统提供了重要且迄今未知且不可用的解决方案、能力和功能方面。所得的配置是简单、经济、不复杂、高度通用、准确、灵敏且有效的,并且可以通过采用已知部件来实施,以用于现成、高效且经济的制造、应用和利用。
虽然已经结合特定的最佳模式描述了光学传感器封装系统,但是应当理解,鉴于先前的描述,许多替代方案、修改和变化对于本领域技术人员来说是显而易见的。因此,旨在涵盖落入所附权利要求范围内的所有此类替代方案、修改和变化。本文阐述或附图中示出的所有主题将以说明性且非限制性的意义解释。

Claims (20)

1.一种制造光学传感器封装系统的方法,其包括:
提供嵌入式基板,该嵌入式基板包括嵌入式芯片,该嵌入式芯片通过连接在该嵌入式芯片与重新分布焊盘之间的重新分布线联接到该重新分布焊盘;
将光学传感器安装到该嵌入式基板,该光学传感器包括形成在该光学传感器的有源光学侧的光敏区域上的光敏材料;
通过从该有源光学侧连接到该重新分布焊盘的第一接合引线来将该光学传感器引线接合到该嵌入式基板;
利用包覆模制件来包封该光学传感器、该第一接合引线和该光敏材料,该包覆模制件形成有与该光敏材料的表面共面的顶表面,该包覆模制件围绕该光敏材料并围绕该光敏区域形成竖直延伸的边界,并且该包覆模制件形成在该第一接合引线上方;以及
将该光敏材料从该有源光学侧并从该竖直延伸的边界之间剥离,从而使该有源光学侧从感测窗口内暴露,该感测窗口由该竖直延伸的边界定界。
2.如权利要求1所述的方法,其进一步包括:
将第二光学传感器安装到该嵌入式基板;
将该第二光学传感器引线接合到该嵌入式基板;并且
其中包封该光学传感器进一步包括利用该包覆模制件来包封该第二光学传感器。
3.如权利要求1所述的方法,其中将该光学传感器安装到该嵌入式基板包括:通过晶片附接材料来将该光学传感器安装到该嵌入式基板。
4.如权利要求1所述的方法,其中引线接合进一步包括:连接将该光学传感器联接到该嵌入式基板的第二接合引线,该第二接合引线形成在该光学传感器的与该第一接合引线的相反侧上。
5.如权利要求1所述的方法,其中安装该光学传感器包括:将该光学传感器安装到该嵌入式基板,其中嵌入式芯片有源侧面向该光学传感器。
6.一种制造光学传感器封装系统的方法,其包括:
提供嵌入式基板,该嵌入式基板包括基板包封件和嵌入式芯片,该嵌入式芯片通过连接在该嵌入式芯片与重新分布焊盘之间的重新分布线联接到该重新分布焊盘,该基板包封件包封该嵌入式芯片和该重新分布线;
将光敏材料沉积在光学传感器上;
使该光敏材料的部分暴露于光;
使该光敏材料显影以去除未覆盖该光学传感器的有源光学侧的光敏区域的该光敏材料;
将该光学传感器安装到该嵌入式基板;
通过从该有源光学侧上的传感器焊盘连接到该重新分布焊盘的接合引线来将该光学传感器引线接合到该嵌入式基板;
利用包覆模制件来包封该光学传感器、该接合引线和该光敏材料,该包覆模制件形成有与该光敏材料的表面共面的顶表面,该包覆模制件围绕该光敏材料并围绕该光敏区域形成竖直延伸的边界,该包覆模制件形成在该接合引线上方,并且该包覆模制件形成为覆盖该有源光学侧的部分;
将该光敏材料从该有源光学侧并从该竖直延伸的边界之间剥离,从而使该有源光学侧从感测窗口内暴露,该感测窗口由该竖直延伸的边界定界;以及
将该包覆模制件和该基板包封件切片。
7.如权利要求6所述的方法,其中沉积该光敏材料包括:沉积通过光降解的正性光敏材料,或通过光增强的负性光敏材料。
8.如权利要求6所述的方法,其中安装该光学传感器包括:通过将该光学传感器联接到该嵌入式芯片的引线上膜晶片附接粘合剂来安装该光学传感器,其中嵌入式芯片接合引线延伸穿过该引线上膜晶片附接粘合剂。
9.如权利要求6所述的方法,其中安装该光学传感器包括:将该光学传感器安装到该嵌入式基板,其中嵌入式芯片有源侧背离该光学传感器。
10.如权利要求6所述的方法,其中将该光学传感器安装到该嵌入式基板包括:将该光学传感器安装到从该嵌入式基板的该基板包封件暴露的晶片焊盘。
11.一种光学传感器封装系统,其包括:
嵌入式基板,该嵌入式基板包括嵌入式芯片,该嵌入式芯片通过连接在该嵌入式芯片与重新分布焊盘之间的重新分布线联接到该重新分布焊盘;
光学传感器,该光学传感器安装到该嵌入式基板,该光学传感器包括形成在该光学传感器的有源光学侧的光敏区域上的光敏材料;
第一接合引线,其将该光学传感器引线接合到该嵌入式基板、从该有源光学侧连接到该重新分布焊盘;以及
包覆模制件,该包覆模制件包封该光学传感器、该第一接合引线和该光敏材料,该包覆模制件形成有与该光敏材料的表面共面的顶表面,该包覆模制件围绕该光敏材料并围绕该光敏区域形成竖直延伸的边界,并且该包覆模制件形成在该第一接合引线上方。
12.如权利要求11所述的系统,其进一步包括安装到该嵌入式基板的第二光学传感器,该第二光学传感器引线接合到该嵌入式基板,并且该第二光学传感器通过该包覆模制件进行包封。
13.如权利要求11所述的系统,其进一步包括晶片附接材料,该晶片附接材料将该光学传感器附连到该嵌入式基板。
14.如权利要求11所述的系统,其进一步包括将该光学传感器联接到该嵌入式基板的第二接合引线,该第二接合引线形成在该光学传感器的与该第一接合引线的相反侧上。
15.如权利要求11所述的系统,其中该嵌入式基板包括面向该光学传感器的嵌入式芯片有源侧。
16.如权利要求11所述的系统,其中:
该嵌入式基板包括基板包封件,该基板包封件包封该嵌入式芯片和该重新分布线;
该光敏材料被图案化,使得该光敏材料覆盖该光学传感器的该有源光学侧的该光敏区域;并且
该第一接合引线从该有源光学侧上的传感器焊盘连接到该重新分布焊盘。
17.如权利要求16所述的系统,其中该光敏材料是通过光降解的正性光敏材料,或通过光增强的负性光敏材料。
18.如权利要求16所述的系统,其进一步包括将该光学传感器联接到该嵌入式芯片的引线上膜晶片附接粘合剂,其中嵌入式芯片接合引线延伸穿过该引线上膜晶片附接粘合剂。
19.如权利要求16所述的系统,该嵌入式基板包括背离该光学传感器的嵌入式芯片有源侧。
20.如权利要求16所述的系统,其进一步包括晶片焊盘,该晶片焊盘从该嵌入式基板的该基板包封件和安装到该嵌入式基板的该光学传感器暴露。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727086B2 (en) * 2018-03-24 2020-07-28 Maxim Integrated Products, Inc. Optical sensor packaging system
TWI705538B (zh) * 2018-06-29 2020-09-21 同欣電子工業股份有限公司 指紋感測封裝模組的製法
US11145782B2 (en) * 2018-12-27 2021-10-12 Texas Instruments Incorporated Processing an optical device
US11004700B2 (en) * 2019-08-21 2021-05-11 Infineon Technologies Ag Temporary post-assisted embedding of semiconductor dies

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393130A (en) * 1982-01-11 1983-07-12 Critikon, Inc. System for encapsulation of semiconductor chips
US20050059188A1 (en) * 2003-09-17 2005-03-17 Bolken Todd O. Image sensor packages and methods of fabrication
CN102365744A (zh) * 2009-02-11 2012-02-29 米辑电子 图像和光传感器芯片封装
CN103512596A (zh) * 2012-06-15 2014-01-15 英特赛尔美国有限公司 晶片级光电子器件封装及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7199438B2 (en) * 2003-09-23 2007-04-03 Advanced Semiconductor Engineering, Inc. Overmolded optical package
TWI384602B (zh) 2008-06-13 2013-02-01 Unimicron Technology Corp 嵌埋有感光半導體晶片之封裝基板及其製法
US8686543B2 (en) * 2011-10-28 2014-04-01 Maxim Integrated Products, Inc. 3D chip package with shielded structures
TWI544423B (zh) 2015-09-02 2016-08-01 原相科技股份有限公司 感測晶片封裝結構及其製造方法
US10727086B2 (en) * 2018-03-24 2020-07-28 Maxim Integrated Products, Inc. Optical sensor packaging system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393130A (en) * 1982-01-11 1983-07-12 Critikon, Inc. System for encapsulation of semiconductor chips
US20050059188A1 (en) * 2003-09-17 2005-03-17 Bolken Todd O. Image sensor packages and methods of fabrication
CN102365744A (zh) * 2009-02-11 2012-02-29 米辑电子 图像和光传感器芯片封装
CN103512596A (zh) * 2012-06-15 2014-01-15 英特赛尔美国有限公司 晶片级光电子器件封装及其制造方法

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