CN110284110A - 一种集成电路pp膜耐湿性控制工艺 - Google Patents
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Abstract
本发明公开了一种集成电路pp膜耐湿性控制工艺,步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至58‑69摄氏度,保持300‑450s,步骤二、转至真空箱,采用1500‑2500目的砂纸对pp膜进行表面挤压处理,挤压压强为35‑65pa。本发明中,对pp膜上的铝膜进行58‑69摄氏度温度软化,然后在真空度为25‑30Pa为真空箱内采用2000目的砂纸采用35‑65pa的压强进行挤压处理,pp膜表层形成密布凹坑状,方便后续涂层附着,转至离子涂层箱中,真空度为40Pa,进行SiO2镀膜,或者进行选取Si和SiO2的混合质量比例为1:3进行镀膜,镀膜时间为14s,镀膜完成后的SiO2镀膜的厚度为80μm,Si和SiO2混合膜厚度为80μm,断面检测致密度高,Si和SiO2可提高PP膜的耐腐蚀性和降低吸水性,电性能方面具有低损耗和低耗电。
Description
技术领域
本发明涉及半导体PP膜耐湿技术领域,尤其涉及一种集成电路pp膜耐湿性控制工艺。
背景技术
在微电子工艺中,通常在半导体的集成电路的上覆盖一层pp膜,然后pp膜表面进行镀金属膜处理,一般是先进行镀铝,然后在铝膜上进行镀锌,然而采用此方式处理的pp薄膜不耐湿,产品在做高温高湿环境下,容易失效,以及镀膜层附着程度差导致出现腐蚀性低,在电性能方面具有高损耗和高耗电的现象。
本发明提供一种集成电路pp膜耐湿性控制工艺。
发明内容
本发明的目的在于:为了解决传统的半导体集成电路pp膜镀金属铝和锌层容易出现pp薄膜不耐湿以及pp薄膜镀膜层附着程度差导致出现腐蚀性低,在电性能方面具有高损耗和高耗电的问题,而提出的一种集成电路pp膜耐湿性控制工艺。
为了实现上述目的,本发明采用了如下技术方案:
步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至58-69摄氏度,保持300-450s;
步骤二、转至真空箱,真空度为25-30Pa,采用1500-2500目的砂纸对pp膜进行表面挤压处理,挤压压强为35-65pa,保压时间为20-35s;
步骤三、转至离子涂层箱中,真空度为30-50Pa,对pp膜上的铝层进行SiO2镀膜,镀膜时间为12-20s;
步骤四、然后进行离子电镀Zn层;
步骤五、检验,采用激光切割,并通过显微设备对断层SiO2镀膜厚度测量。
作为上述技术方案的进一步描述:
根据步骤一,升温箱中,升温度至60摄氏度,保持320s。
作为上述技术方案的进一步描述:
砂纸采用2000目,挤压压强为40pa。
作为上述技术方案的进一步描述:
根据步骤三中,真空度为40Pa,镀膜时间为14s。
作为上述技术方案的进一步描述:
离子涂层箱中还可选用Si进行镀膜或者进行Si和SiO2混合镀膜。
作为上述技术方案的进一步描述:
选取Si和SiO2的混合质量比例为1:3。
综上所述,由于采用了上述技术方案,本发明的有益效果是:
1、本发明中,对pp膜上的铝膜进行58-69摄氏度温度软化,然后在真空度为25-30Pa为真空箱内采用2000目的砂纸采用35-65pa的压强进行挤压处理,pp膜表层形成密布凹坑状,方便后续涂层附着,转至离子涂层箱中,真空度为40Pa,进行SiO2镀膜,或者进行选取Si和SiO2的混合质量比例为1:3进行镀膜,镀膜时间为14s,镀膜完成后的SiO2镀膜的厚度为80μm,Si和SiO2混合膜厚度为80μm,断面检测致密度高,Si和SiO2可提高PP膜的耐腐蚀性和降低吸水性,电性能方面具有低损耗和低耗电。
具体实施方式
下面将结合本发明的实施例,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
实施例1
步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至58-69摄氏度,保持300-450s,此环境下pp膜上的铝膜层软化并处于临界变形状态;
步骤二、转至真空箱,真空度为25-30Pa,采用1500-2500目的砂纸对pp膜进行表面挤压处理,挤压压强为35-65pa,保压时间为20-35s,真空环境排出杂质,此范围砂纸对软化的铝膜挤压后,在铝膜的上表面形成密布的附着深孔,由此有助于SiO2的镀膜附着;
步骤三、转至离子涂层箱中,真空度为30-50Pa,排出砂纸挤压产生的杂质,对pp膜上的铝层进行SiO2镀膜,SiO2可提高PP膜的耐腐蚀性和降低吸水性,镀膜时间为12-20s,此镀膜时间内,SiO2涂层厚度为56-85μm;
步骤四、然后进行离子电镀Zn层;
步骤五、检验,采用激光切割,并通过显微设备对SiO2镀膜厚度的断层进行测量SiO2涂层厚度。
实施例2
步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至60摄氏度,保持320s,此环境下pp膜上的铝膜层软化接近临界变形状态;
步骤二、转至真空箱,真空度为25-30Pa,采用2000目的砂纸对pp膜进行表面挤压处理,挤压压强为40pa,2000目的砂纸,减小挤压后砂纸产生的砂砾脱落,保压时间为20-35s,在铝膜的上表面形成密布的附着深孔,由此有助于SiO2的镀膜附着;
步骤三、转至离子涂层箱中,真空度为40Pa,对pp膜上的铝层进行SiO2镀膜,镀膜时间为14s,此镀膜时间内,SiO2可提高PP膜的耐腐蚀性和降低吸水性,SiO2涂层厚度为80μm,电性能方面具有低损耗和低耗电;
步骤四、然后进行离子电镀Zn层,80μm内SiO2涂层厚度后进行的电镀Zn层表面光洁度质量高;
步骤五、检验,采用激光切割,并通过显微设备对SiO2镀膜厚度断层进行测量,观测断层致密度。
实施例3
步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至60摄氏度,保持320s,此环境下pp膜上的铝膜层软化接近临界变形状态;
步骤二、转至真空箱,真空度为25-30Pa,采用2000目的砂纸对pp膜进行表面挤压处理,挤压压强为40pa,2000目的砂纸,减小挤压后砂纸产生的砂砾脱落,保压时间为20-35s,在铝膜的上表面形成密布的附着深孔,由此有助于SiO2的镀膜附着;
步骤三、转至离子涂层箱中,真空度为40Pa,对pp膜上的铝层进行Si和SiO2混合镀膜,混合质量比例为1:3,镀膜时间为14s。此镀膜时间内,涂层厚度为85μm,电性能方面具有低损耗和低耗电;
步骤四、然后进行离子电镀Zn层,80μm的Si和SiO2混合镀膜涂层厚度后进行的电镀Zn层表面光洁度质量高,Si缓慢氧化转化成SiO2,提高Si和SiO2镀膜涂层的致密性,电性能方面具有低损耗和低耗电;
步骤五、检验,采用激光切割,并通过显微设备对Si和SiO2混合镀膜断层进行测量,观测断层致密度。
以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,根据本发明的技术方案及其发明构思加以等同替换或改变,都应涵盖在本发明的保护范围之内。
Claims (6)
1.一种集成电路pp膜耐湿性控制工艺,其特征在于,包括以下步骤:
步骤一、将带有pp膜的基板的置于升温箱中,并提升温度至58-69摄氏度,保持300-450s;
步骤二、转至真空箱,真空度为25-30Pa,采用1500-2500目的砂纸对pp膜进行表面挤压处理,挤压压强为35-65pa,保压时间为20-35s;
步骤三、转至离子涂层箱中,真空度为30-50Pa,对pp膜上的铝层进行SiO2镀膜,镀膜时间为12-20s;
步骤四、然后进行离子电镀Zn层;
步骤五、检验,采用激光切割,并通过显微设备对断层SiO2镀膜厚度测量。
2.根据权利要求1所述的一种集成电路pp膜耐湿性控制工艺,其特征在于,根据步骤一,升温箱中,升温度至60摄氏度,保持320s。
3.根据权利要求1所述的一种集成电路pp膜耐湿性控制工艺,其特征在于,根据步骤二中,砂纸采用2000目,挤压压强为40pa。
4.根据权利要求1所述的一种集成电路pp膜耐湿性控制工艺,其特征在于,根据步骤三中,真空度为40Pa,镀膜时间为14s。
5.根据权利要求1-4所述的一种集成电路pp膜耐湿性控制工艺,其特征在于,离子涂层箱中还可选用Si进行镀膜或者进行Si和SiO2混合镀膜。
6.根据权利要求5所述的一种集成电路pp膜耐湿性控制工艺,其特征在于,选取Si和SiO2的混合质量比例为1:3。
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CN116200708A (zh) * | 2023-04-12 | 2023-06-02 | 合肥亿米特科技股份有限公司 | 一种基于界面改性提高pvd涂层在高分子材料附着强度的制备方法 |
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CN1254934A (zh) * | 1998-11-23 | 2000-05-31 | 微涂层技术公司 | 薄膜电容器的形成 |
CN206022118U (zh) * | 2016-08-31 | 2017-03-15 | 北京埃德万斯离子束技术研究所股份有限公司 | 薄膜电容器 |
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