CN110246835A - 一种三维集成高压碳化硅模块封装结构 - Google Patents

一种三维集成高压碳化硅模块封装结构 Download PDF

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Publication number
CN110246835A
CN110246835A CN201910428016.5A CN201910428016A CN110246835A CN 110246835 A CN110246835 A CN 110246835A CN 201910428016 A CN201910428016 A CN 201910428016A CN 110246835 A CN110246835 A CN 110246835A
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substrate
driving
metal
high pressure
shell
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CN201910428016.5A
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CN110246835B (zh
Inventor
王来利
侯晓东
赵成
王见鹏
马定坤
杨成子
杨旭
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Xian Jiaotong University
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Xian Jiaotong University
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Priority to CN201910428016.5A priority Critical patent/CN110246835B/zh
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Priority to US16/882,301 priority patent/US11158609B2/en
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Abstract

发明公开了一种三维集成高压碳化硅模块封装结构，其包括自上而下的源极基板、芯片子模块、上驱动端子、上驱动基板、陶瓷外壳、可集成水冷散热器的金属基板、进水口、出水口、芯片子模块、下驱动端子、下驱动基板、漏极基板，其中芯片子模块由驱动连接基板、功率源极金属块、驱动栅极金属柱、驱动栅极金属柱、碳化硅裸片、绝缘结构等组成。采用三维集成结构让回路不收二维布局的局限，寄生参数大幅降低；采用集成水冷散热器的中间基板能保证每层芯片都是双面散热结构，提高模块的散热效率；采用外接解耦电容组，减小电压振荡的同时也不会影响模块内部的可靠性；采用金属平板作为引出端子，能够与现有的电网输变电系统相兼容。

Description

一种三维集成高压碳化硅模块封装结构
技术领域
本发明涉及半导体制造领域，尤其涉及一种三维集成高压碳化硅模块封装结构。
背景技术
以碳化硅和氮化镓为代表的第三代功率半导体器件(即宽禁带功率半导体器件)具有开关速度快，损耗低，工作温度高等特点，其性能远超现有的硅功率半导体器件。目前，在宽禁带功率半导体器件技术逐渐走向成熟的过程中，尤其针对高压碳化硅功率器件的封装，国际上还没有成熟的封装技术。
目前已有的封装结构可以分为两类：基于焊接工艺的封装结构和基于压接工艺的封装结构。基于焊接工艺的封装结构通常在中低压(650～3300V)功率器件的封装中使用，在高压功率器件的封装中应用较少。目前电网用功率模块通常采用基于压接工艺的封装结构。
目前的典型的压接封装结构主要适用于硅功率器件，针对高压碳化硅器件的封装技术尚不成熟，无法保证可靠性、充分发挥高压碳化硅器件的优良性能，并在电网领域得到广泛的应用。
在输配电系统实际应用过程中，经常需要将两个分立的压接模块串联起来形成半桥结构，这样会导致寄生参数高的问题。
发明内容
本发明的目的是针对以上问题，提出一种三维集成高压碳化硅模块封装结构，解决现有封装结构寄生参数大的问题。
为实现以上目的，本发明采用如下技术方案：
一种三维集成高压碳化硅模块封装结构，包括源极基板、外壳、金属基板、漏极基板和驱动层，金属基板设置于外壳内，源极基板和漏极基板分别与外壳的两端密封连接；
驱动层包括第一驱动层和第二驱动层，第一驱动层和第二驱动层结构相同，均包括驱动基板和芯片子模块，驱动基板和芯片子模块构成半桥结构，驱动基板上设置有驱动端子，驱动端子贯穿外壳并伸出于外壳：
芯片子模块包括驱动连接基板、功率源极金属块、驱动栅极金属柱、驱动栅极金属柱、碳化硅裸片和绝缘结构，驱动栅极金属柱的一端和驱动栅极金属柱的一端分别与碳化硅裸片上的栅极和源极烧结，功率源极金属块的一端与碳化硅裸片上的源极烧结，驱动连接基板与驱动栅极金属柱的另一端和驱动栅极金属柱的另一端均烧结，碳化硅裸片的四周设置绝缘结构；
驱动连接基板与驱动基板烧结，功率源极金属块的另一端贯穿驱动基板；
第一驱动层和第二驱动层均设置于外壳内，第一驱动层设置于源极基板与金属基板之间，第一驱动层的功率源极金属块的另一端与源极基板烧结，第一驱动层的碳化硅裸片的漏极与金属基板烧结；
第二驱动层设置于漏极基板与金属基板之间，第二驱动层的功率源极金属块的另一端与金属基板烧结，第二驱动层的碳化硅裸片的漏极与漏极基板烧结。
金属基板内部设置有水冷通道，水冷通道上连接有进水口和出水口，进水口和出水口贯穿外壳并伸出于外壳。
源极基板和漏极基板时间连接有解耦电容。
解耦电容设置于外壳的外部，解耦电容包括电容基板和设置于电容基板上的高压电容，高压电容的两极分别与源极基板和漏极基板连接，电容基板和高压电容包覆于绝缘层内。
高压电容设置多个，且多个高压电容之间相互串联，多个高压电容串联后的两极分别与源极基板和漏极基板连接。
驱动栅极金属柱和驱动栅极金属柱均位于功率源极金属块的同一侧。
驱动连接基板上开设有通孔，驱动连接基板通过通孔套设在功率源极金属块上，驱动连接基板与功率源极金属块之间留有间隙。
驱动栅极金属柱和驱动栅极金属柱的高度相同。
所述烧结为纳米银烧结。
所述外壳为陶瓷外壳。
本发明具有如下有益效果：
本发明三维集成高压碳化硅模块封装结构中，芯片子模块的驱动栅极金属柱的一端和驱动栅极金属柱的一端分别与碳化硅裸片上的栅极和源极烧结，功率源极金属块的一端与碳化硅裸片上的源极烧结，驱动连接基板与驱动栅极金属柱的另一端和驱动栅极金属柱的另一端均烧结，由于本发明的芯片子模块采用了上述结构，使得芯片子模块的驱动连接基板与驱动基板能够进行烧结，驱动连接基板与驱动基板能够进行烧结，第一驱动层的功率源极金属块的另一端能够与源极基板烧结，第一驱动层的碳化硅裸片的漏极能够与金属基板烧结，第二驱动层的功率源极金属块的另一端能够与金属基板烧结，第二驱动层的碳化硅裸片的漏极能够与漏极基板烧结，首先由于采用了烧结连接的方式，因此能够降低整个三维集成高压碳化硅模块封装结构的寄生参数。其次，本发明的三维集成高压碳化硅模块封装结构中，采用三维集成半桥结构，能够让回路不受二维布局的局限性，与焊接结构相比，寄生参数大幅降低，与压接型结构相比模块内部寄生参数相当。其次，本发明中采用了烧结连接，烧结层具有低温烧结、高熔点、高热导率的特点，对热机械疲劳的抵抗力较强，大大提高了模块在苛刻应用环境下的长期可靠性，避免了传统压接模块中由于温度分布不均导致压力无法均匀分布降低组件连接可靠性的问题。本发明的子模块结构是一种新型子模块结构，在芯片子模块上设置了功率源极金属块及驱动金属柱(即驱动栅极金属柱和驱动栅极金属柱)，通过功率源极金属块及驱动金属柱上的平面与其他部件烧结，确保了在芯片子模块面积很小的情况下的安装精度，同时驱动电路的驱动栅极金属柱与功率回路的功率源极金属块相互分离，因此能够减小芯片子模块源极寄生电感对驱动回路的影响，也即实现了驱动回路的卡尔文连接，提高驱动的可靠性。
进一步的，金属基板内部设置有水冷通道，因此能够保证每一层芯片都具有双面散热条件。
进一步的，源极基板和漏极基板时间连接有解耦电容，解耦电容能够降低母线和金属基板寄生电感对模块开关的影响、减小电压振荡。
进一步的，解耦电容设置于外壳的外部，因此能够使解耦电容独立于模块封装之外，能够根据需要选择是否安装，亦可单独替换，不会降低模块内部的可靠性。
进一步的，驱动栅极金属柱和驱动栅极金属柱均位于功率源极金属块的同一侧，使得片子模块的结构更加紧凑。
附图说明
图1为本发明三维集成高压碳化硅模块封装结构的分解示意图；
图2为本发明三维集成高压碳化硅模块封装结构组装过程示意图；
图3为本发明图2中A-A截面剖视图；
图4为本发明解耦电容的结构示意图；
图5为本发明一实施例的三维集成高压碳化硅模块封装结示意图；
图6为本发明芯片子模块的结构示意图；
图7为本发明芯片子模块的组装过程示意图；
图8为本发明芯片子模块的结构示意图。
图中：1-源极基板，2-第一驱动端子，3-外壳，4-第二驱动端子，5-漏极基板，6-第一驱动基板，7-第一芯片子模块，8-金属基板，9-进水口，10-出水口，11-第二驱动基板，12-第二芯片子模块，13-解耦电容，14-绝缘层，15-高压电容，16-电容基板，17-连接插头，18-半桥上开关，19-半桥下开关，20-驱动连接基板，21-功率源极金属块，22-驱动栅极金属柱，23-驱动栅极金属柱，24-碳化硅裸片，24-1-栅极，24-2-源极，24-3-漏极，25-绝缘结构，26-纳米银烧结点。
具体实施方式
为了使本领域技术人员更好地理解本发明的技术方案，下面结合附图对本发明进行详细描述，本部分的描述仅是示范性和解释性，不应对本发明的保护范围有任何的限制作用。
如图1、图2和图3所示，本发明的三维集成高压碳化硅模块封装结构，包括源极基板1、外壳3、金属基板8、漏极基板5和驱动层，金属基板8设置于外壳3内，源极基板1和漏极基板5分别与外壳3的两端密封连接；驱动层包括第一驱动层和第二驱动层，第一驱动层和第二驱动层结构相同，均包括驱动基板和芯片子模块，驱动基板和芯片子模块构成半桥结构，驱动基板上设置有驱动端子，驱动端子贯穿外壳3并伸出于外壳3：如图6～图8所示，芯片子模块包括驱动连接基板20、功率源极金属块21、驱动栅极金属柱22、驱动栅极金属柱23、碳化硅裸片24和绝缘结构25，以图1和图2中显示的方位为例，驱动栅极金属柱22的和驱动栅极金属柱23的下端分别与碳化硅裸片24上的栅极24-1和源极24-2烧结，功率源极金属块21的下端与碳化硅裸片24上的源极24-2烧结，驱动连接基板20与驱动栅极金属柱22和驱动栅极金属柱23的上端均烧结，碳化硅裸片24的四周设置绝缘结构25；驱动连接基板20的上表面与驱动基板的下表面烧结，功率源极金属块21的上端贯穿驱动基板；第一驱动层和第二驱动层均设置于外壳3内，第一驱动层设置于源极基板1与金属基板8之间，第一驱动层的功率源极金属块21的上端与源极基板1烧结，第一驱动层的碳化硅裸片24的漏极24-3与金属基板8烧结；第二驱动层设置于漏极基板5与金属基板8之间，第二驱动层的功率源极金属块21的上端与金属基板8烧结，第二驱动层的碳化硅裸片24的漏极24-3与漏极基板5烧结。源极基板1和漏极基板5均为金属基板，采用金属平板作为引出端子，能够与现有的电网输变电系统相兼容。
参照图3，本发明的三维集成高压碳化硅模块封装结构中，将在各个芯片子模块的驱动连接在一个驱动基板上就形成驱动层，一个驱动层就是一个半桥开关，图1～图3中所示，上部的驱动层构成半桥上开关18，下部的驱动层构成半桥下开关19。再将半桥上开关18中所有所有芯片子模块的功率源极金属块通过纳米银烧结和顶层的源极基板1连接，然后将半桥上开关18中所有芯片子模块中碳化硅裸片的漏极烧结在同一块金属基板8上形成漏极层，半桥下开关19的功率源极金属块烧结在中间的金属基板8上，半桥下开关19中碳化硅裸片的漏极烧结在最底部的漏极基板，最后在模块外部加装外壳。
作为本发明优选的实施方案，金属基板8可集成水冷散热器，金属基板8内部设置有水冷通道，水冷通道上连接有进水口9和出水口10，进水口9和出水口10贯穿外壳3并伸出于外壳3。
如图2和图5所示，作为本发明优选的实施方案，本发明的三维集成高压碳化硅模块封装结构可根据需要外接解耦电容13，解耦电容13通过基板插孔和源极基板1以及漏极基板5连接，必要时可通过螺丝加固解耦电容13，这样在保证封装结构内部的可靠性不受影响的前提下降低了母线和水冷散热器寄生电感对模块开关的影响。
如图4和图5所示，作为本发明优选的实施方案，解耦电容13设置于外壳3的外部，根据需要，外壳3的外部可连接多个解耦电容13，每个解耦电容13包括电容基板16和设置于电容基板16上的高压电容15，高压电容15的两极分别与源极基板1和漏极基板5连接，电容基板16和高压电容15包覆于绝缘层14内，其中绝缘层14保障了解耦电容在高压应用中的绝缘等级，电容基板16上设置了可以和源极基板1和漏极基板5连接的连接插头17。
如图4所示，作为本发明优选的实施方案，每个解耦电容13中，高压电容15设置多个，且多个高压电容15之间相互串联，多个高压电容15串联后的两极分别与源极基板1和漏极基板5连接。
参照图6～图8，本发明中，驱动栅极金属柱22和驱动栅极金属柱23均位于功率源极金属块21的同一侧。驱动连接基板20上开设有通孔，驱动连接基板20通过通孔套设在功率源极金属块21上，驱动连接基板20与功率源极金属块21之间留有间隙。驱动栅极金属柱22和驱动栅极金属柱23的高度相同。所述烧结为纳米银烧结。外壳3为陶瓷外壳。
本发明的三维集成高压碳化硅模块封装结构采用三维集成半桥结构；在该结构中可根据功率等级与散热需求选择将水冷散热器集成在中间基板上；并在此基础上提出外接独立于模块之外的解耦电容组。本发明采用纳米银烧结平面互联工艺，降低了模块寄生参数，同时纳米银烧结层具有低温烧结，高熔点，高热导率的特点，对热机械疲劳的抵抗力较强，大大提高了模块在苛刻应用环境下的长期可靠性，避免了传统压接模块中由于温度分布不均导致压力无法均匀分布降低组件连接可靠性的问题。本发明在芯片终端添加高绝缘强度材料的绝缘结构25，保证芯片的耐压能力。与现有技术相比：
1.本发明采用三维集成半桥结构，能够让回路不受二维布局的局限性，与焊接结构相比寄生参数大幅降低，与压接型结构相比模块内部寄生参数相当。
2.本发明可根据功率等级和散热需求选择在中间的金属基板8上集成水冷散热器，保证每一层芯片都具有双面散热条件。
3.本发明提出在源极基板1和漏极基板5侧边安装解耦电容组，不但可以降低母线和金属基板寄生电感对模块开关的影响、减小电压振荡，同时还使解耦电容组独立于模块封装之外，可根据需要选择是否安装，亦可单独替换，不会降低模块内部的可靠性。
4.本发明主要应用于高压电网中，其封装结构和电网现有的输变电系统相兼容。

Claims (9)

1.一种三维集成高压碳化硅模块封装结构，其特征在于，包括源极基板(1)、外壳(3)、金属基板(8)、漏极基板(5)和驱动层，金属基板(8)设置于外壳(3)内，源极基板(1)和漏极基板(5)分别与外壳(3)的两端密封连接；
驱动层包括第一驱动层和第二驱动层，第一驱动层和第二驱动层结构相同，均包括驱动基板和芯片子模块，驱动基板和芯片子模块构成半桥结构，驱动基板上设置有驱动端子，驱动端子贯穿外壳(3)并伸出于外壳(3)：
芯片子模块包括驱动连接基板(20)、功率源极金属块(21)、驱动栅极金属柱(22)、驱动栅极金属柱(23)、碳化硅裸片(24)和绝缘结构(25)，驱动栅极金属柱(22)的一端和驱动栅极金属柱(23)的一端分别与碳化硅裸片(24)上的栅极(24-1)和源极(24-2)烧结，功率源极金属块(21)的一端与碳化硅裸片(24)上的源极(24-2)烧结，驱动连接基板(20)与驱动栅极金属柱(22)的另一端和驱动栅极金属柱(23)的另一端均烧结，碳化硅裸片(24)的四周设置绝缘结构(25)；
驱动连接基板(20)与驱动基板烧结，功率源极金属块(21)的另一端贯穿驱动基板；
第一驱动层和第二驱动层均设置于外壳(3)内，第一驱动层设置于源极基板(1)与金属基板(8)之间，第一驱动层的功率源极金属块(21)的另一端与源极基板(1)烧结，第一驱动层的碳化硅裸片(24)的漏极(24-3)与金属基板(8)烧结；
第二驱动层设置于漏极基板(5)与金属基板(8)之间，第二驱动层的功率源极金属块(21)的另一端与金属基板(8)烧结，第二驱动层的碳化硅裸片(24)的漏极(24-3)与漏极基板(5)烧结。
2.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，金属基板(8)内部设置有水冷通道，水冷通道上连接有进水口(9)和出水口(10)，进水口(9)和出水口(10)贯穿外壳(3)并伸出于外壳(3)。
3.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，源极基板(1)和漏极基板(5)时间连接有解耦电容(13)。
4.根据权利要求3所述的一种三维集成高压碳化硅模块封装结构，其特征在于，解耦电容(13)设置于外壳(3)的外部，解耦电容(13)包括电容基板(16)和设置于电容基板(16)上的高压电容(15)，高压电容(15)的两极分别与源极基板(1)和漏极基板(5)连接，电容基板(16)和高压电容(15)包覆于绝缘层(14)内。
5.根据权利要求4所述的一种三维集成高压碳化硅模块封装结构，其特征在于，高压电容(15)设置多个，且多个高压电容(15)之间相互串联，多个高压电容(15)串联后的两极分别与源极基板(1)和漏极基板(5)连接。
6.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，驱动栅极金属柱(22)和驱动栅极金属柱(23)均位于功率源极金属块(21)的同一侧。
7.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，驱动连接基板(20)上开设有通孔，驱动连接基板(20)通过通孔套设在功率源极金属块(21)上，驱动连接基板(20)与功率源极金属块(21)之间留有间隙。
8.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，驱动栅极金属柱(22)和驱动栅极金属柱(23)的高度相同。
9.根据权利要求1所述的一种三维集成高压碳化硅模块封装结构，其特征在于，所述烧结为纳米银烧结。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114021505A (zh) * 2022-01-06 2022-02-08 青岛展诚科技有限公司 集成电路FinFET复杂三维结构描述文件的生成方法和系统
CN114152850A (zh) * 2020-08-19 2022-03-08 华中科技大学 一种用于功率模块开关性能测试的动态测试装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114141744A (zh) * 2021-10-15 2022-03-04 西安交通大学 一种SiC MOSFET子模组单元压接型封装
CN115132713B (zh) * 2022-07-07 2023-02-17 杭州谱析光晶半导体科技有限公司 一种三维空间排布器件的功率半导体封装模块结构及制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4336205B2 (ja) * 2004-01-05 2009-09-30 三菱電機株式会社 パワー半導体モジュール
US8134236B2 (en) * 2006-07-05 2012-03-13 Infineon Technologies, Ag Electronic module with switching functions and method for producing the same
US8946882B2 (en) * 2012-03-15 2015-02-03 Denso Corporation Semiconductor module and semiconductor device
CN109314087A (zh) * 2017-05-19 2019-02-05 新电元工业株式会社 电子模块、连接体的制造方法以及电子模块的制造方法
EP2546874B1 (en) * 2011-07-11 2020-03-04 Infineon Technologies Americas Corp. Stacked Half-Bridge Power Module

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5067267B2 (ja) * 2008-06-05 2012-11-07 三菱電機株式会社 樹脂封止型半導体装置とその製造方法
JP5115632B2 (ja) * 2010-06-30 2013-01-09 株式会社デンソー 半導体装置
CN102148169B (zh) 2011-01-04 2012-12-12 株洲南车时代电气股份有限公司 碳化硅功率模块的封装方法及碳化硅功率模块
CN105914185B (zh) 2016-06-21 2018-07-31 华中科技大学 一种碳化硅功率器件的封装结构及封装方法
CN108682655B (zh) 2018-05-17 2020-01-17 江苏芯澄半导体有限公司 一种宽禁带半导体碳化硅功率模块高温封装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4336205B2 (ja) * 2004-01-05 2009-09-30 三菱電機株式会社 パワー半導体モジュール
US8134236B2 (en) * 2006-07-05 2012-03-13 Infineon Technologies, Ag Electronic module with switching functions and method for producing the same
EP2546874B1 (en) * 2011-07-11 2020-03-04 Infineon Technologies Americas Corp. Stacked Half-Bridge Power Module
US8946882B2 (en) * 2012-03-15 2015-02-03 Denso Corporation Semiconductor module and semiconductor device
CN109314087A (zh) * 2017-05-19 2019-02-05 新电元工业株式会社 电子模块、连接体的制造方法以及电子模块的制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114152850A (zh) * 2020-08-19 2022-03-08 华中科技大学 一种用于功率模块开关性能测试的动态测试装置
CN114021505A (zh) * 2022-01-06 2022-02-08 青岛展诚科技有限公司 集成电路FinFET复杂三维结构描述文件的生成方法和系统

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