CN110148595A - 功率半导体元件 - Google Patents
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- 239000004020 conductor Substances 0.000 description 31
- 238000000034 method Methods 0.000 description 18
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Abstract
本发明提供一种功率半导体元件,包括衬底定义有有源区与终端区。有源区具有多个第一沟槽。终端区具有第二沟槽。多个第一沟槽沿第一方向延伸且沿第二方向排列。第二沟槽沿第二方向延伸。第一方向与第二方向相交。第二沟槽具有多个突出部,分别位于两相邻的第一沟槽之间。上述功率半导体元件可在一定的元件尺寸下提升功率半导体元件的击穿电压。
Description
技术领域
本发明是有关于一种半导体元件,且特别是有关于一种功率半导体元件。
背景技术
功率半导体元件是一种广泛使用在模拟电路的半导体元件。由于功率半导体元件具有非常低的导通电阻与非常快的切换速度,因此,功率半导体元件可应用在电源切换(Power switch)电路上,使得电源管理技术(power management techniques)更有效率。
随着科技进步,电子元件朝着轻薄化的趋势发展。由于电子元件的尺寸不断地缩小,维持功率半导体元件的高击穿电压(Breakdown voltage)也愈发困难。因此,如何在一定的元件尺寸下提升功率半导体元件的击穿电压将成为重要的一门课题。
发明内容
本发明提供一种功率半导体元件,其可均匀化有源区与终端区之间的电力线的分布,以提升元件的击穿电压,进而提升功率半导体元件的可靠度。
本发明提供一种功率半导体元件,包括衬底定义有有源区与终端区。有源区具有多个第一沟槽。终端区具有第二沟槽。多个第一沟槽沿第一方向延伸且沿第二方向排列。第二沟槽沿第二方向延伸。第一方向与第二方向相交。第二沟槽具有多个突出部,分别位于两相邻的第一沟槽之间。
在本发明的一实施例中,各所述多个突出部具有中心点(central point),其位于所对应的两相邻的所述第一沟槽之间的中心线(center line)上。
在本发明的一实施例中,所述第一沟槽中的一者具有第一转角部(corner part)。第一沟槽中的另一者相邻于所述第一沟槽中的所述一者且具有第二转角部。所述第一转角部与所对应的中心点之间具有第一距离。所述第二转角部与所对应的所述中心点之间具有第二距离。所述第一距离等于所述第二距离。
在本发明的一实施例中,所述多个突出部自所述衬底的顶面延伸至所述衬底中。
在本发明的一实施例中,各所述多个第一沟槽包括条状部与两个延伸部。条状部具有沿着所述第一方向的相对两端。两个延伸部分别配置于所述条状部的所述两端上。
本发明提供一种功率半导体元件,包括衬底定义有有源区与终端区。有源区具有多个第一沟槽。终端区具有第二沟槽。多个第一沟槽沿第一方向延伸且沿第二方向排列。第二沟槽沿第二方向延伸。第一方向与第二方向相交。各所述第一沟槽包括条状部与两个延伸部。所述两个延伸部分别配置在所述条状部的相对两端上。
在本发明的一实施例中,所述两个延伸部覆盖所述条状部的所述两端的两角落。
在本发明的一实施例中,所述两个延伸部与所述条状部的所述两端为共平面。
在本发明的一实施例中,所述两个延伸部完全覆盖所述条状部的所述两端的表面。
在本发明的一实施例中,所述延伸部彼此分离。
基于上述,本发明通过在终端区的第二沟槽中配置多个突出部,使其分别位于有源区的两相邻的第一沟槽之间。此配置可调整或缩短有源区的第一沟槽与终端区的第二沟槽之间的距离,以均匀化电力线的分布,进而提升功率半导体元件的击穿电压,并提升功率半导体元件的可靠度。
此外,本发明也可在有源区的第一沟槽的条状部的相对两端上配置两个延伸部,以均匀化有源区与终端区之间的电力线的分布,进而提升功率半导体元件的击穿电压。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1是本发明的第一实施例的一种功率半导体元件的上视示意图。
图2A是图1的区域A的放大示意图。
图2B是图2A的区域B的放大示意图。
图2C是图2B的区域C的放大立体示意图。
图3A与图3B分别是图1的区域A的放大示意图。
图4是图1的线I-I’的剖面示意图。
图5是本发明的第二实施例的一种功率半导体元件的上视示意图。
图6A至图6C分别是图2的区域A’的放大示意图。
图7是本发明的第三实施例的一种功率半导体元件的上视示意图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而,本发明也可以各种不同的形式体现,而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件,以下段落将不再一一赘述。
图1是本发明的第一实施例的一种功率半导体元件的上视示意图。图2A是图1的区域A的放大示意图。图2B是图2A的区域B的放大示意图。
请参照图1,本发明的第一实施例的功率半导体元件1包括衬底100,其定义有有源区R1与终端区R2。终端区R2环绕有源区R1,以防止电压击穿的现象发生。在一实施例中,衬底100可以是半导体衬底、半导体化合物衬底或是具有外延层在其上的硅衬底。
具体来说,有源区R1具有多个第一沟槽104。多个第一沟槽104配置在有源区R1的衬底100中。第一沟槽104沿第一方向D1延伸且沿第二方向D2排列。在一实施例中,第一沟槽104是以等距离的方式排列,而互相分离。在一实施例中,第一沟槽104的端面S5实质上是对齐的。终端区R2具有第二沟槽106。第二沟槽106配置在终端区R2的衬底100中。第二沟槽106沿第二方向D2延伸,且环绕有源区R1中的第一沟槽104,以形成封闭式的环形沟槽。如图1所示,第一沟槽104与第二沟槽106彼此分离,而不相连。第一方向D1与第二方向D2相交。在一实施例中,第一方向D1垂直于第二方向D2。在本实施例中,第一沟槽104可用以当作元件沟槽(cell trench)以容纳栅极结构10(如图4所示);而第二沟槽106可用以当作终端沟槽(termination trench)以容纳终端结构20(如图4所示)。
如图1所示,第二沟槽106包括平行部202与多个突出部204。具体来说,平行部202为沿着第二方向D2平行配置的条状沟槽,其具有相对的第一侧面S1与第二侧面S2。第一侧面S1靠近有源区R1,其可视为内侧面;而第二侧面S2远离有源区R1,其可视为外侧面。多个突出部204配置在平行部202的第一侧面S1上。突出部204自第一侧面S1往有源区R1的方向突出。第二侧面S2则是沿着第二方向D2平行配置的直线形状。在一实施例中,如图2A所示,突出部204的轮廓可以是山丘形。但本发明不以此为限。在其他实施例中,突出部204的轮廓也可以是矩形(如图3A的突出部204a所示)、三角形(如图3B的突出部204b所示)、不规则形或其组合。
详细地说,突出部204分别位于两相邻的第一沟槽104之间。在一实施例中,如图2A所示,各突出部204的宽度W小于两相邻的第一沟槽104之间的间距P。在一实施例中,如图2B所示,突出部204具有中心点204c,其位于所对应的两相邻的第一沟槽104之间的中心线15上。如图2B所示,第一沟槽104-1具有第一转角部CP1。第一沟槽104-2相邻于第一沟槽104-1且具有第二转角部CP2。第一沟槽104-1的第一转角部CP1与所对应的中心点204c之间具有第一距离d1。第一沟槽104-2的第二转角部CP2与所对应的中心点204c之间具有第二距离d2。在一实施例中,第一距离d1等于第二距离d2。第二沟槽106的第一侧面S1与第一沟槽104之间的最短距离为第三距离d3。在一实施例中,第三距离d3大于第一距离d1,且第三距离d3大于第二距离d2。在一实施例中,突出部204的突出长度L小于第三距离d3。
值得注意的是,如图2B所示,本实施例可通过光罩来定义第二沟槽106的突出部204的形状与尺寸,以将第一沟槽104-1的第一转角部CP1与第一侧面S1处的交叉点202c(也就是说第二沟槽106的第一侧面S1的延伸方向与中心线15的交会处)之间的第一距离d1’缩短或调整为第一距离d1。相似地,第一沟槽104-2的第二转角部CP2与第一侧面S1处的交叉点202c之间的第二距离d2’也可缩短或调整为第二距离d2。因此,有源区R1的第一沟槽104-1、104-2与终端区R2的第二沟槽106之间的电力线可均匀分布,以有效增加功率半导体元件1的击穿电压,进而提升功率半导体元件1的可靠度。
图2C是图2B的区域C的放大立体示意图。
请同时参照图1与图2C,终端区R2的第二沟槽106中可填入绝缘层108与导体层110,以在终端区R2的衬底100中形成终端结构20。绝缘层108共形地覆盖第二沟槽106的内表面,而导体层110填满整个第二沟槽106,使得绝缘层108配置于导体层110与衬底100之间。具体来说,终端结构20包括片状结构22与配置于第一侧面S1上的多个突出结构24。如图1与图2C所示,第二沟槽106的突出部204自第一侧面S1往有源区R1的方向突出,且自衬底100的顶面延伸至衬底100中。因此,填入第二沟槽106的突出部204的突出结构24也自第一侧面S1往有源区R1的方向突出,且自衬底100的顶面延伸至衬底100中。
图4是图1的线I-I’的剖面示意图。在以下的实施例中,是以第一导电型为N型,第二导电型为P型为例来说明,但本发明并不以此为限。本领域技术人员应了解,第一导电型也可以为P型,而第二导电型为N型。
请同时参照图1与图4,当第一沟槽104与第二沟槽106形成之后,还包括在第一沟槽104中形成栅极结构10,且在第二沟槽106中形成终端结构20,藉此形成本发明的第一实施例的功率半导体元件1。在一实施例中,功率半导体元件1可以是沟槽式金氧半导体场效晶体管(trench metal oxide semiconductor field effect transistor),但本发明不以此为限。
具体来说,功率半导体元件1包括衬底100、外延层102、第一导体层110a、第二导体层110b、第三导体层122、第一绝缘层108a、第二绝缘层108b以及第三绝缘层116。
如图4所示,衬底100具有有源区R1与终端区R2。在一实施例中,衬底100可以是具有第一导电型的半导体衬底,例如是N型重掺杂的硅衬底。外延层102配置于衬底100上,且外延层102中具有位于有源区R1中的第一沟槽104以及位于终端区R2中的第二沟槽106。在一实施例中,外延层102为具有第一导电型的外延层,例如是N型轻掺杂的外延层,且其形成方法包括进行选择性外延生长(selective epitaxy growth,SEG)工艺。
第一导体层110a配置于第一沟槽104中。第二导体层110b配置于第二沟槽106中。第三导体层122配置于第一沟槽104中且位于第一导体层110a上。在一实施例中,第一导体层110a、第二导体层110b以及第三导体层122的材料分别包括掺杂多晶硅,且其形成方法包括进行化学气相沉积工艺。
第一绝缘层108a配置于第一导体层110a与外延层102之间。第二绝缘层108b配置于第二导体层110b与外延层102之间。第三绝缘层116配置于第一导体层110a与第三导体层122之间。在一实施例中,第一绝缘层108a、第二绝缘层108b以及第三绝缘层116的材料分别包括氧化硅,且其形成方法包括进行热氧化法或化学气相沉积工艺。另外,第一导体层110a的顶面低于第二导体层110b的顶面。在一实施例中,由于线I-I’横越了第二沟槽106的突出部204,因此,在线I-I’的剖面上,第二沟槽106(或第二导体层110b)的宽度大于第一沟槽104(或第一导体层110a)的宽度。
在一实施例中,第三绝缘层116的宽度同于第一导体层110a的宽度。在一实施例中,第三绝缘层116与第一绝缘层108a接触,以电性隔离第一导体层110a与第三导体层122。在一实施例中,如图4所示,第三绝缘层116的顶面与第一绝缘层108a的顶面大致上齐平。但本发明不以此为限,在其他实施例中,第三绝缘层116的顶面低于第一绝缘层108a的顶面。
在一实施例中,功率半导体元件1还包括介电层120、主体层124以及掺杂区126。主体层124配置于有源区R1与终端区R2的外延层102中,且环绕第一沟槽104与第二沟槽106。在一实施例中,主体层124为具有第二导电型的主体层,例如是P型主体层,且其形成方法包括进行离子注入工艺。掺杂区126配置于有源区R1与终端区R2的主体层124中,且环绕第一沟槽104以及第二沟槽106的上部。在一实施例中,掺杂区126为具有第一导电型的掺杂区126,例如是N型重掺杂区,且其形成方法包括进行离子注入工艺。介电层120环绕第三导体层122的侧壁,且延伸覆盖有源区R1与终端区R2的掺杂区126的顶面。在一实施例中,介电层120的材料包括氧化硅,且其形成方法包括进行热氧化法。在一实施例中,主体层124的底面低于第三绝缘层116的顶面。
在一实施例中,功率半导体元件1还包括介电层128、第一接触窗130以及第二接触窗132。介电层128配置于有源区R1与终端区R2的外延层102上。在一实施例中,介电层128的材料包括氧化硅、硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、氟硅玻璃(FSG)或未掺杂硅玻璃(USG),且其形成方法包括进行化学气相沉积工艺。第一接触窗130穿过介电层128与介电层120,以与掺杂区126电性连接。第二接触窗132穿过介电层128并与第二导体层110b电性连接。在一实施例中,第一接触窗130与第二接触窗132的材料包括导体材料,其可以是金属,例如铝,且其形成方法包括进行化学气相沉积工艺。
在本实施例的功率半导体元件1中,第三导体层122可用以作为栅极,介电层120可用以作为栅介电层,第一导体层110a可用以作为遮蔽电极,以构成栅极结构10。衬底100可用以作为漏极,而掺杂区126可用以作为源极。在一实施例中,如图4所示,第三绝缘层116以及部分第一绝缘层108a的组合可用以作为栅极(例如,第三导体层122)与遮蔽栅极(例如,第一导体层110a)之间的栅间绝缘层。
图5是本发明的第二实施例的一种功率半导体元件的上视示意图。图6A至图6C分别是图2的区域A’的放大示意图。
请参照图5,基本上,本发明的第二实施例的功率半导体元件2与第一实施例的功率半导体元件1相似。上述两者不同之处在于:第二实施例的功率半导体元件2的第一沟槽104包括条状部206与两个延伸部208。条状部206具有沿着第一方向D1的相对两端E1、E2。两个延伸部208分别配置于条状部206的两端E1、E2上。在一实施例中,延伸部208彼此分离且不相连。另外,第二实施例的功率半导体元件2的第二沟槽106不包括多个突出部。
在一实施例中,如图6A所示,两个延伸部208a覆盖条状部206的两端E1、E2的两角落C1、C2。在另一实施例中,如图6B所示,延伸部208b覆盖条状部206的两端E1、E2的两侧壁S3、S4,而未覆盖两端E1、E2的端面S5。也就是说,条状部206的两端E1、E2的端面S5外露于两个延伸部208b,且两个延伸部208b与条状部206的两端E1、E2的端面S5为共平面。在其他实施例中,如图6C所示,两个延伸部208c完全覆盖条状部206的两端E1、E2的表面。也就是说,两个延伸部208c覆盖条状部206的两端E1、E2的两侧壁S3、S4以及两端E1、E2的端面S5。
值得一提的是,本实施例可通过光罩来定义第一沟槽104的延伸部208的形状与尺寸,使得有源区R1的第一沟槽104与终端区R2的第二沟槽106之间的电力线均匀分布,进而提升功率半导体元件2的击穿电压,并提升功率半导体元件2的可靠度。
图7是本发明的第三实施例的一种功率半导体元件的上视示意图。
请参照图7,基本上,本发明的第三实施例的功率半导体元件3是结合第一实施例的功率半导体元件1的突出部204与第二实施例的功率半导体元件2的延伸部208,使得有源区R1的第一沟槽104与终端区R2的第二沟槽106之间的电力线均匀分布,进而提升功率半导体元件3的击穿电压,并提升功率半导体元件3的可靠度。也就是说,功率半导体元件3不仅具有第二沟槽106平行部202的第一侧面S1上的突出部204,还具有第一沟槽104的条状部206的两端E1、E2上的两个延伸部208。
综上所述,本发明通过在终端区的第二沟槽中配置多个突出部,使其分别位于有源区的两相邻的第一沟槽之间。此配置可调整或缩短有源区的第一沟槽与终端区的第二沟槽之间的距离,以均匀化电力线的分布,进而提升功率半导体元件的击穿电压,并提升功率半导体元件的可靠度。
此外,本发明也可在有源区的第一沟槽的条状部的相对两端上配置两个延伸部,以均匀化有源区与终端区之间的电力线的分布,进而提升功率半导体元件的击穿电压。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视所附权利要求所界定者为准。
Claims (10)
1.一种功率半导体元件,其特征在于,包括:
衬底,定义有有源区与终端区,所述有源区具有多个第一沟槽,所述终端区具有第二沟槽,所述多个第一沟槽沿第一方向延伸且沿第二方向排列,所述第二沟槽沿所述第二方向延伸,所述第一方向与所述第二方向相交,
其中所述第二沟槽具有多个突出部,分别位于两相邻的所述第一沟槽之间。
2.根据权利要求1所述的功率半导体元件,其特征在于,各所述多个突出部具有中心点,其位于所对应的两相邻的所述第一沟槽之间的中心线上。
3.根据权利要求2所述的功率半导体元件,其特征在于,
所述第一沟槽中的一者,具有第一转角部,
所述第一沟槽中的另一者,相邻于所述第一沟槽中的所述一者,且具有第二转角部,
所述第一转角部与所对应的中心点之间具有第一距离,所述第二转角部与所对应的所述中心点之间具有第二距离,所述第一距离等于所述第二距离。
4.根据权利要求1所述的功率半导体元件,其特征在于,所述多个突出部自所述衬底的顶面延伸至所述衬底中。
5.根据权利要求1所述的功率半导体元件,其特征在于,各所述多个第一沟槽包括:
条状部,具有沿着所述第一方向的相对两端;以及
两个延伸部分别配置于所述条状部的所述两端上。
6.一种功率半导体元件,其特征在于,包括
衬底,定义有有源区与终端区,所述有源区具有多个第一沟槽,所述终端区具有第二沟槽,所述多个第一沟槽沿第一方向延伸且沿第二方向排列,所述第二沟槽沿所述第二方向延伸,所述第一方向与所述第二方向相交,
各所述第一沟槽包括条状部与两个延伸部,所述两个延伸部分别配置在所述条状部的相对两端上。
7.根据权利要求6所述的功率半导体元件,其特征在于,所述两个延伸部覆盖所述条状部的所述两端的两角落。
8.根据权利要求6所述的功率半导体元件,其特征在于,所述两个延伸部与所述条状部的所述两端为共平面。
9.根据权利要求6所述的功率半导体元件,其特征在于,所述两个延伸部完全覆盖所述条状部的所述两端的表面。
10.根据权利要求6所述的功率半导体元件,其特征在于,所述延伸部彼此分离。
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US20130248979A1 (en) * | 2012-03-23 | 2013-09-26 | Kabushiki Kaisha Toshiba | Power semiconductor device |
US20150108569A1 (en) * | 2013-10-21 | 2015-04-23 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device including trench termination and trench structure therefor |
TW201611183A (zh) * | 2014-09-02 | 2016-03-16 | 萬國半導體股份有限公司 | 改善uis性能的溝槽式功率半導體器件及其製備方法 |
US9620585B1 (en) * | 2016-07-08 | 2017-04-11 | Semiconductor Components Industries, Llc | Termination for a stacked-gate super-junction MOSFET |
US20170263718A1 (en) * | 2016-03-09 | 2017-09-14 | Polar Semiconductor, Llc | Termination trench structures for high-voltage split-gate mos devices |
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US20130248979A1 (en) * | 2012-03-23 | 2013-09-26 | Kabushiki Kaisha Toshiba | Power semiconductor device |
US20150108569A1 (en) * | 2013-10-21 | 2015-04-23 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device including trench termination and trench structure therefor |
TW201611183A (zh) * | 2014-09-02 | 2016-03-16 | 萬國半導體股份有限公司 | 改善uis性能的溝槽式功率半導體器件及其製備方法 |
US20170263718A1 (en) * | 2016-03-09 | 2017-09-14 | Polar Semiconductor, Llc | Termination trench structures for high-voltage split-gate mos devices |
US9620585B1 (en) * | 2016-07-08 | 2017-04-11 | Semiconductor Components Industries, Llc | Termination for a stacked-gate super-junction MOSFET |
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