CN110134622A - The data interaction system of data acquisition module and data transmission module - Google Patents
The data interaction system of data acquisition module and data transmission module Download PDFInfo
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- CN110134622A CN110134622A CN201910373918.3A CN201910373918A CN110134622A CN 110134622 A CN110134622 A CN 110134622A CN 201910373918 A CN201910373918 A CN 201910373918A CN 110134622 A CN110134622 A CN 110134622A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The invention discloses the data interaction system of data acquisition module and data transmission module, solves data transmission bauds between FPGA and ARM and mismatch.System includes with FPGA data acquisition module, ARM data transmission module, serial port communicating protocol, SRAM memory module, switch chip.Serial port communicating protocol carries out the interaction of a small amount of control information and order data for FPGA and ARM, and switch chip is for FPGA and connection of the ARM timesharing to storage chip, buffering of the SRAM as a large amount of digital signals.The data exchange channels of ARM and FPGA are established by serial port communicating protocol, complete the interaction of SRAM status information, command code interaction and data reliability verifying.The present invention solves in data acquisition, FPGA sample rate and the unmatched problem of ARM transmission speed, and ensure that the reliability of data interaction, takes high speed storing chip and high speed arm processor to have many advantages, such as compared to tradition cheap, method is simple.
Description
Technical field
The present invention relates to data collecting fields, and in particular between the transmission and acquisition module and transmission module of digital signal
The interaction of coomand mode.
Background technique
With the development of data acquisition technology, gradually develop to high-precision high-speed direction, and the data of data collecting plate card
Transmission mode can be different with the difference to pursue a goal, have the features such as at high cost, exploitation is complicated.It is high-precision same when pursuing
When, how to design reliable data transfer mode is the key that design, and data collecting plate card core controller generallys use
FPGA, because of its clock stable, speed is fast, anti-interference strong, and ARM has serial operation characteristic, and programs and be easy, exploitation letter
It is single, thus it is very efficient for constituting data collecting card with the combination of FPGA+ARM, and how to be designed according to higher sample rate
A kind of interactive system is the key that data collecting card.
Summary of the invention
The object of the present invention is to provide a kind of low in cost, the higher data acquisition module of sample rate and data transmission modules
Data interaction system.
The present invention is implemented as follows:
The data interaction system of data acquisition module and data transmission module, including data acquisition module FPGA, data transmit mould
Block ARM, storage chip SRAM, switch chip, interface chip USB, serial port communicating protocol, SPI communications protocol, the storage chip
SRAM is N block, and every piece of storage chip is driven by 4 line SPI, carries out hardware addressing for N block storage chip, distinguishes table with a byte
Be shown as addr1, addr2, addr3 ... addrN, address value be 0 represent the piece storage chip be it is empty, represent the piece for OXFF and deposit
Storage chip value be it is full, the switch chip is integrated single-pole double-throw switch (SPDT), and with variable connector, its input terminal of every way switch is connected
Every piece of storage chip, output channel are connected to FPGA and ARM, and every way switch is controlled by FPGA connection, FPGA and ARM
Timesharing connects muti-piece storage chip, and FPGA is connected with ARM by 2 line serial ports, and FPGA transmits state of a control information, state of a control letter
2 bytes of transmission are a frame every time for breath definition, and first character section indicates artificially defined address information, and second byte representation should
The corresponding value in address, and ARM one frame data of every reception need to send a frame response message, response frame information first character section value table
Show address, second byte uses a fixed value 0XAA as answer signal, and FPGA and ARM is sent every time, the address of response is believed
The value of breath should be consistent,
FPGA acquisition signal simultaneously sends information to the course of work of ARM as following steps:
The N number of state variable addr1 of S1:FPGA creation, address of addr2, addr3 ... the addrN as each piece of SRAM, initially
Change the address of each piece of SRAM, the value of each piece of address SRAM is initialized to 0, represent the value of block SRAM as sky,
S2:FPGA data acquisition module reads the corresponding value in each piece of address SRAM,
Whether the address value that S3:FPGA detects each piece of storage chip is 0, if zero, executes S4: otherwise continuing to execute S3,
S4:FPGA control switch chip is connected to FPGA and SRAM,
S5:FPGA carries out data acquisition, the continuous number signal of acquisition is sequentially written in N block SRAM, and change block SRAM
State variable value be it is full, that is, be assigned a value of OXFF,
S6:FPGA disconnects the connection with SRAM, and FPGA control switch chip is attached SRAM with ARM,
S7:FPGA successively sends each piece of SRAM address value to ARM by serial ports, and sending 2 bytes is one group, and first character section is ground
Location, second byte is value, indicates that the block chip has been expired with 0XFF,
S8: if FPGA does not receive the response message of ARM within a certain period of time, continuing to execute S7 step, otherwise execute S9,
S9: lower block address is sent, S7, S8 step are repeated.
Whether S10:N block SRAM is all sent completely, if executing S2, otherwise executes S7,
FPGA receives the step of ARM data are as follows:
S1:FPGA receives the data sent from ARM, parses data,
S2:FPGA sends response message to ARM,
The data that S3:ARM is sent are operated if host computer state, and after executing corresponding operation, FPGA executes S1, if ARM is sent
Data be SRAM address information, execute S4,
SRAM storage information preservation in the maintained state variable of SRAM, is executed S1 by S4:FPGA,
The data step of ARM reception FPGA are as follows:
S1:ARM carries out the initialization of each state variable,
S2:ARM detects Serial Port Information,
S3: whether serial ports has the information from FPGA, if executing S4, otherwise executes S2,
S4: receiving the data from FPGA by serial ports, modify the value of corresponding state variable,
S5: sending response message to FPGA, execute S2,
ARM sends PC control information to FPGA and derives from two parts, and a part comes from the control information of host computer, the
Two are partly due to transmit the value that each piece of sram chip of FPGA is fed back to after each piece of SRAM content,
From the transfer step of PC control information are as follows:
S1:ARM initializes each host computer performance variable,
S2:ARM detects host computer port information,
Whether S3: having PC control information, if executing S4, otherwise executes S2,
S4:ARM sends PC control information to FPGA,
Whether S5: receiving the response message of FPGA within a certain period of time, if executing S2, otherwise executes S4,
It transmits information to from the sending step of SRAM are as follows:
S1:ARM reads each piece of SRAM state variable value,
Whether S2:N block SRAM state value is all full, if executing S3, otherwise executes S1,
S3:ARM is successively read the value in every piece of SRAM by SPI protocol, is sent to host computer by USB interface, and modifying should
Block SRAM state variable value is sky
S4:ARM sends the fast SRAM status information to FPGA by serial ports,
Whether S5:ARM receives the response message of FPGA within a certain period of time, if executing S6, otherwise executes S4,
Whether S6:N block SRAM is all sent completely, if executing S1, otherwise executes S3.
The storage chip SRAM is N block, and every piece of storage depth is 1Mb, passes through the achievable N Mb data of N block storage chip
Storage.ARM uses STM32, FPGA to use EP4CE6F17C8, and SRAM selection storage speed can reach the chip of sample rate
23LC1024, and switch chip selects integrated single-pole double-throw switch (SPDT) ADG734, ADG734 gating time is within tens nanoseconds, USB
CH372 may be selected in interface chip, and 4 input pin IN1 that 4 pins of the SPI of sram chip are connected to switch chip are arrived
IN4, FPGA are connected to 4 control pin CON1 to CON4 of SRAM, while 4 SPI pins of FPGA are connected to switch chip
Pin A1, B1, C1, D1, and 4 SPI pins of ARM are connected to pin A2, B2, C2, D2 of switch chip, switch chip with
CON1-CON4 between FPGA is gate control signal, the height of the voltage of switch chip make pin IN-IN4, pin A1, B1,
C1, D1 are connected to pin A2, B2, C2, D2 timesharing, and USB interface is used for and host computer is attached, under original state, at the beginning of FPGA
Beginningization control pin all exports high level, is connected to the input terminal of switch chip with A1-D1, is also equivalent to FPGA and SRAM is straight
Connect it is connected, FPGA carry out data acquisition after, write data into SRAM, low level then be arranged in control terminal, make SRAM
It is connected to ARM.Then FPGA is changed after ARM receives data by the status information that serial ports sends SRAM using interactive step
Data are sent to host computer, and status information feedback are carried out the acquisition of next round data to FPGA by corresponding Status Flag, when
When ARM receives the control information of host computer, FPGA is routed the message to by ARM interactive step.
The present invention provides the systems that data between a kind of FPGA and ARM are transmitted, higher for sample rate, solve data
The scheme of caching and transmission has structure simple, and development difficulty is lower, and serial port communication method can guarantee the correctness of data.
Detailed description of the invention
Fig. 1 is block diagram of the invention.
Fig. 2 is the flow chart that FPGA sends information to ARM.
Fig. 3 is the flow chart that FPGA receives ARM information.
Fig. 4 is the flow chart that ARM receives FPGA information.
Fig. 5 and Fig. 6 is the flow chart that ARM sends FPGA information.
The detailed circuit schematic diagram of mono- piece of SRAM of Fig. 7.
Specific embodiment
The data interaction system of data acquisition module and data transmission module, including data acquisition module FPGA, data pass
Defeated modules A RM, storage chip SRAM, switch chip, interface chip USB, serial port communicating protocol, SPI communications protocol, ARM are used
STM32, FPGA use EP4CE6F17C8, and SRAM selection storage speed can reach the chip 23LC1024 of sample rate, and open
It closes chip and selects integrated single-pole double-throw switch (SPDT) ADG734, within tens nanoseconds, USB interface chip may be selected ADG734 gating time
4 pins of CH372, the SPI of sram chip are connected to 4 input pin IN1 to IN4 of switch chip, and FPGA is connected to
4 control pin CON1 to CON4 of SRAM, at the same 4 SPI pins of FPGA be connected to pin A1, B1 of switch chip, C1,
D1, and 4 SPI pins of ARM are connected to pin A2, B2, C2, D2 of switch chip, the CON1- between switch chip and FPGA
CON4 is gate control signal, the height of the voltage of switch chip make pin IN-IN4, pin A1, B1, C1, D1 and pin A2,
B2, C2, D2 timesharing connection, USB interface is used for and host computer is attached, and under original state, FPGA initialization control pin is all
Export high level, be connected to the input terminal of switch chip with A1-D1, be also equivalent to FPGA and SRAM is connected directly, FPGA into
After row data acquire, writes data into SRAM, low level then is arranged in control terminal, be connected to SRAM with ARM.Then
FPGA changes corresponding state mark using interactive step by the status information that serial ports sends SRAM after ARM receives data
Data are sent to host computer, and status information feedback are carried out the acquisition of next round data to FPGA by will, when ARM receives host computer
Control information when, FPGA is routed the message to by ARM interactive step.
The storage chip SRAM is N block, and every piece of storage depth is 1Mb, passes through the achievable N Mb data of N block storage chip
Storage, every piece of storage chip drives by 4 line SPI, carries out hardware addressing for N block storage chip, is respectively indicated with a byte
For addr1, addr2, addr3 ... addrN, address value be 0 represent the piece storage chip be it is empty, represent piece storage for OXFF
Chip value be it is full, the switch chip is integrated single-pole double-throw switch (SPDT), has variable connector, and the connection of its input terminal of every way switch is every
Block storage chip, output channel are connected to FPGA and ARM, and every way switch is controlled by FPGA connection, and FPGA and ARM divide
When connect muti-piece storage chip, FPGA connects with ARM by 2 line serial ports, FPGA transmission state of a control information, state of a control information
2 bytes of transmission are a frame every time for definition, and first character section indicates artificially defined address information, second byte representation ground
The corresponding value in location, and ARM one frame data of every reception need to send a frame response message, response frame information first character section value indicates
Address, second byte use a fixed value 0XAA as answer signal, and FPGA and ARM send every time, the address information of response
Value should be consistent,
FPGA acquisition signal simultaneously sends information to the course of work of ARM as following steps:
S1:FPGA creates N number of state variable addr1, address of addr2, addr3 ... the addrN as each piece of SRAM, initialization
The value of the address of each piece of SRAM, each piece of address SRAM is initialized to 0, represent the value of block SRAM as sky,
S2:FPGA data acquisition module reads the corresponding value in each piece of address SRAM,
Whether the address value that S3:FPGA detects each piece of storage chip is 0, if zero, executes S4: otherwise continuing to execute S3,
S4:FPGA control switch chip is connected to FPGA and SRAM,
S5:FPGA carries out data acquisition, the continuous number signal of acquisition is sequentially written in N block SRAM, and change block SRAM
State variable value be it is full, that is, be assigned a value of OXFF,
S6:FPGA disconnects the connection with SRAM, and FPGA control switch chip is attached SRAM with ARM,
S7:FPGA successively sends each piece of SRAM address value to ARM by serial ports, and sending 2 bytes is one group, and first character section is ground
Location, second byte is value, indicates that the block chip has been expired with 0XFF,
S8: if FPGA does not receive the response message of ARM within a certain period of time, continuing to execute S7 step, otherwise execute S9,
S9: lower block address is sent, S7, S8 step are repeated.
Whether S10:N block SRAM is all sent completely, if executing S2, otherwise executes S7,
FPGA receives the step of ARM data are as follows:
S1:FPGA receives the data sent from ARM, parses data,
S2:FPGA sends response message to ARM,
The data that S3:ARM is sent are operated if host computer state, and after executing corresponding operation, FPGA executes S1, if ARM is sent
Data be SRAM address information, execute S4,
SRAM storage information preservation in the maintained state variable of SRAM, is executed S1 by S4:FPGA,
The data step of ARM reception FPGA are as follows:
S1:ARM carries out the initialization of each state variable,
S2:ARM detects Serial Port Information,
S3: whether serial ports has the information from FPGA, if executing S4, otherwise executes S2,
S4: receiving the data from FPGA by serial ports, modify the value of corresponding state variable,
S5: sending response message to FPGA, execute S2,
ARM sends PC control information to FPGA and derives from two parts, and a part comes from the control information of host computer, the
Two are partly due to transmit the value that each piece of sram chip of FPGA is fed back to after each piece of SRAM content,
From the transfer step of PC control information are as follows:
S1:ARM initializes each host computer performance variable,
S2:ARM detects host computer port information,
Whether S3: having PC control information, if executing S4, otherwise executes S2,
S4:ARM sends PC control information to FPGA,
Whether S5: receiving the response message of FPGA within a certain period of time, if executing S2, otherwise executes S4,
It transmits information to from the sending step of SRAM are as follows:
S1:ARM reads each piece of SRAM state variable value,
Whether S2:N block SRAM state value is all full, if executing S3, otherwise executes S1,
S3:ARM is successively read the value in every piece of SRAM by SPI protocol, is sent to host computer by USB interface, and modifying should
Block SRAM state variable value is sky
S4:ARM sends the fast SRAM status information to FPGA by serial ports,
Whether S5:ARM receives the response message of FPGA within a certain period of time, if executing S6, otherwise executes S4,
Whether S6:N block SRAM is all sent completely, if executing S1, otherwise executes S3.
Claims (3)
1. the data interaction system of data acquisition module and data transmission module, which is characterized in that including data acquisition module
FPGA, data transmission module ARM, storage chip SRAM, switch chip, interface chip USB, serial port communicating protocol, SPI communication association
View, the storage chip SRAM are N block, and every piece of storage chip is driven by 4 line SPI, carry out hardware addressing for N block storage chip,
Addr1, addr2, addr3 ... addrN are expressed as with a byte, address value is 0 to represent the piece storage chip as sky,
The piece storage chip value is represented to be full for OXFF, and the switch chip is integrated single-pole double-throw switch (SPDT), has variable connector, every road
Switch its input terminal and connect every piece of storage chip, output channel is connected to FPGA and ARM, every way switch by FPGA connect into
Row control, FPGA with ARM timesharing connect muti-piece storage chip, FPGA and ARM and are connected by 2 line serial ports, FPGA transmission control shape
State information, 2 bytes of transmission are a frame to the definition of state of a control information every time, and first character section indicates artificially defined address letter
Breath, the corresponding value in second byte representation address, and ARM one frame data of every reception need to send a frame response message, response
Frame information first character section value indicates address, and second byte uses a fixed value 0XAA as answer signal, and FPGA is every with ARM
The value of the address information of secondary transmission, response should be consistent,
FPGA acquisition signal simultaneously sends information to the course of work of ARM as following steps:
The N number of state variable addr1 of S1:FPGA creation, address of addr2, addr3 ... the addrN as each piece of SRAM, initially
Change the address of each piece of SRAM, the value of each piece of address SRAM is initialized to 0, represent the value of block SRAM as sky,
S2:FPGA data acquisition module reads the corresponding value in each piece of address SRAM,
Whether the address value that S3:FPGA detects each piece of storage chip is 0, if zero, executes S4: otherwise continuing to execute S3,
S4:FPGA control switch chip is connected to FPGA and SRAM,
S5:FPGA carries out data acquisition, the continuous number signal of acquisition is sequentially written in N block SRAM, and change block SRAM
State variable value be it is full, that is, be assigned a value of OXFF,
S6:FPGA disconnects the connection with SRAM, and FPGA control switch chip is attached SRAM with ARM,
S7:FPGA successively sends each piece of SRAM address value to ARM by serial ports, and sending 2 bytes is one group, and first character section is ground
Location, second byte is value, indicates that the block chip has been expired with 0XFF,
S8: if FPGA does not receive the response message of ARM within a certain period of time, continuing to execute S7 step, otherwise execute S9,
S9: block address under sending, repetition S7, S8 step,
Whether S10:N block SRAM is all sent completely, if executing S2, otherwise executes S7,
FPGA receives the step of ARM data are as follows:
S1:FPGA receives the data sent from ARM, parses data,
S2:FPGA sends response message to ARM,
The data that S3:ARM is sent are operated if host computer state, and after executing corresponding operation, FPGA executes S1, if ARM is sent
Data be SRAM address information, execute S4,
SRAM storage information preservation in the maintained state variable of SRAM, is executed S1 by S4:FPGA,
The data step of ARM reception FPGA are as follows:
S1:ARM carries out the initialization of each state variable,
S2:ARM detects Serial Port Information,
S3: whether serial ports has the information from FPGA, if executing S4, otherwise executes S2,
S4: receiving the data from FPGA by serial ports, modify the value of corresponding state variable,
S5: sending response message to FPGA, execute S2,
ARM sends PC control information to FPGA and derives from two parts, and a part comes from the control information of host computer, the
Two are partly due to transmit the value that each piece of sram chip of FPGA is fed back to after each piece of SRAM content,
From the transfer step of PC control information are as follows:
S1:ARM initializes each host computer performance variable,
S2:ARM detects host computer port information,
Whether S3: having PC control information, if executing S4, otherwise executes S2,
S4:ARM sends PC control information to FPGA,
Whether S5: receiving the response message of FPGA within a certain period of time, if executing S2, otherwise executes S4,
It transmits information to from the sending step of SRAM are as follows:
S1:ARM reads each piece of SRAM state variable value,
Whether S2:N block SRAM state value is all full, if executing S3, otherwise executes S1,
S3:ARM is successively read the value in every piece of SRAM by SPI protocol, is sent to host computer by USB interface, and modifying should
Block SRAM state variable value is sky
S4:ARM sends the fast SRAM status information to FPGA by serial ports,
Whether S5:ARM receives the response message of FPGA within a certain period of time, if executing S6, otherwise executes S4,
Whether S6:N block SRAM is all sent completely, if executing S1, otherwise executes S3.
2. the data interaction system of data acquisition module according to claim 1 and data transmission module, which is characterized in that
The storage chip SRAM is N block, and every piece of storage depth is 1Mb, by the storage of the achievable N Mb data of N block storage chip,
ARM uses STM32, FPGA to use EP4CE6F17C8, and SRAM selection storage speed can reach the chip of sample rate
23LC1024, and switch chip selects integrated single-pole double-throw switch (SPDT), gating time is within tens nanoseconds, USB interface chip selection
CH372。
3. the data interaction system of data acquisition module according to claim 1 or 2 and data transmission module, feature exist
In ARM uses STM32, FPGA to use EP4CE6F17C8, and SRAM selection storage speed can reach the chip of sample rate
23LC1024, switch chip select integrated single-pole double-throw switch (SPDT) ADG734, and within tens nanoseconds, USB connects ADG734 gating time
Mouth chip selects CH372, and 4 pins of the SPI of sram chip are connected to 4 input pin IN1 to IN4 of switch chip,
FPGA is connected to 4 control pin CON1 to CON4 of SRAM, while 4 SPI pins of FPGA are connected to drawing for switch chip
Foot A1, B1, C1, D1, and 4 SPI pins of ARM are connected to pin A2, B2, C2, D2 of switch chip, switch chip and FPGA
Between CON1-CON4 be gate control signal, the height of the voltage of switch chip make pin IN-IN4, pin A1, B1, C1,
D1 is connected to pin A2, B2, C2, D2 timesharing, and USB interface is used for and host computer is attached, under original state, FPGA initialization
Control pin all exports high level, is connected to the input terminal of switch chip with A1-D1, is also equivalent to the direct phase of FPGA and SRAM
Even, it after FPGA carries out data acquisition, writes data into SRAM, low level then is arranged in control terminal, make SRAM and ARM
Connection, then FPGA sends the status information of SRAM by serial ports, using interactive step, changes after ARM receives data corresponding
Status Flag, data are sent to host computer, and give FPGA to carry out the acquisition of next round data status information feedback, when ARM is received
To host computer control information when, FPGA is routed the message to by ARM interactive step.
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