CN1678086A

CN1678086A - High-speeld code-flow playing and receiving device based on PCI

Info

Publication number: CN1678086A
Application number: CN 200510041801
Authority: CN
Inventors: 李兵兵; 黄新平; 杨秀莲; 蔚述明; 王莎莎; 李乐乐
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2005-03-16
Filing date: 2005-03-16
Publication date: 2005-10-05
Anticipated expiration: 2025-03-16
Also published as: CN100452885C

Abstract

The disclosed device in use for testing and analyzing code stream in digital TV includes computer, code stream playing card, and code stream receiving card. The said code stream playing card, and code stream receiving card are composed of FPGA programmable logic device, PCI interface chip, external storage FIFO in large capacity and periphery devices respectively. FPGA is in use for controlling PCI state, coordinating operations between PCI interface chip and FIFO. PCI state and logic control, NCO circuit, data buffer, interrupt control, code rate adjustment etc. are collocated in FPGA of the playing card. Input interface selection, input signal processing, PCI state and logic control, data buffer, interrupt control etc. are collocated in FPGA of the receiving card. Reasonable using function of PCI interface chip, through FPGA processing, the invention realizes code rate in high rate played and received by computer. The transmitted code rate can reach as high as 120Mbps.

Description

High-speed code stream playing and receiving device based on PCI

Technical Field

The invention relates to the technical field of digital television broadcasting, in particular to a high-speed code stream playing and receiving device based on Peripheral Component Interconnect (PCI).

Background

With the development of digital televisions and the establishment of the MPEG-2 standard, the development and application of digital audio and video and MPEG in the field of digital televisions at home and abroad are in a rapidly developing stage. In the process of source coding and channel maintenance design, it is often necessary to know whether the generated code stream or the obtained code stream meets the standard. Sometimes the code stream must also be analyzed to obtain its performance in terms of encoding and transmission. In the process of monitoring or fault checking of the digital television system, related equipment is also needed to analyze the generated or obtained code stream. Still other devices also need to perform code stream verification procedures and the like during modulation. These tasks all require the implementation of devices capable of receiving and playing the codestream.

At present, several major instrument and broadcasting equipment manufacturers at home and abroad are developing or developing the equipment, and the hardware design of the equipment is also based on the PCI interface of the computer. But the design principle is more complex and the performance is not ideal enough. For example, the MPEG-2 transport stream data acquisition card BSRC-11 and the transmitting card BSTC-11 developed by the blue topology of the domestic famous professional manufacturer of digital television test measuring equipment are both devices based on PCI interfaces, the principle design is complex, a programmable logic device with larger resources is used on a main signal processing module, the code rate of the code stream which can be received or transmitted is 108Mbps at most, and the design cost of the product is higher. The code stream playing and receiving card produced by the American computer module company has a simple design and a single product function, can only receive and transmit the code stream singly, and does not have the code rate adjustment function.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a high-speed code stream playing and receiving device based on Peripheral Component Interconnect (PCI). The device can be used for analyzing, testing and monitoring the high-speed code stream of a digital television system by utilizing a Peripheral Component Interconnect (PCI) interface chip of a computer to control the playing and receiving of the high-speed code stream.

The technical scheme of the invention comprises a PC, a code stream playing card and a code stream receiving card, wherein the PC controls the code stream playing card and the code stream receiving card respectively through a peripheral device interconnection PCI interface chip to realize playing and acquisition of the code stream. The code stream playing card mainly comprises a programmable logic device FPGA, a PCI interface chip, an external large-capacity memory FIFO and a peripheral device 27M clock source, FPGA initialization and configuration, an AD9851 frequency synthesizer, an ASI output module and an SPI output module. The code stream receiving card mainly comprises a programmable logic device FPGA, a PCI interface chip, an external large-capacity memory FIFO and peripheral component 27M clock source, FPGA initialization and configuration, an ASI input module and an SPI input module; wherein,

the programmable logic device FPGA is connected with the PCI interface chip and the external large-capacity memory FIFO and is used for controlling the PCI interconnection state of the peripheral devices and coordinating the work between the PCI interface chip and the external FIFO;

the PCI interface chip is used for simplifying a PCI bus protocol, converting complex PCI bus operation into simple local bus operation and realizing the sending and receiving of code stream data by matching with a programmable logic device FPGA;

the 27MHZ clock source is used for generating and shaping a reference clock, generating a 27MHZ system clock and providing a stable reference clock for a CY7B933/CY7B923 chip, an FPGA chip and a PCI interface chip;

initializing and configuring the FPGA, and downloading relevant setting information required by the FPGA into a configuration space of the FPGA when the FPGA is powered on so that the FPGA can realize the required function;

the external large-capacity memory FIFO is used for caching data when the high-speed code rate code stream is played/received, and the processing speed of the PC machine on the data is improved;

the AD9851 frequency synthesizer is used for synthesizing a clock with the same size as the code stream code rate and sending a clock signal to the clock control module;

the SPI output module is used for completing level conversion of output signals, converting output TTL level signals into low-voltage differential level signals and LVDS (low voltage differential signaling) to be output, converting the SPI signals into signals suitable for cable transmission to be output and improving the anti-interference capability of the signals in channel transmission;

the ASI output module converts ASI signals into signals suitable for cable transmission and comprises a CY7B923 chip and a coupling shaping circuit, wherein the CY7B923 chip mainly realizes 8/10bit conversion of code words, insertion of a synchronous word K28.5 and parallel-serial conversion, and drive and coupling output of the ASI signals with the constant output rate of 270MHZ are completed;

the SPI input module is used for completing level conversion of input signals, converting low-voltage differential level signals LVDS (low voltage differential signaling) input from the SPI interface into TTL (transistor-transistor logic) level signals and outputting 11 paths of signals conforming to an SPI signal structure;

the ASI input module mainly completes the coupling amplification and shaping of input signals, the interface coupling circuit completes the recovery of clocks and data of the input signals, the CY7B933 chip mainly realizes 10/8bit conversion of code words, removal of synchronous words K28.5 and serial-parallel conversion, 8 paths of parallel data signals are output, and the transmission rate of the ASI is constant at 270 MHZ. Because the rates of the code streams are different, an internal FIFO is needed to complete the rate matching of the input signals, and the internal RAM of the FPGA is used for realizing the rate matching.

The main configuration of the programmable logic device FPGA of the play card comprises a PCI state and logic control module, an NCO numerically controlled oscillator circuit, a data cache module, a clock control module, an interrupt control module, an output clock synthesis and control module, a code rate adjustment module, an output interface selection module and an interface chip control module. Wherein,

PCI state and logic control, which realizes the function of PCI and completes the DMA control of PCI, and sends the output interface selection signal generated by address decoding to the output interface selection module; outputting the generated clock control signal to a clock control module; sending the generated continuous pulses to an NCO circuit as a writing clock of the configuration word;

the data cache is used for caching configuration words input by a computer and data transmitted between the computer and an external large-capacity memory FIFO by using the FIFO provided in the FPGA, and transmitting different configuration words to an NCO circuit and an output clock synthesis and control module when the equipment is started by combining a PCI state and logic control module;

the NCO numerically controlled oscillator circuit is characterized in that computer software converts a new code rate to be adjusted into a configuration word and sends the configuration word to an NCO circuit module, the NCO generates a clock signal according with the size of the new code rate according to configuration word information, the stepping precision of code rate adjustment is 1HZ, and the clock signal is sent to a code rate adjustment module;

the code rate adjusting module receives a code stream sent by an external large-capacity memory FIFO and a clock signal input by an NCO circuit, and realizes multi-code rate playing of a single program source, namely, the code rate of an original code stream is changed and the code stream is output at any code rate with the precision of 1 HZ;

the clock control controls the clock synthesized by the AD9851 based on the input clock control signal, and outputs this clock signal to the external mass storage as a clock for reading data from the external mass storage.

The output clock synthesis and control module analyzes the code rate of the code stream obtained by the computer software and converts the code rate into corresponding configuration words to be sent to the module, and the module writes the configuration words into the AD9851 frequency synthesizer and controls the AD9851 chip to output corresponding clocks to the clock control module;

the interrupt control module takes the half-full state of the external memory FIFO as an interrupt signal to realize the communication between external hardware and computer software, and simultaneously the computer software takes the signal as a time mark for the computer to initiate data transmission;

the output interface selection module is used for finishing the signal transmission from the ASI interface or the SPI interface according to a selection input control signal set by the computer;

the ASI transmission rate is constant at 270MHZ, the output code stream rates are different, FIFO is needed to realize rate matching, and the communication between the output data and the CY7B923 chip is logically controlled;

the main configuration of the FPGA of the code stream receiving card comprises input interface selection, input signal processing, PCI state and logic control, interrupt control and a data cache module, and the main purposes and signal transmission relations of each configuration module are as follows:

the input interface selection module completes receiving an ASI input signal or an SPI input signal according to a selection control input signal set by the computer;

the input signal processing module analyzes the selected interface input signal, writes the selected interface input signal into an external large-capacity memory FIFO, and controls the start/stop time of received data according to an input control signal set by a computer;

the data caching module is used for caching data and ensuring stable DMA (direct memory access) transmission of the data between the external memory and the internal memory of the computer;

the interrupt control module is used for taking the half-full state of the external memory as an interrupt signal to realize the communication between external hardware and computer software, and meanwhile, the computer software takes the signal as a mark of when the computer initiates data transmission;

the PCI state and logic control module is used for realizing the function of the PCI and finishing the DMA control of the PCI and sending an input interface selection signal generated by address decoding into the input interface selection module; the generated enable signal is sent to the input signal processing module.

The invention uses the special PCI interface chip with powerful function and reasonably designs the configuration of the FPGA, thereby realizing the direct playing and receiving of code streams by a computer. Compared with the prior art, the method has the advantages of simple hardware circuit design, perfect functions, good performance and low equipment cost, and realizes the high-speed transmission of code stream data. The code rate of the transmitted code stream reaches up to 120Mbps, the processing of multi-path synthesis of high-code-rate transport streams can be met, and the code stream can be detected and analyzed while the code stream is played and received with the assistance of software. Therefore, the present invention has wide application in the installation, debugging, detection and maintenance of digital television systems.

Drawings

FIG. 1: overall structure of the invention

FIG. 2: internal structure diagram of code stream playing card

FIG. 3: internal structure flow chart of code rate regulation module of the invention

FIG. 4: internal structure chart of code stream receiving card

FIG. 5: the invention is a schematic diagram of the test

Detailed Description

Referring to fig. 1, the internal structure of the present invention includes a code stream playing card, a code stream receiving card and a PC, wherein the PC controls the code stream playing card and the code stream receiving card through a peripheral interconnection PCI interface chip, respectively, to realize the playing and receiving of data.

Referring to fig. 2, the code stream playing card of the present invention comprises a PCI interface chip, an external mass storage FIFO, a programmable logic device FPGA, an SPI output, an ASI output, a 27MHZ clock source, an AD9851 chip, and an FPGA initialization and configuration module. The internal configuration of the programmable logic device FPGA comprises a PCI state and logic control module, a data cache module, an interrupt control module, an output clock synthesis and control module, a clock control module, an NCO numerically controlled oscillator circuit, a code rate adjusting module and an output interface selection output chip control module, wherein the functions and signal transmission relations of the modules are as follows:

the PCI interface chip converts complex PCI bus operation into simple local bus operation, simplifies the PCI bus protocol, ensures the flexibility of circuit design and the stability of performance by the powerful function of the PCI interface chip, and shows the superiority in the aspect of finishing high-speed data processing. The PCI interface chip selects a PLX PCI9054 chip capable of executing a DMA (direct memory access) transmission function and is matched with a programmable logic device FPGA (field programmable gate array) to realize the transmission of code stream data.

And the PCI state and logic control realize the function of the PCI and complete the DMA control of the PCI, thereby ensuring the stable and accurate playing of the high-speed code stream. The control of PCI bus interface, address and data control, address decoding, DMA data transmission and state control are completed. The address decoding generates output interface selection signals to be output to the output interface selection module, generates clock control signals to be output to the clock control module, and generates continuous pulses to be sent to the NCO circuit to be used as a writing clock of the configuration word.

And the data cache is used for caching the input data by using FIFO (first in first out) provided inside the FPGA. The FIFO combines PCI state and logic control to realize that different configuration words sent by the computer are respectively transmitted to the NCO circuit and the output clock synthesis and control module, and then are specially used for caching data between the computer and an external mass memory.

When the high-code-rate code stream is played, in order to make up for the delay of DMA processing of the computer and the reading of the internal data of the computer, the external high-capacity memory needs to cache the data, and simultaneously, the processing speed of the local end of the PCI interface chip on the data is improved by changing the reading and writing speed.

And interrupt control, namely, using the half-full state of the external memory as an interrupt signal to realize the communication between the external hardware and the computer software. At the same time, the computer software takes the signal as a time mark for the computer to initiate data output.

Output clock synthesis and control, the code rate of the code stream is obtained through the analysis of computer software and is converted into a corresponding configuration word to be sent to the module, the module realizes the control of the writing of the configuration word into the AD9851 frequency synthesizer and controls the AD9851 frequency synthesizer to output a corresponding clock to the clock control module;

The NCO circuit, computer software will want the new code rate of adjustment to convert the configuration word to send into NCO circuit module, NCO produces a clock signal according with the new code rate according to the configuration word information, output the clock and send to the code rate adjustment module. The code stream is output from an external interface at the code rate, and the circuit realizes that the stepping precision with adjustable code rate is 1 HZ.

And selecting an output interface, namely realizing the purpose of controlling an input signal according to selection set by a computer and finishing the signal transmission from an ASI interface or an SPI interface.

And the SPI output module is used for finishing the level conversion of output signals, converting output TTL level signals into low-voltage differential level signals (LVDS) for output, converting SPI signals into signals suitable for cable transmission for output and improving the anti-interference capability of the signals in channel transmission.

The transmission rate of the ASI is constant at 270MHZ under the control of the output chip, and the output code stream rates are different, so that FIFO is needed to realize rate matching, and the communication between the output data and the FIFO and the CY7B923 chip needs to be logically controlled.

And the ASI output module is used for converting the ASI signals into signals suitable for cable transmission. The circuit comprises a CY7B923 chip and a coupling shaping circuit. The CY7B923 chip mainly realizes 8/10bit conversion, synchronous word insertion K28.5 and parallel/serial conversion of code words, and completes the driving and coupled output of ASI signals with the output rate constant at 270 MHZ.

And a 27MHZ clock source generates and shapes a reference clock to generate a 27MHZ system clock and provide a stable reference clock for a CY7B933 chip, an FPGA chip and a PCI interface chip.

Initializing and configuring the FPGA, and downloading relevant setting information required by the FPGA into a configuration space of the FPGA when the FPGA is powered on so that the FPGA can realize the required functions.

And the code rate adjusting module is used for realizing multi-code rate playing of a single program source, namely, the code stream is output at any code rate with the precision of 1HZ by changing the code rate of the original code stream. The code stream adjustment is to cache the input TS code stream and then carry out synchronous head detection, pack the TS stream into continuous stream of one packet per 188Byte, carry out PCR detection by taking the packet as a unit, extract PCR value in the TS stream, and subtract the PCR value and the number generated by the counter to obtain new PCR value to be inserted into the TS stream. And inserting the input clock generated by the NCO circuit into the TS flow empty packet of the modified PCR information to generate a new TS flow. And then extracting the PCR value in the new TS again, adding the PCR value and the generated number of the counter, modifying the PCR information for the second time, and finally, putting the obtained PCR information into the TS to finish code rate adjustment of the code stream.

As shown in fig. 3, the internal configuration of the code rate adjustment module includes: internal FIFO (A), synchronous head detection, PCR detection, subtracter, PCR insertion, internal FIFO (B), empty packet generator and empty packet insertion, internal FIFO (C), adder and counter. The purposes and signal transmission relations of the configurations are as follows:

[1] internal FIFO (1): using FIFO provided in FPGA to buffer input TS stream, using a 27MHZ high clock as FIFO read clock to read TS stream, and increasing speed for subsequent processing;

[2] and (3) synchronous head detection: the TS stream is composed of TS packets, each TS packet is composed of 188Byte data, and the module extracts the implicit synchronous signals in the input TS stream, namely, the TS stream is processed into a series of continuous TS packets. The output of TS detected by the synchronous head is divided into two paths, one path is used for PCR detection, and the other path is input to a PCR insertion module to finish modification of PCR information

[3] And (3) PCR detection: and extracting PCR values in the TS stream. The format of TS stream is in accordance with MPEG-2 standard, wherein the information of each TS packet header is fixed, PCR detection obtains whether the packet contains PCR information by detecting the TS packet header information, if the TS packet contains PCR information, the PCR value is extracted and output to the addition and subtraction arithmetic unit;

[4] a subtracter: subtracting the PCR value extracted from the TS stream from the count generated by a counter with a reference clock of 27MHZ and outputting the result as a new PCR value;

[5] PCR insertion: detecting input TS stream signals by taking a packet as a unit, removing a PCR value in a PCR domain of the TS stream, inserting an input new PCR value into the PCR domain of the TS stream to obtain and output the TS stream with the modified PCR information;

[6] internal FIFO (2): using FIFO provided in FPGA to buffer input TS stream, and using input clock generated by NCO circuit as FIFO read clock to read TS stream and send it to empty packet generator together with FIFO empty and full signal;

[7] a blank packet generator: and outputting the data stream with the null information which conforms to the TS packet format, namely outputting the null packet.

[8] Inserting an empty bag: according to the input empty full signal of the internal FIFO (2), when the half full signal of the internal FIFO (2) is effective, the input TS stream is output by taking a packet as a unit, otherwise, an empty packet is output, and the insertion of the empty packet is completed.

[9] Internal FIFO (3): the incoming new TS stream is buffered using a FIFO provided internally in the FPGA. The output signal is divided into two paths: one path enters into the PCR extension for extracting PCR information; and the other path is transmitted to a PCR embedding module to finish the modification of the PCR information.

[10] An adder: the PCR value extracted from the TS stream is added to the number generated by a counter with a reference clock of 27MHz and the result is sent as a new PCR value.

[11] A counter: the reference clock 27MHZ is used as the counting clock of the counter, and the generated count is input into the adder and the subtracter for adjusting the PCR value.

Referring to fig. 4, the code stream receiving card of the present invention comprises an ASI input module, an SPI input module, a programmable logic device FPGA, an external mass storage FIFO, a PCI interface chip, a 27MHZ clock source, and an FPGA initialization and configuration. The internal configuration of the FPGA includes: input interface selection, input signal processing, PCI state and logic control, interrupt control and a data caching module. The usage of the modules of the external mass storage FIFO, the PCI interface chip, the 27M clock source, the FPGA initialization and configuration and the like is the same as that of the corresponding modules of the code stream playing card. The purposes and data transmission relations of other component modules are as follows:

an ASI input module: the CY7B933 chip mainly realizes 10/8bit conversion of code words, removal of synchronous words K28.5 and serial-parallel conversion, and outputs 8 paths of parallel data signals. The transmission rate of the ASI is constant at 270MHZ, and the rates of the code streams are different, so that a FIFO is needed to complete the rate matching of input signals, and the internal RAM of the FPGA is used for realizing the rate matching.

An SPI input module: and completing level conversion of input signals, converting low-voltage differential level signals (LVDS) input by the SPI into TTL level signals, and outputting 11 paths of signals conforming to the SPI signal structure.

Selecting an input interface: the ASI input signal or the SPI input signal is received according to a selection control input signal set by a computer.

Input signal processing: and finishing the analysis of the selected interface input signal, writing the selected interface input signal into an external mass storage, and realizing the control of when to start or stop receiving data according to an enabling control signal input set by the computer.

Data caching: and buffering the data to ensure stable DMA transfer between the external memory and the internal memory of the computer.

And (3) interrupt control: and the half-full state of the external memory is used as an interrupt signal to realize the communication between the external hardware and the computer software. At the same time, the computer software takes this signal as an indication of when the computer initiated the data transfer.

PCI status and logic control: the function of peripheral device interconnection PCI is realized, DMA control of the PCI is completed, and stable and accurate receiving of high-speed code streams is ensured. The control of PCI bus interface, address and data control, address decoding, DMA data transmission and state control are completed. The address decoding generates input interface selection signals and sends the input interface selection signals to the input interface selection module, and the address decoding generates enable signals and sends the enable signals to the input signal processing module.

The working process of the invention is as follows:

the invention realizes that the data stored in the computer is continuously sent out from the external interface according to the preset format or receives the continuous code stream from the external interface and stores the continuous code stream in the computer by reasonably designing the configuration of the FPGA and utilizing the strong functions of the PCI interface chips on the mutual edges of the peripheral devices.

The working process of the code stream playing is as follows: firstly, the computer completes the initialization of hardware; then under the control of PCI interface chip, the code stream data in the internal storage area of the computer is transmitted to the FIFO of the external large-capacity memory in a DMA mode, wherein the DMA transmission of the data adopts a block transmission mode, the block size of each transmission is half of the capacity of the external FIFO, and simultaneously, the half-full mark of the external FIFO is used as an interrupt signal source to be fed back to the computer; then, an AD9851 frequency synthesis circuit generates a clock with the same size as the code rate of the code stream, the clock is controlled by a clock control module to continuously read out code stream data from an external FIFO and send the code stream data to a code rate adjustment module in the FPGA, and the code rate adjustment module realizes that the code stream is output to an output interface module at any code rate with the stepping precision of 1 HZ; the output interface selection module realizes that the code stream is output in an ASI format or an SPI format.

The working process of code stream receiving is as follows: firstly, the computer completes the initialization of hardware; then the computer controls the PCI interface chip to send a read-write instruction to the FPGA, the interior of the FPGA informs the input signal processing module to start writing data to the external FIFO through instruction decoding, and the half-full mark of the external FIFO is used as an interrupt signal source and is sent to the computer through the PCI interface chip so as to realize the communication between the external FIFO and the computer. Under the control of a PCI interface chip, data in an external FIFO is written into an internal memory of a computer in a DMA mode, wherein the DMA transmission of the data adopts a block transmission mode, the size of a block transmitted each time is half of the capacity of the external FIFO, the computer controls the DMA transmission of the data through a received interrupt signal, the realization mode is that the data is transmitted once by the DMA mode after the data is received, because the speed of the data input by the external interface is less than 27MBps, and the speed of the data read by the computer to the external FIFO is 27MBps, the data can not overflow in the external FIFO all the time, the continuous input data of the external interface can be ensured to be completely received, the FPGA controls the PCI state, and the work between the PCI interface chip and the external FIFO is coordinated.

Fig. 5 is a schematic diagram of the code stream transmission test of the present invention. When the invention is used for testing TS flow transmitted in a communication network, the device can be accessed to a node to be tested, the TS flow is collected into a computer through an ASI interface or an SPI interface, and then the collected code flow information is analyzed by using corresponding software, so that code flow information required or to be detected is obtained; when a test source is added to a node to be tested, the code stream stored in the PC can be played, the device supports the output of an ASI signal format and an SPI signal format respectively, the code rate of the output code stream can be changed randomly according to the requirement, and the precision of the changeable code rate reaches 1 Hz/s.

Claims

1. A high-speed code stream playing and receiving device based on PCI comprises a computer, a code stream playing card and a code stream receiving card, wherein the computer controls the code stream playing card and the code stream receiving card respectively through a peripheral device interconnection PCI interface chip to realize playing and receiving of code streams; the code stream playing card mainly comprises a programmable logic device FPGA, a peripheral device interconnection PCI interface chip, an external large-capacity memory FIFO and a peripheral device 27MHZ clock source, FPGA initialization and configuration, an AD9851 frequency synthesizer, an ASI output module and an SPI output module; the code stream receiving card mainly comprises a programmable logic device FPGA, a peripheral device interconnection PCI interface chip, an external large-capacity memory FIFO and a peripheral device 27MHZ clock source, FPGA initialization and configuration, an ASI input module and an SPI input module; the purpose and signal transmission relationship of the above-mentioned each component module are as follows:

the programmable logic device FPGA is mutually connected with the PCI interface chip and the external memory FIFO and is used for controlling the PCI state and coordinating the work between the PCI interface chip and the external FIFO;

the PCI interface chip is used for simplifying a PCI bus protocol, converting complex PCI bus operation into a simple local bus and matching with a programmable logic device FPGA to realize the sending and receiving of code stream data;

initializing and configuring the FPGA, and downloading relevant setting information required by the FPGA to a configuration space of the FPGA when the FPGA is powered on so that the FPGA can realize required functions;

the external large-capacity memory FIFO is used for caching data so as to make up the delay of DMA processing of a computer and internal data reading of the computer when the high-code-rate code stream is played/received, and simultaneously, the processing speed of the local end of the PCI interface chip to the data is improved by changing the read-write speed;

the SPI output module is used for finishing the level conversion of an output signal and converting the SPI signal into a signal suitable for cable transmission to output;

the ASI output module comprises a CY7B923 chip and a coupling shaping circuit, ASI signals are converted into signals suitable for cable transmission, the CY7B923 chip mainly realizes 8/10bit conversion of code words, insertion of synchronous words K28.5 and parallel/serial conversion, and the driving and coupling output of the ASI signals with the output rate constant at 270MHZ are completed;

the SPI input module is used for finishing the level conversion of input signals and outputting 11 paths of signals which accord with an SPI signal structure to the input interface selection module;

the ASI input module completes the coupling amplification and shaping of input signals, the coupling shaping circuit completes the recovery of clocks and data of the input signals, the CY7B933 chip realizes 10/8bit conversion, synchronous word removal K28.5 and serial-parallel conversion of code words, and 8 paths of parallel data signals are output to the input interface selection module.

2. The high-speed code stream playing and receiving device according to claim 1, wherein the configuration of the programmable logic device FPGA of the code stream playing card includes PCI status and logic control, NCO digitally controlled oscillator circuit, data cache, clock control, interrupt control, output clock synthesis and control, code rate adjustment, output interface selection, interface chip control module, and the usage and signal transmission relationship of each configuration module are as follows:

PCI state and logic control, which realizes the function of PCI interconnection of peripheral devices and completes the DMA control of PCI, and sends the output interface selection signal generated by address decoding to the output interface selection module; the generated clock control signal is output to a clock control module; the generated continuous pulse is sent to an NCO numerical control oscillating circuit to be used as a writing clock of the configuration word;

the data cache is used for caching configuration words input by a computer and data transmitted between the computer and an external large-capacity memory FIFO by using the FIFO provided in the programmable logic device FPGA, and transmitting different configuration words to an NCO circuit and an output clock synthesis and control module when the equipment is started;

the NCO numerically controlled oscillator circuit generates a clock signal according with the size of a new code rate according to the configuration word information sent by the computer and sends the clock signal to the code rate adjusting module;

the code rate adjusting module receives the code stream sent by the FIFO of the external large-capacity memory to realize the multi-code rate playing of the single program source;

clock control for controlling the clock synthesized by the AD9851 based on the input clock control signal and outputting the clock signal to the external mass storage as a clock for reading data from the external mass storage;

the output clock synthesis and control module is used for realizing the writing of the control configuration word into the AD9851 frequency synthesizer and controlling the AD9851 chip to output a corresponding clock to the clock control module;

the interrupt control module takes the half-full state of the external memory FIFO as an interrupt signal to realize the communication between external hardware and computer software, and the computer software takes the signal as a mark of when the computer initiates data transmission;

and the interface chip control module is used for carrying out logic control on the output data, the FIFO and the communication between the CY7B923 chips.

3. The high-speed code stream playing and receiving device according to claim 1, wherein the configuration of the programmable logic device FPGA of the code stream receiving card includes input interface selection, input signal processing, PCI status and logic control, interrupt control, data cache module, and the main purpose and signal transmission relationship of each configuration module are as follows:

the data caching module is used for caching data and ensuring stable DMA (direct memory access) transmission of the data between an external memory FIFO (first in first out) and an internal memory of the computer;

the interrupt control module is used for taking the half-full state of the external memory FIFO as an interrupt signal to realize the communication between external hardware and computer software, and simultaneously, the computer software takes the signal as a time mark for the computer to initiate data transmission;

PCI state and logic control module, which realizes PCI interconnection function of peripheral devices and completes DMA control of PCI, and sends the input interface selection signal generated by address decoding to the input interface selection module; and sending the generated enable signal to an input signal processing module.

4. The high-speed code stream playing and receiving device according to claim 2, wherein the code rate adjusting module mainly comprises internal fifos (a), (B), and (C), sync header detection, PCR insertion, subtracter and adder, counter, null packet generator, and null packet insertion module; wherein:

[1] an internal FIFO (A) which buffers the input TS stream by using the FIFO provided in the FPGA, and reads the TS stream by using a high clock of 27MHZ as a reading clock of the FIFO, thereby increasing the speed for the following processing;

[2] synchronous head detection, extracting the hidden synchronous signals in the input TS stream, processing the TS stream into a string of continuous TS packets, and then outputting the TS packets in two paths, wherein one path is used for PCR detection, and the other path is input into a PCR insertion module to finish the modification of PCR information;

[3] PCR detection, extracting PCR values in the TS stream, and outputting the PCR values to an addition and subtraction arithmetic unit;

[4] a subtracter for subtracting the PCR value extracted from the TS stream from the count generated by the counter with the reference clock of 27MHZ and sending the result as a new PCR value;

[5] PCR insertion, detecting input TS stream signals by taking packets as units, removing PCR values in a TS stream PCR domain, then inserting input new PCR values into the TS stream PCR domain, obtaining TS streams with modified PCR information and outputting the TS streams;

[6] an internal FIFO (B) which uses the FIFO provided in the FPGA to buffer the input TS stream, and simultaneously uses the input clock generated by the NCO circuit as the reading clock of the FIFO to read the TS stream and send the TS stream and the empty and full signals of the FIFO into the empty packet generator;

[7] the empty packet generator outputs a data stream with empty information which conforms to the TS packet format;

[8] inserting empty packets, and outputting the input TS stream by taking packets as units when the half-full signal of the internal FIFO (B) is effective, otherwise, outputting the empty packets;

[9] and the internal FIFO (C) buffers the input new TS stream by using the FIFO provided in the FPGA, and divides the output signal into two paths: one path enters a PCR expansion module to extract PCR information; the other path is transmitted to a PCR embedding module to finish the modification of the PCR information;

[10] an adder for adding the extracted PCR value to a value generated by a counter with a reference clock of 27MHZ and sending the result as a new PCR value;

[11] the counter uses the reference clock 27MHZ as a counting clock, and the generated count is input into the adder and the subtracter to be used for adjusting the PCR value.