CN107679003A - Data safe transmission system based on FPGA - Google Patents
Data safe transmission system based on FPGA Download PDFInfo
- Publication number
- CN107679003A CN107679003A CN201711048248.5A CN201711048248A CN107679003A CN 107679003 A CN107679003 A CN 107679003A CN 201711048248 A CN201711048248 A CN 201711048248A CN 107679003 A CN107679003 A CN 107679003A
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- Prior art keywords
- fpga
- data
- pci
- management module
- transmission system
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/606—Protecting data by securing the transmission between two devices or processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bioethics (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Storage Device Security (AREA)
Abstract
The invention discloses the data safe transmission system based on FPGA,Management module and PCI chips are controlled including FPGA,The FPGA controls management module is connected with PCI chips by local bus,The FPGA controls management module is connected with digital signal processor and memory,The PCI chips are connected with encrypted master and 1394b data transmission modules,The PCI chips are connected with 1394b data transmission modules by pci bus,The 1394b data transmission modules are connected with described in main frame and are provided with PLL in FPGA controls management module,Sync cap and asynchronous interface,The FPGA controls management module is also associated with flash storage,Serial storage,Digital signal processor,Static memory and AD/DA data-interfaces,The flash storage is connected with PLL,The present invention realizes the safe transmission of 1394b data transmission modules using FPGA control management modules and PCI chips,The security performance of offer system,It is fast with transmission speed,The characteristics of safe.
Description
Technical field
The present invention relates to field of data transmission, is the data safe transmission system based on FPGA specifically.
Background technology
21st century is information-based century, as the globalization of the development of network technology, particularly internet, information are common
The degree enjoyed further improves, the more and more deep various aspects for affecting social life of digital information, various based on interconnection
The web-based applications of network technology, as E-Government, ecommerce have also obtained fast development, the shared too busy to get away data biography of information
Defeated, for the requirement more and more higher of now how many data/address bus, existing bus standard is increasingly difficult to meet in practical application
Requirement；Network just progressively turns into inalienable part in people's work, life, open and general due to internet
Property, online most data messages are all disclosed to owner, so the data information security problem on network is also increasingly prominent
Go out.
The continuous propulsion of national information construction and the continuous development of network technology, the network more and more open in face of one
Environment, the information transfer of highly effective and safe has become characteristic essential in network economy development, due to hacker attacks, inside
Personnel such as divulge a secret at the reason, it is easy to and data occur or data loses leakage, the significant consequences thereby resulted in be able to not will make up,
By the application of secure memory techniques, the generation of such time can be effectively prevented to a great extent, is avoided due to data
Heavy losses caused by leakage, in fact, some statistics show, due to economic loss caused by loss of data and leakage
Considerably beyond expected loss, most enterprises and unit propose higher requirement to the safety of data information transfer, in information
It is then even more important to grasp core technology in addition to taking necessary safeguard measure and related regulation, policy for secure context.
The content of the invention
It is an object of the invention to provide the data safe transmission system based on FPGA, use on the basis of existing technology
FPGA controls management module and PCI chips to realize the safe transmission of 1394b data transmission modules, there is provided the performance of system, has
The characteristics of transmission speed is fast, safe.
The present invention is achieved through the following technical solutions：Data safe transmission system based on FPGA, including FPGA control pipes
Module and PCI chips are managed, the FPGA controls management module is connected with PCI chips by local bus, the FPGA control pipes
Reason module is connected with digital signal processor and memory, and the PCI chips are connected with encrypted master and 1394b data transfers
Module, the PCI chips are connected with 1394b data transmission modules by pci bus, the 1394b data transmission modules connection
There is main frame.
Further is that the present invention is better achieved, especially using following setting structures：The FPGA controls management module
PLL, sync cap and asynchronous interface are inside provided with, the FPGA controls management module is also associated with flash storage, serially deposited
Reservoir, digital signal processor, static memory and AD/DA data-interfaces, the flash storage are connected with PLL.
Further is that the present invention is better achieved, especially using following setting structures：The sync cap is connected with difference
Divide receiver, the differential receiver is connected with compression of images plate, and described image compression plate is also associated with DVD player；It is described
Asynchronous interface is connected with serial ports.
Further is that the present invention is better achieved, especially using following setting structures：The DVD player and AD/DA
Data-interface connects, and the asynchronous interface connects serial ports by RS232.
Further is that the present invention is better achieved, especially using following setting structures：The 1394b data transmission modules
The link layer chip and physical chip of interconnection are provided with, 1394b EBIs, institute are provided with the physical chip
1394b EBIs are stated with main frame to be connected.
Further is that the present invention is better achieved, especially using following setting structures：The PCI chips are total by PCI
Line connecting link layer chip, the PCI chips are also connected with read-only storage by universal serial bus, and the PCI chips use
PCI9054。
Further is that the present invention is better achieved, especially using following setting structures：1394b is provided with the main frame
Data collecting card.
Further is that the present invention is better achieved, especially using following setting structures：The AD/DA data-interfaces with
Sync cap connects in FPGA control management modules.
The present invention compared with prior art, has advantages below and beneficial effect：
The present invention uses PCI chips connection FPGA to control management module to realize the safe transmission of data, by the pci bus of complexity
The control of interface is converted to the control of relatively simple local bus interface, and PCI chips use 32 digits at local bus end
According to bus, message transmission rate is greatly improved.
Encrypted master is connected with PCI chips in the present invention, can be obtained more stable data transmission security guarantee, be kept away
Exempt from occur safety problem in data transmission procedure.
FPGA controls the asynchronous interface set in management module in the present invention, can be the different step numbers such as some control commands
It is believed that number by asynchronous interface be sent into FPGA control management module, handled by digital signal processor, digital signal processor
The efficiency of data transfer can further be improved by being combined with FPGA controls management module.
Brief description of the drawings
Fig. 1 is schematic structural view of the invention.
Embodiment
The present invention is described in further detail with reference to embodiment, but the implementation of the present invention is not limited to this.
Embodiment 1：
Data safe transmission system based on FPGA, including FPGA control management modules and PCI chips, the FPGA controls management
Module is connected with PCI chips by local bus, and the FPGA controls management module is connected with digital signal processor and storage
Device, the PCI chips are connected with encrypted master and 1394b data transmission modules, and encrypted master is turned in data-signal
It is encrypted when changing, the PCI chips are connected with 1394b data transmission modules by pci bus, the 1394b data
Transport module is connected with main frame；The safe transmission of data is realized using PCI chips and FPGA controls management module, by complexity
Pci bus controls the control for being converted to relatively simple local bus interface, greatly reduces the workload of system, and connect locally
Mouth end uses the data/address bus of 32, further improves message transmission rate；PCI chips are as a kind of bridging chip in local
Information transmission is provided between bus and pci bus.
Further is that the present invention is better achieved, especially using following setting structures：The FPGA controls management module
PLL, sync cap and asynchronous interface are inside provided with, the FPGA controls management module is also associated with flash storage, serially deposited
Reservoir, digital signal processor, static memory and AD/DA data-interfaces, the flash storage are connected with PLL；Data
The type of transmission is divided into synchrodata and asynchronous data, and synchrodata synchronizes transmission by sync cap, and asynchronous data is led to
Cross asynchronous interface and carry out asynchronous transmission, during synchronous transfer the data of varying number according to the time interval of regulation to an address
Send, it is desirable to which real-time is higher, it is not necessary to sends confirmation signal；Specific address, logarithm are transferred data to during asynchronous transmission
It is higher, it is necessary to send confirmation signal according to the accuracy requirement of transmission；Some asynchronous datas are passed to FPGA diabolos management mould by serial ports
, it is necessary to be handled by data signal processor during block, so be combined with digital signal processor can for FPGA control modules
To greatly improve data transmission efficiency；FPGA controls management module is realizing the information of the serioparallel exchange of data in static conversion
Device and serial storage are cached.
Further is that the present invention is better achieved, especially using following setting structures：The sync cap is connected with difference
Divide receiver, the differential receiver is connected with compression of images plate, and described image compression plate is also associated with DVD player；It is described
Asynchronous interface is connected with serial ports.In systems by the data that DVD player is sent through compression of images plate compression after by differential received
Device is passed to FPGA control management modules, or is sent into FPGA by AD/DA data-interfaces and controls management module, and both are synchronization
Data.
Further is that the present invention is better achieved, especially using following setting structures：The DVD player and AD/DA
Data-interface connects, and the asynchronous interface connects serial ports by RS232.
Embodiment 2：
The present embodiment is further optimized on the basis of above-described embodiment, as shown in figure 1, further is that this is better achieved
Invention, especially using following setting structures：The 1394b data transmission modules are provided with the link layer chip and thing of interconnection
Layer chip is managed, is provided with 1394b EBIs in the physical chip, the 1394b EBIs are connected with main frame；PCI
The data/address bus data conversion of local side into can be by the pci bus data that link layer chip transmits, then be passed through link layer by chip
Chip realizes the processing to synchrodata and asynchronous data, the data access by physical chip to bus, data is passed to
In the main frame for connecting 1394b data transmission modules.
Further is that the present invention is better achieved, especially using following setting structures：The PCI chips are total by PCI
Line connecting link layer chip, the PCI chips are also connected with read-only storage by universal serial bus, and read-only storage preserves backup
The data of transmission, the PCI chips use PCI9054.
Further is that the present invention is better achieved, especially using following setting structures：1394b is provided with the main frame
Data collecting card, by setting 1394b data collecting cards to complete the data transfer with 1394b data transmission systems.
Further is that the present invention is better achieved, especially using following setting structures：The AD/DA data-interfaces with
Sync cap connects in FPGA control management modules.
It is described above, be only presently preferred embodiments of the present invention, any formal limitation not done to the present invention, it is every according to
Any simply modification, the equivalent variations made according to the technical spirit of the present invention to above example, each fall within the protection of the present invention
Within the scope of.
Claims (8)
1. the data safe transmission system based on FPGA, it is characterised in that：Management module and PCI chips, institute are controlled including FPGA
State FPGA controls management module to be connected by local bus with PCI chips, the FPGA controls management module is connected with digital letter
Number processor and memory, the PCI chips are connected with encrypted master and 1394b data transmission modules, the PCI chips with
1394b data transmission modules are connected by pci bus, and the 1394b data transmission modules are connected with main frame.
2. the data safe transmission system according to claim 1 based on FPGA, it is characterised in that：The FPGA control pipes
Be provided with PLL, sync cap and asynchronous interface in reason module, the FPGA controls management module be also associated with flash storage,
Serial storage, digital signal processor, static memory and AD/DA data-interfaces, the flash storage are connected with PLL
Connect.
3. the data safe transmission system according to claim 2 based on FPGA, it is characterised in that：The sync cap connects
Differential receiver is connected to, the differential receiver is connected with compression of images plate, and described image compression plate is also associated with DVD broadcastings
Device；The asynchronous interface is connected with serial ports.
4. the data safe transmission system according to claim 3 based on FPGA, it is characterised in that：The DVD player
It is connected with AD/DA data-interfaces, the asynchronous interface connects serial ports by RS232.
5. the data safe transmission system according to claim 1 or 2 based on FPGA, it is characterised in that：The 1394b numbers
The link layer chip and physical chip of interconnection are provided with according to transport module, 1394b is provided with the physical chip
EBI, the 1394b EBIs are connected with main frame.
6. the data safe transmission system according to claim 5 based on FPGA, it is characterised in that：The PCI chips are also
Read-only storage is connected with by universal serial bus, the PCI chips use PCI9054.
7. the data safe transmission system according to claim 7 based on FPGA, it is characterised in that：The PCI chips lead to
Pci bus connecting link layer chip is crossed, the AD/DA data-interfaces control sync cap in management module to be connected with FPGA.
8. the data safe transmission system according to claim 8 based on FPGA, it is characterised in that：Set in the main frame
There are 1394b data collecting cards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711048248.5A CN107679003A (en) | 2017-10-31 | 2017-10-31 | Data safe transmission system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711048248.5A CN107679003A (en) | 2017-10-31 | 2017-10-31 | Data safe transmission system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107679003A true CN107679003A (en) | 2018-02-09 |
Family
ID=61143967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711048248.5A Withdrawn CN107679003A (en) | 2017-10-31 | 2017-10-31 | Data safe transmission system based on FPGA |
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| Country | Link |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1678086A (en) * | 2005-03-16 | 2005-10-05 | 西安电子科技大学 | High-speeld code-flow playing and receiving device based on PCI |
| CN101625669A (en) * | 2009-08-20 | 2010-01-13 | 上海交通大学 | IEEE1394b data transmission processing system based on FPGA |
| CN102279830A (en) * | 2011-08-01 | 2011-12-14 | 北京航空航天大学 | Multifunctional data acquisition module based on compact peripheral component interconnect (CPCI) bus |
| CN203659010U (en) * | 2013-12-30 | 2014-06-18 | 上海威亿实业有限公司 | Computer evidence obtaining device |
| CN105045704A (en) * | 2015-06-24 | 2015-11-11 | 哈尔滨工业大学 | Method for implementing data exchange between boards by using PCI master mode |
| CN106713094A (en) * | 2016-12-26 | 2017-05-24 | 北京旋极信息技术股份有限公司 | 1394 data collection module |
-
2017
- 2017-10-31 CN CN201711048248.5A patent/CN107679003A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1678086A (en) * | 2005-03-16 | 2005-10-05 | 西安电子科技大学 | High-speeld code-flow playing and receiving device based on PCI |
| CN101625669A (en) * | 2009-08-20 | 2010-01-13 | 上海交通大学 | IEEE1394b data transmission processing system based on FPGA |
| CN102279830A (en) * | 2011-08-01 | 2011-12-14 | 北京航空航天大学 | Multifunctional data acquisition module based on compact peripheral component interconnect (CPCI) bus |
| CN203659010U (en) * | 2013-12-30 | 2014-06-18 | 上海威亿实业有限公司 | Computer evidence obtaining device |
| CN105045704A (en) * | 2015-06-24 | 2015-11-11 | 哈尔滨工业大学 | Method for implementing data exchange between boards by using PCI master mode |
| CN106713094A (en) * | 2016-12-26 | 2017-05-24 | 北京旋极信息技术股份有限公司 | 1394 data collection module |
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Application publication date: 20180209 |