CN206712810U - A kind of high speed password card based on PCI E buses - Google Patents
A kind of high speed password card based on PCI E buses Download PDFInfo
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Abstract
The utility model discloses a kind of high speed password card based on PCI E buses, including fpga logic chip, master cpu chip, cryptographic algorithm module, noise source WNG9 chips, PCI E interfaces module, safety protection module；Master cpu chip is connected with SRAM and SPI FLASH, and master cpu chip is connected by serial ports with safety protection module；Cryptographic algorithm module includes SM1, SM2, SM3, SM4 algorithm chip, cryptographic algorithm module connection fpga logic chip；Noise source WNG9 chips are provided with 2 groups, and every group of noise source WNG9 chip is provided with 2 tunnels, noise source WNG9 chips connection fpga logic chip；PCI E interfaces module connects fpga logic chip；Safety protection module connects fpga logic chip.The utility model ensures confidentiality, integrality and the non-repudiation of sensitive data, and overall is functional.
Description
Technical field
It the utility model is related to information security field technical field, and in particular to a kind of high speed based on PCI-E buses is close
Code card.
Background technology
PCI-Express (peripheral component interconnect express) is a kind of high speed serialization
Computer expansion bus standard, its original entitled " 3GIO ", it is to be proposed by Intel in 2001, it is intended to substitute old
PCI, PCI-X and AGP bus standard.PCIe belongs to the point-to-point binary channels high bandwidth transmission of high speed serialization, the equipment connected point
With bandwidth chahnel is exclusively enjoyed, bus bandwidth is not shared, mainly supports active power management, error reporting, end-to-end reliability passes
It is defeated, the function such as hot plug and service quality (QOS).PCIe transfers to ability after PCI-SIG (PCI particular interests tissue) certification issue
It is renamed as " PCI-Express ", referred to as " PCI-E ".Its main advantage is exactly high, the current v2.x versions of message transmission rate
X16 passages can reach 8GB/s, and also sizable development potentiality.
With attention of the country to information security, current many departments and enterprise requirements are entered using domestic algorithm to its information
Row protection, therefore higher requirement is proposed to domestic password product.To meet the equipment such as server, gateway to cryptographic algorithm speed
Degree and the demand of security, present many manufacturers have developed the cipher card based on pci interface.Pci bus uses parallel bus knot
Structure, all external equipments share bus bandwidth in same bus, employ parallel interconnection, and this leverages system entirety
Performance, while parallel signal also seriously constrains the further lifting of speed in the future due to interfering.With user
Scale increases substantially, and finds the bottleneck of PCI cipher cards and causes gateway handling capacity not lifted, can not meet high performance network application
Needs.
Utility model content
The purpose of this utility model is to provide a kind of high speed password card based on PCI-E buses, can be all kinds of safety
Platform provides multi-process, the high speed password computational service of multithreading, meets it to digital signature/sign test, symmetrical/asymmetric plus solution
Close, data integrity verifying, true random number generate, the requirement of the function such as key generation and management, ensure the secret of sensitive data
Property, integrality and non-repudiation.
The concrete technical scheme that the utility model solves above-mentioned technical problem is as follows：A kind of high speed based on PCI-E buses
Cipher card, including fpga logic chip, master cpu chip, cryptographic algorithm module, noise source WNG9 chips, PCI-E interface mould
Block, safety protection module；The described cryptographic algorithm module of described fpga logic chip connection, noise source WNG9 chips, PCI-E
Interface module, master cpu chip；Described master cpu chip is connected with SRAM and SPI FLASH, and master cpu chip passes through string
Mouth is connected with safety protection module；Described cryptographic algorithm module includes SM1, SM2, SM3, SM4 algorithm chip, cryptographic algorithm mould
The described fpga logic chip of block connection；Described noise source WNG9 chips are provided with 2 groups, and every group of noise source WNG9 chip is provided with 2
Road, the described fpga logic chip of noise source WNG9 chips connection；The described fpga logic of described PCI-E interface module connection
Chip；Described safety protection module includes light current storage control chip, environmental sensor, button lithium battery, flexible PCB, outer
Shell, the described fpga logic chip of safety protection module connection.
A kind of high speed password card based on PCI-E buses as described above, the model that described fpga logic chip is selected
It is the XC6SLX75-3FGG676C of XILINX Spartan-6 series.Fpga logic chip is handled for the core transfer of encrypted card
Unit, it is responsible for communicating with PCI-E interface module, gathers with examining noise source signal and cryptographic algorithm chip communication and master control core
The work such as piece communication.
A kind of high speed password card based on PCI-E buses as described above, described master cpu chip use Tongfang share
32 SOC TF32A09 of Co., Ltd, the close model SSX1019 of business.Master cpu chip is responsible for the scheduling work of whole board
Make, realized by fpga logic chip and communicated with host, call the external algorithm chips of FPGA, external extension SRAM and extension
SPI Flash, by serial ports and safety protection module interactive information, the identity for realizing user by intelligent card interface differentiates, real
When to the working condition of outer display board card.
A kind of high speed password card based on PCI-E buses as described above, described cryptographic algorithm module include SM1 algorithms
Chip, SM2 algorithm chips, SM3 algorithm chips, SM4 algorithm chips；Described SM1 algorithm chips think electronics skill using Beijing is grand
The SSX30-D chips of art Co., Ltd, the block length of SM1 algorithm chip block ciphers is 128 bits, and key length is
128 bits, SSX30-D chips have ECB, CBC and OFB operational pattern and two kinds of monobus, dual bus working methods,
Encryption and decryption speed reaches as high as 1.4Gbps under ecb mode dual bus working method.
SM2 algorithm chips use the HSM2-H2 chips of Beijing Hong Si Electron Technology Co., Ltd, the close model of business
SSX1303, SM2 algorithm chip are high-performance cryptographic algorithms harmonizing processor chip, and HSM2-H2 chips realize national standard SM2
With SM3 cryptographic algorithm functions, the chip can realize time/second of digital signature 5000 of SM2 algorithms, the digital signature of SM2 algorithms
Verify 2500 times/second；
SM3 algorithm chips, SM4 algorithm chips use the HSM4-H1 of Beijing Hong Si Electron Technology Co., Ltd, the close model of business
For SSX1304.The chip is High Performance Block Cipher algorithm chip, and the chip has ECB, CBC, OFB operational pattern and list
Two kinds of bus, dual bus working methods, encryption and decryption speed reaches as high as 2.0Gbps under ecb mode dual bus working method.
Encryption and decryption speed reaches as high as 1.5Gbps under CBC pattern dual bus working methods.
A kind of high speed password card based on PCI-E buses as described above, described SM1 algorithm chips, SM4 algorithm chips
2 are respectively used, concurrent working, so as to improve cipher card overall performance.
A kind of high speed password card based on PCI-E buses as described above, described noise source WNG9 chips use Beijing
The HSNWNG9 of Hong Si Electron Technology Co., Ltd, the close model SXH20147994 of business.The chip has already been through national password
The examination ＆ approval of management board, meet national Password Management office issue《Randomness inspection criterion》It is required that.Cipher card selects 4 tunnel noise sources
Chip, point 2 groups of uses, every group to two-way noise source XOR.Between two groups of noise sources by the way of table tennis uses, once
After use, exchange next time and use another group.
A kind of high speed password card based on PCI-E buses as described above, described PCI-E interface module use Intel
NHI350AM4 chips.
A kind of high speed password card based on PCI-E buses as described above, described master cpu chip are connected with smart card
Read write line, intelligent card read/write device are equipped with management card and subscriber card.
Safety protection module is by light current storage control chip, environmental sensor, button lithium battery, flexible PCB, metal shell
Deng composition.Safety protection module monitors in real time to the working environment of equipment, if the ambient parameter monitored exceeds default model
(temperature, voltage) is enclosed, or is disassembled, safety protection module destroys the key components of its storage inside and notifies main control chip pin
Temporary resource is ruined, resets PCI-E cipher cards.After detecting the physics intrusion behavior such as dismounting, cutting, drilling, safety is destroyed immediately
Other relevant sensitization security parameters are destroyed in key components in protection module, notice master control.
The utility model method has the following advantages that：Multi-process, the high speed of multithreading can be provided for all kinds of security platforms
Crypto-operation service, meet it to digital signature/sign test, symmetrical/asymmetric encryption and decryption, data integrity verifying, true random number
Generation, the requirement of the function such as key generation and management, ensures the confidentiality, integrality and non-repudiation of sensitive data, overall
It is functional, while disclosure satisfy that the needs of high performance network application.
Brief description of the drawings
High speed password card hardware configuration connection diagrams of the Fig. 1 based on PCI-E buses；
High speed password card workflow diagrams of the Fig. 2 based on PCI-E buses.
Embodiment
Following examples are used to illustrate the utility model, but are not limited to the scope of the utility model.
As shown in figure 1, a kind of high speed password card based on PCI-E buses, including fpga logic chip 1, master cpu chip
2nd, cryptographic algorithm module 3, noise source WNG9 chips 4, PCI-E interface module 5, safety protection module 6；Described fpga logic core
Piece 1 connects described cryptographic algorithm module 3, noise source WNG9 chips 4, PCI-E interface module 5, master cpu chip 2；Described
Master cpu chip 2 is connected with SRAM7 and SPI FLASH8, and master cpu chip 2 is connected by serial ports with safety protection module 6；
Described cryptographic algorithm module 3 includes SM1, SM2, SM3, SM4 algorithm chip, and cryptographic algorithm module 3 connects described FPGA and patrolled
Collect chip 1；Described noise source WNG9 chips 4 are provided with 2 groups, and every group of noise source WNG9 chip 4 is provided with 2 tunnels, noise source WNG9 cores
Piece 4 connects described fpga logic chip 1；Described PCI-E interface module 5 connects described fpga logic chip 1；Described
Safety protection module 6 includes light current storage control chip, environmental sensor, button lithium battery, flexible PCB, shell, security protection
Module 6 connects described fpga logic chip 1.
In one embodiment of high speed password card based on PCI-E buses, the model of described fpga logic chip 1 selection
It is the XC6SLX75-3FGG676C of XILINX Spartan-6 series.Fpga logic chip 1 is handled for the core transfer of encrypted card
Unit, it is responsible for communicating with PCI-E interface module 5, gathers with examining noise source signal and cryptographic algorithm chip communication and master control
The work such as chip communication.
In one embodiment of high speed password card based on PCI-E buses, described master cpu chip 2 uses Tongfang stock
Part 32 SOC TF32A09 of Co., Ltd, the close model SSX1019 of business.Master cpu chip 2 is responsible for the scheduling of whole board
Work, realized by fpga logic chip 1 and communicated with host, call the external algorithm chips of FPGA, external extension SRAM and expansion
SPI Flash are opened up, by serial ports and the interactive information of safety protection module 6, the identity for realizing user by intelligent card interface differentiates,
In real time to the working condition of outer display board card.
In one embodiment of high speed password card based on PCI-E buses, described cryptographic algorithm module 3 is calculated including SM1
Method chip, SM2 algorithm chips, SM3 algorithm chips, SM4 algorithm chips；Described SM1 algorithm chips use the grand think of electronics in Beijing
The SSX30-D chips of Technology Co., Ltd., the block lengths of SM1 algorithm chip block ciphers are 128 bits, key length
For 128 bits, SSX30-D chips have ECB, CBC and OFB operational pattern and two kinds of monobus, dual bus working methods,
Encryption and decryption speed reaches as high as 1.4Gbps under ecb mode dual bus working method.
SM2 algorithm chips use the HSM2-H2 chips of Beijing Hong Si Electron Technology Co., Ltd, the close model of business
SSX1303, SM2 algorithm chip are high-performance cryptographic algorithms harmonizing processor chip, and HSM2-H2 chips realize national standard SM2
With SM3 cryptographic algorithm functions, the chip can realize time/second of digital signature 5000 of SM2 algorithms, the digital signature of SM2 algorithms
Verify 2500 times/second；
SM3 algorithm chips, SM4 algorithm chips use the HSM4-H1 of Beijing Hong Si Electron Technology Co., Ltd, the close model of business
For SSX1304.The chip is High Performance Block Cipher algorithm chip, and the chip has ECB, CBC, OFB operational pattern and list
Two kinds of bus, dual bus working methods, encryption and decryption speed reaches as high as 2.0Gbps under ecb mode dual bus working method.
Encryption and decryption speed reaches as high as 1.5Gbps under CBC pattern dual bus working methods.
In one embodiment of high speed password card based on PCI-E buses, described SM1 algorithm chips, SM4 algorithm chips
2 are respectively used, concurrent working, so as to improve cipher card overall performance.
In one embodiment of high speed password card based on PCI-E buses, described noise source WNG9 chips 4 use Beijing
The HSNWNG9 of Hong Si Electron Technology Co., Ltd, the close model SXH20147994 of business.The chip has already been through national password
The examination ＆ approval of management board, meet national Password Management office issue《Randomness inspection criterion》It is required that.Cipher card selects 4 tunnel noise sources
Chip, point 2 groups of uses, every group to two-way noise source XOR.Between two groups of noise sources by the way of table tennis uses, once
After use, exchange next time and use another group.
In one embodiment of high speed password card based on PCI-E buses, described PCI-E interface module 5 uses Intel
NHI350AM4 chips.
In one embodiment of high speed password card based on PCI-E buses, described master cpu chip 2 is connected with intelligence
Card reader, intelligent card read/write device are equipped with management card and subscriber card.
In one embodiment of high speed password card based on PCI-E buses, safety protection module 6 stores control core by light current
Piece, environmental sensor, button lithium battery, flexible PCB, metal shell etc. form.Working environment of the safety protection module 6 to equipment
Monitoring in real time, if the ambient parameter monitored exceeds default scope (temperature, voltage), or is disassembled, security protection mould
Block 6 destroys the key components of its storage inside and notifies main control chip to destroy temporary resource, resets PCI-E cipher cards.Detect
After the physics intrusion behaviors such as dismounting, cutting, drilling, key components in safety protection module 6 are destroyed immediately, and notice master control destroys it
His relevant sensitization security parameter.
The utility model key technology is performed parallel using block cipher chip multipath：PCI-E cipher cards support SM1
With SM4 symmetric key algorithms.To lift cipher card symmetric key algorithm encryption/decryption speed, every PCI-E cipher card has selected two
Piece SM1 algorithm chips and two panels SM4 algorithm chips are run parallel.Support three-level key structure system：PCI-E cipher cards support three
Level key structure system, wherein protection key is first order key, for protecting, managing other safety in secondary key and system
Sensitive parameter.
User key, key-encrypting key are secondary key.Using " three or two thresholding " mechanism realize in cipher card key and
The carrying out safety backup of sensitive data and recovery, only just had using wherein two simultaneously and back up and recover authority.Cipher key backup machine
System had both solved device damage, key is lost or the security risk of key damage, ensures the safety of user's ciphertext data, solves again
Backup and the security of recovery operation in itself.
Session key is three-level key, for carrying out encryption and decryption to session data.
Referring to Fig. 2, the utility model function, which is realized, is broadly divided into initialization, crypto-operation function and key management three parts
Work.Cipher card needs first to carry out initial work when running, input, generation key and account information, and it is close to be loaded into PCI-E
Code card and binding smart card, then can just provide crypto-operation function.Cipher card supports protection key, user key and key
Encryption key, session key three-level key structure system, wherein protection key be first order key, for protect user key,
Key-encrypting key, key management work run through whole system.
Initial work mainly generates cipher card management account, configuration cipher card running parameter, generation protection key, distribution
User account, generation user key and key-encrypting key, the generation device keyses pair of PCI-E cipher cards.Now password sticks into
Enter ready state.
PCI-E cipher cards in ready state, after differentiating operator's identity, open the operation associated with identity and role
Authority, crypto-operation function is provided for application program.
Cipher card processing message workflow is as follows：Application program sends one section of message-protocol layer module by api interface
Data subpackage transmission-cipher card is received, handled, loopback-protocol layer module receives, group bag-api interface function returns.
Cipher card receives the packet that main frame sends over, according to protocol fields, be divided into FPGA directly handle message and
Master cpu participates in processing message situation.Flow chart of data processing is as follows：
FPGA directly handles message situation (below by taking SM4 encryption and decryption computings as an example)：Main frame application data passes through api interface
Message-protocol layer module is sent by data subpackage transmission-cipher card PCI-E interface chip reception-FPGA algorithm interface modules
Manage unit-SM4 algorithm chip processing-FPGA algorithm interfaces modular processing unit-cipher card PCI-E interface chip transmission-agreement
Layer module returns to data receiver, group bag-api function.
The flow mainly realizes the crypto-operation higher to performance requirement.
Below by taking DES encryption and decryption computings as an example, illustrate that master cpu participates in processing message situation：Participated in when needing master cpu
When handling message, main frame application data sends message-protocol layer module by data subpackage transmission-cipher card by api interface
Write-in reads data exchange with master cpu data exchange buffering area-master cpu inside the processing unit-FPGA of PCI-E interface module 5
Buffering area and analytic message-master cpu handled, call cryptographic algorithm computing after-master cpu exchanges data write back data
5 processing units of cipher card PCI-E interface module-cipher card PCI-E interface chip transmission-agreement is sent to inside buffering area-FPGA
Layer module returns to data receiver, group bag-api function.
Although above having made detailed description to the utility model with generality explanation and specific embodiment,
On the basis of the utility model, it can be made some modifications or improvements, this is apparent to those skilled in the art
's.Therefore, the these modifications or improvements on the basis of without departing from the utility model spirit, belonging to the utility model will
Seek the scope of protection.
Claims (8)
- A kind of 1. high speed password card based on PCI-E buses, it is characterised in that：Including fpga logic chip, master cpu chip, Cryptographic algorithm module, noise source WNG9 chips, PCI-E interface module, safety protection module；Described fpga logic chip connection Described cryptographic algorithm module, noise source WNG9 chips, PCI-E interface module, master cpu chip；Described master cpu chip SRAM and SPI FLASH are connected with, master cpu chip is connected by serial ports with safety protection module；Described cryptographic algorithm mould Block includes SM1, SM2, SM3, SM4 algorithm chip, the described fpga logic chip of cryptographic algorithm module connection；Described noise source WNG9 chips are provided with 2 groups, and every group of noise source WNG9 chip is provided with 2 tunnels, the described fpga logic core of noise source WNG9 chips connection Piece；The described fpga logic chip of described PCI-E interface module connection；Described safety protection module includes light current storage control Coremaking piece, environmental sensor, button lithium battery, flexible PCB, shell, the described fpga logic chip of safety protection module connection.
- A kind of 2. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described FPGA The model that logic chip is selected is the XC6SLX75-3FGG676C of XILINX Spartan-6 series.
- A kind of 3. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described master control Cpu chip uses 32 SOC TF32A09 of Tongfang Co., Ltd, the close model SSX1019 of business.
- A kind of 4. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described password Algoritic module includes SM1 algorithm chips, SM2 algorithm chips, SM3 algorithm chips, SM4 algorithm chips；Described SM1 algorithm chips Using the SSX30-D chips of Beijing Hong Si Electron Technology Co., Ltd；SM2 algorithm chips are limited using the grand think of electronic technology in Beijing The HSM2-H2 chips of company, the close model SSX1303 of business；Described SM3 algorithm chips, SM4 algorithm chips use the grand think of in Beijing The HSM4-H1 of Electron Technology Co., Ltd, the close model SSX1304 of business.
- A kind of 5. high speed password card based on PCI-E buses according to claim 4, it is characterised in that：Described SM1 is calculated Method chip, SM4 algorithm chips respectively use 2, concurrent working.
- A kind of 6. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described noise Source WNG9 chips use the HSNWNG9, the close model SXH20147994 of business of Beijing Hong Si Electron Technology Co., Ltd.
- A kind of 7. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described PCI-E Interface module uses Intel NHI350AM4 chips.
- A kind of 8. high speed password card based on PCI-E buses according to claim 1, it is characterised in that：Described master control Cpu chip is connected with intelligent card read/write device, and intelligent card read/write device is equipped with management card and subscriber card.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109145568A (en) * | 2018-08-21 | 2019-01-04 | 西安得安信息技术有限公司 | A kind of full algorithm cipher card and its encryption method based on PCI-E interface |
| CN109344664A (en) * | 2018-08-21 | 2019-02-15 | 西安得安信息技术有限公司 | A kind of cipher card and its encryption method that based on FPGA data are carried out with algorithm process |
| CN110868289A (en) * | 2019-11-13 | 2020-03-06 | 深圳前海智安信息科技有限公司 | Cipher machine system capable of expanding distributed computation and control response method thereof |
| CN111314078A (en) * | 2019-12-10 | 2020-06-19 | 南京昆睿通信技术有限公司 | SIM type password card system with double chip design |
| CN112910932A (en) * | 2021-04-30 | 2021-06-04 | 北京数盾信息科技有限公司 | Data processing method, device and system |
| CN112910646A (en) * | 2021-04-30 | 2021-06-04 | 北京数盾信息科技有限公司 | Data processing method and device of server cipher machine and server cipher machine |
| CN113094762A (en) * | 2021-04-30 | 2021-07-09 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113194097A (en) * | 2021-04-30 | 2021-07-30 | 北京数盾信息科技有限公司 | Data processing method and device for security gateway and security gateway |
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2017
- 2017-05-10 CN CN201720518894.2U patent/CN206712810U/en active Active
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109145568A (en) * | 2018-08-21 | 2019-01-04 | 西安得安信息技术有限公司 | A kind of full algorithm cipher card and its encryption method based on PCI-E interface |
| CN109344664A (en) * | 2018-08-21 | 2019-02-15 | 西安得安信息技术有限公司 | A kind of cipher card and its encryption method that based on FPGA data are carried out with algorithm process |
| CN110868289A (en) * | 2019-11-13 | 2020-03-06 | 深圳前海智安信息科技有限公司 | Cipher machine system capable of expanding distributed computation and control response method thereof |
| CN111314078A (en) * | 2019-12-10 | 2020-06-19 | 南京昆睿通信技术有限公司 | SIM type password card system with double chip design |
| CN112910932A (en) * | 2021-04-30 | 2021-06-04 | 北京数盾信息科技有限公司 | Data processing method, device and system |
| CN112910646A (en) * | 2021-04-30 | 2021-06-04 | 北京数盾信息科技有限公司 | Data processing method and device of server cipher machine and server cipher machine |
| CN113094762A (en) * | 2021-04-30 | 2021-07-09 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN112910646B (en) * | 2021-04-30 | 2021-07-20 | 北京数盾信息科技有限公司 | Data processing method and device of server cipher machine and server cipher machine |
| CN112910932B (en) * | 2021-04-30 | 2021-07-20 | 北京数盾信息科技有限公司 | Data processing method, device and system |
| CN113194097A (en) * | 2021-04-30 | 2021-07-30 | 北京数盾信息科技有限公司 | Data processing method and device for security gateway and security gateway |
| CN113094762B (en) * | 2021-04-30 | 2021-12-07 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113194097B (en) * | 2021-04-30 | 2022-02-11 | 北京数盾信息科技有限公司 | Data processing method and device for security gateway and security gateway |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A High Speed Password Card Based on PCI-E Bus Effective date of registration: 20181226 Granted publication date: 20171205 Pledgee: Zhongguancun Beijing technology financing Company limited by guarantee Pledgor: BEIJING SHUDUN INFORMATION TECHNOLOGY CO.,LTD. Registration number: 2018990001229 |
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