CN110098158A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN110098158A
CN110098158A CN201910083632.1A CN201910083632A CN110098158A CN 110098158 A CN110098158 A CN 110098158A CN 201910083632 A CN201910083632 A CN 201910083632A CN 110098158 A CN110098158 A CN 110098158A
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China
Prior art keywords
substrate
semiconductor chip
chip
semiconductor
illusory
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CN201910083632.1A
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CN110098158B (zh
Inventor
李秀昶
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供一种半导体封装件，其包括：基底，具有第一表面和与第一表面背对的第二表面；多个第一垫和多个第二垫，分别设置在第一表面和第二表面上并彼此电连接；半导体芯片，设置在第一表面上并连接到多个第一垫；虚设芯片，具有与半导体芯片的一个侧表面面对的侧表面，设置在第一表面上并在与第一表面平行的方向上与半导体芯片分隔开，虚设芯片在与第一表面垂直的方向上具有比半导体芯片的上表面低的上表面；底填件，设置在半导体芯片与第一表面之间，具有在与第一表面垂直的方向上沿着半导体芯片和虚设芯片的彼此面对的侧表面延伸的延伸部分，延伸部分的上端部设置为比半导体芯片的上表面低；密封材料，设置在第一表面上并密封半导体芯片和虚设芯片。

Description

半导体封装件
本申请要求于2018年1月29日在韩国知识产权局提交的第10-2018-0010700号韩国专利申请的优先权的权益，所述韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
根据本发明构思的示例实施例涉及一种包括半导体芯片的半导体封装件。
背景技术
随着电子工业的发展，对电子组件的高性能、高速度和小型化的需求正在增长。根据这种趋势，通常通过在单个中介件或者封装基底上安装多个半导体芯片来制造封装件。由于构成半导体封装件的单个组件之间的热膨胀系数(CTE)的差异，所以会发生半导体封装件弯曲的翘曲现象，用于控制半导体封装件的翘曲的技术可以是有用的。
发明内容
示例实施例提供了一种能够控制翘曲的半导体封装件。
根据示例实施例，半导体封装件包括：基底，具有第一表面和与所述第一表面背对的第二表面；多个第一垫，设置在所述基底的所述第一表面上，多个第二垫，设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫；虚设芯片，具有与所述半导体芯片的一个侧表面面对的侧表面，设置在所述基底的所述第一表面上并且在与所述基底的所述第一表面平行的方向上与所述半导体芯片分隔开，所述虚设芯片在与所述基底的所述第一表面垂直的方向上具有比所述半导体芯片的所述上表面低的上表面；底填件，设置在所述半导体芯片与所述基底的所述第一表面之间，具有在与所述基底的所述第一表面垂直的所述方向上沿着所述半导体芯片和所述虚设芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述半导体芯片的所述上表面低；以及密封材料，设置在所述基底的所述第一表面上并且密封所述半导体芯片和所述虚设芯片。
根据示例实施例，半导体封装件包括：基底，具有第一表面和与所述第一表面背对的第二表面；多个第一垫，设置在所述基底的所述第一表面上，多个第二垫，设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；第一半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫的第一部分；第二半导体芯片，设置在所述基底的所述第一表面上并在与所述基底的所述第一表面平行的方向上与所述第一半导体芯片分隔开，并且连接到所述多个第一垫的与所述多个垫的所述第一部分不同的第二部分；虚设芯片，设置在所述基底的所述第一表面上以至少具有与所述第一半导体芯片的一个侧表面面对的侧表面，具有在与所述基底的所述第一表面垂直的方向上比所述第一半导体芯片的所述上表面低的上表面；底填件，设置在所述第一半导体芯片、所述第二半导体芯片与所述基底的所述第一表面之间，具有在与所述基底的所述第一表面垂直的所述方向上沿着所述第一半导体芯片和所述虚设芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述第一半导体芯片的所述上表面低；以及密封材料，设置在所述基底的所述第一表面上并且密封所述第一半导体芯片、所述第二半导体芯片和所述虚设芯片。
根据示例实施例，半导体封装件包括：基底，具有第一表面和与所述第一表面背对的第二表面；多个第一垫，设置在所述基底的所述第一表面上，多个第二垫，设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；第一半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫的第一部分；第二半导体芯片，具有面对所述第一半导体芯片的一个侧表面的侧表面，设置在所述基底的所述第一表面上，并且在与所述基底的所述第一表面垂直的方向上具有比所述第一半导体芯片的在与所述基底的所述第一表面垂直的方向上的安装高度低的安装高度；底填件，设置在所述第一半导体芯片、所述第二半导体芯片与所述基底的所述第一表面之间，具有在与所述基底的所述第一表面垂直的所述方向上沿着所述第一半导体芯片和所述第二半导体芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述第一半导体芯片的所述安装高度低；以及密封材料，设置在所述基底的所述第一表面上，以在覆盖所述底填件的所述延伸部分的同时密封所述第一半导体芯片和所述第二半导体芯片，所述密封材料的热膨胀系数比所述底填件的热膨胀系数低。
附图说明
通过下面结合附图进行的详细描述，本发明构思的以上及其它方面、特征和优点将被更加清楚地理解，在附图中：
图1是示出根据示例实施例的半导体封装件的剖面侧视图；
图2是图1中示出的半导体封装件的平面图；
图3和图4是图1中示出的半导体封装件的一部分的放大剖视图；
图5是示出根据虚设芯片的安装高度改善翘曲的效果的曲线图；
图6是示出采用图1中示出的半导体封装件的模块的剖面侧视图；
图7是根据示例实施例的半导体封装件的平面图；
图8是图7中示出的半导体封装件的沿线X1-X1'截取的剖面侧视图；
图9是图7中示出的半导体封装件的沿线X2-X2'截取的剖面侧视图；
图10是图7中示出的半导体封装件的沿线Y-Y'截取的剖面侧视图；
图11是示出采用图8中示出的半导体封装件的模块的剖面侧视图；
图12是根据示例实施例的半导体封装件的平面图；
图13是图12中示出的半导体封装件的沿线X-X'截取的剖面侧视图；以及
图14是示出根据本公开的示例性实施例的制造将在半导体封装件中使用的半导体器件的方法的流程图。
具体实施方式
在下文中，将参照附图描述本发明构思的示例实施例。
图1是示出根据示例实施例的半导体封装件的剖面侧视图，图2是图1中示出的半导体封装件的平面图。例如，图1是图2的半导体封装件的沿线I-I'截取的剖视图。
参照图1和图2，根据示例实施例的半导体封装件100A可以包括：中介件110，具有第一表面110A(可被称为中介件110的上表面)和背对的第二表面110B(可被称为中介件110的下/底表面)；半导体芯片120和虚设芯片150，设置在中介件110的第一表面110A上；底填件161，设置在中介件110的第一表面110A与半导体芯片120之间；以及密封材料165，覆盖半导体芯片120和虚设芯片150。根据示例性实施例，中介件110的第一表面110A可以面对半导体芯片120和虚设芯片150的底表面，第二表面110B可以背离半导体芯片120与虚设芯片150的底表面。根据示例性实施例，中介件110可以在同一封装件内位于其它半导体芯片(未示出)上方。
在本示例实施例中采用的中介件110可以包括形成在基体材料111中的布线电路114以及分别设置在第一表面110A和第二表面110B上并且通过布线电路114彼此连接的多个第一垫(pad，或称为“焊盘”)112和多个第二垫(pad，或称为“焊盘”)113。在图1中，布线电路114可以在区域的仅一部分中由虚线来表示，并且可以包括与第一垫112和第二垫113中的每个相关的每个布线电路114。根据实施例，设置在中介件110的第一表面110A上的多个第一垫112通过布线电路114电连接到设置在中介件110的第二表面110B上的多个第二垫113。如在这里所使用的，除非另有说明，否则被描述为“电连接”的项被构造为使得电信号可以从一个项传到另一项。
根据示例性实施例，虚设芯片150可以是由晶体半导体材料形成的单片块，诸如，晶体硅的块和/或与形成半导体芯片120的基底的晶体材料相同的晶体材料的块。因此，虚设芯片150和半导体芯片120的CTE可以基本相同(例如，变化小于10％)。另外，根据示例性实施例，虚设芯片150可以不电连接到布线电路114。虚设芯片150可以不包括任何形成在其中的集成电路。根据示例性实施例，中介件110的基体材料111可以是硅基底(例如，单晶硅)。在另一示例实施例中，基体材料111不限于此，并且可以是印刷电路板(PCB)。例如，基体材料111可以是诸如环氧树脂的热固性树脂，或者诸如聚酰亚胺的热塑性树脂，或者光敏绝缘层。
外部端子115可以设置在于中介件110的第二表面110B上设置的多个第二垫113上。外部端子115可以包括锡(Sn)、铅(Pb)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)和铋(Bi)中的至少一种金属，或者它们的合金。
半导体芯片120可以具有有效表面和非有效表面，所述有效表面与中介件110的第一表面110A面对，所述非有效表面与有效表面背对并且背离中介件110的第一表面110A。连接垫122可以设置在半导体芯片120的有效表面上。连接垫122可以包括连接电极(未示出)。连接端子116可以设置在连接垫122的连接电极与中介件110的第一垫112之间，半导体芯片120可以是通过连接端子116与中介件110的第一表面110A接合的倒装芯片。
在本示例性实施例中采用的虚设芯片150可以设置在中介件110的第一表面110A上并且在与第一表面110A平行的水平方向上与半导体芯片120分隔开，以具有面对半导体芯片120的一个侧表面的侧表面。根据示例性实施例，虚设芯片150可以以与半导体芯片120不同的方式利用粘合层152接合到中介件110的第一表面，使得粘合层152的上表面接触虚设芯片150的底表面150L(虚设芯片的面对中介件110的第一表面110A的表面)并且粘合层152的底表面接触中介件110的第一表面110A。根据示例性实施例，虚设芯片150的侧表面可以与粘合层152的侧表面处于同一平面(例如，这些侧表面可以竖直地对齐)。根据示例性实施例，虚设芯片150的底表面150L可以位于比半导体芯片120的底表面(这里，有效表面)低的水平处(水平指竖直水平，竖直指与中介件110的第一表面110A垂直的方向)。虚设芯片150的上表面150T(虚设芯片的背向中介件110的第一表面110A的主表面)可以位于比半导体芯片120的上表面(在本示例中，背侧、非有效表面)低的水平处(例如，相对于与中介件110的第一表面110A垂直的方向位于比半导体芯片120的上表面低的水平处)。可以使用非导电膜(NCF)、各向异性导电膜(ACF)、UV敏感膜、瞬时粘合剂、热固性粘合剂、激光可固化粘合剂、超声波固化粘合剂、非导电膏(NCP)等作为粘合层152。粘合层可以在整个虚设芯片150的下方(例如，当实施为膜时)以及/或者位于虚设芯片150下方的全部位置处具有均匀的厚度。粘合层可以由不同材料的多层形成或者可以是均质的。
虚设芯片150可以设置在中介件110的第一表面110A上，但位于未被半导体芯片120占据的空的区域中，使得虚设芯片150可以减小半导体封装件100A的弯曲。为了弯曲减小的效果，虚设芯片150可以包括具有相对低模量的材料。例如，虚设芯片150可以由具有比密封材料165的模量低的模量的材料构成。根据示例性实施例，当中介件的基体材料111由诸如硅的半导体材料构成时，虚设芯片150可以由与中介件的基底材料111的材料相同或相似的材料构成。
在本示例实施例中，虚设芯片150可以在与中介件110的第一表面110A垂直的方向上具有安装高度T2，所述安装高度T2低于半导体芯片120的在与中介件110的第一表面110A垂直的方向上的安装高度T1。类似地，虚设芯片150的上表面150T可以设置为在与中介件110的第一表面110A垂直的方向上比半导体芯片120的安装高度T1低。具有比半导体芯片120相对低的上表面150T的虚设芯片150可以抑制底填件161在空间S中的不期望的抬升。这将参照图1和图3进行详细描述。例如，图3是图1中示出的半导体封装件100A中的底填件161的延伸部分161B的放大剖视图。
这里描述的器件的各种垫(pad，或称为“焊盘”)可以是连接到器件的内部布线和/或逻辑电路的导电端子，并且可以在器件的内部布线和/或内部电路与外部源之间发送信号和/或提供电压。例如，设置在半导体芯片120的有效表面上的连接垫122可以电连接到半导体芯片120的集成电路与连接到半导体芯片120的器件之间，并且/或者可以在半导体芯片120的集成电路与连接到半导体芯片120的器件之间传输电源电压和/或信号。
参照图1和图3，底填件161可以填充半导体芯片120与中介件110的第一表面110A之间的空间，例如，使半导体芯片120的连接垫122与中介件110的第一垫112连接的连接端子116之间的空间。底填件161可以部分地从半导体芯片120延伸，并且沿着半导体芯片120的侧表面延伸。具体地，底填件161可以沿着在半导体芯片120和虚设芯片150的彼此面对的侧表面之间的空间S延伸。
类似地，在本示例实施例中采用的底填件161可以具有沿着半导体芯片120和虚设芯片150的彼此面对的侧表面延伸的部分161B(也可以称为延伸部分)，以及在半导体芯片120与中介件110的第一表面110A之间的主要部分161A。底填件的延伸部分161B和主要部分161A可以具有相同的材料构成。
底填件161的延伸部分161B可以在与中介件110的第一表面110A垂直的方向上设置得较低，使得延伸部分161B的上端部161T未到达半导体封装件100A的上表面100T，而是到达虚设芯片150的布置得比半导体芯片120的安装高度T1低的上表面150T。通常，尽管底填件161的延伸部分161B在形成底填件期间(例如，在固化之前)在狭窄的空间S之内升高，使得其上端部161T的位置由于毛细现象而形成得较高，但是根据本示例实施例，可以通过具有比半导体芯片120的上表面120T低的上表面150T的虚设芯片150来把延伸部分161B的上端部161T控制得更低。
类似地，可以通过虚设芯片150的相对低的上表面150T来把延伸部分161B的上端部161T控制成具有独特的轮廓。例如，如图3中所示，在延伸部分161B的上端部161T中，与虚设芯片150接触的点C2的水平可以比与半导体芯片120接触的点C1的水平低。例如，延伸部分161B可以包括第一侧表面161B1和第二侧表面161B2，所述第一侧表面161B1与半导体芯片120的侧表面接触，所述第二侧表面161B2与第一侧表面161B1背对并且与虚设芯片150的侧表面接触，其中，半导体芯片120的所述侧表面面对虚设芯片150的所述侧表面。根据示例性实施例，延伸部分161B的与半导体芯片120的所述侧表面接触的第一侧表面161B1的最上点(例如，点C1)可以在与中介件110的第一表面110A垂直的方向上布置得比延伸部分161B的与虚设芯片150的所述侧表面接触的第二侧表面161B2的最上点(例如，点C2)高。
尽管在延伸部分161B的上端部161T中与半导体芯片120接触的点C1的水平以其保持与虚设芯片150的上表面150T的水平基本相等的形式示出，但是本示例实施例中的延伸部分161B的上端部161T可以根据底填件161的量、空间S的形状等而具有不同的轮廓。除非上下文或其它陈述另外指出，否则可以在这里使用术语“基本上”来强调这个含义。例如，描述为“基本上相同”、“基本上相等”或“基本上平面的”的项可以完全相同、相等或平面的，或者可以在例如由于制造工艺而可能发生的可接受的变化之内是相同、相等或是平面的。
例如，当在相同结构的封装件中提供的底填件的量大于图3的量时，也会使大量的底填件被注入到半导体芯片120与虚设芯片150之间的空间S中。结果，如图4中所示，底填件161的延伸部分161B的上端部161T'会覆盖虚设芯片150的上表面150T的一部分。通过虚设芯片150的相对低的上表面150T可以使延伸部分161B的上端部161T的高度保持为低。
如上所述，底填件161的延伸部分161B可以具有各种形状。
底填件161可以具有比密封材料165的热膨胀系数高的热膨胀系数。在另一示例实施例中，底填件161可以具有比密封材料165的模量(或刚度)低的模量(或刚度)。
在这些条件下，底填件161的延伸部分161B会起到屈折点的作用，沿着半导体芯片120与虚设芯片150之间的边界会更严重地发生翘曲。另一方面，根据上述示例性实施例，通过将延伸部分161B的上端部161T保持在较低水平，可以减少由底填件161导致的翘曲问题。
底填件161可以包括诸如环氧树脂的底填树脂。在特定的示例实施例中，底填件161可以包括二氧化硅填料或焊剂。例如，密封材料165可以包括诸如环氧模塑料(EMC)的树脂。底填件161可以由与在外周处形成的密封材料165类似的材料来形成，但是它可以具有相对更高的流动性以有效地填充小空间。在本示例实施例中，底填件161的模量可以比密封材料165的模量低。在另一示例实施例中，底填件161的热膨胀系数可以比密封材料165的热膨胀系数高。
在特定的示例实施例中，当底填件161由与密封材料165相同或相似的树脂形成时，底填件161包含的填料的种类和量(例如，密度)相对少，因此，底填件161可以具有比密封材料165的模量低的模量。
如图1和图3中所示，由于将延伸部分161B的上端部161T保持为比半导体芯片120的上表面120T低，所以密封材料165可以覆盖底填件161的延伸部分161B。可以通过具有比底填件161的刚度高的刚度的密封材料165来减少在半导体芯片120与虚设芯片150之间的边界处发生的翘曲问题。
密封材料165可以设置在中介件110的第一表面110A上，并且可以设置为围绕半导体芯片120和虚设芯片150。如图1中所示，密封材料165可以形成为覆盖虚设芯片150的上表面150T的同时，具有与半导体芯片120的上表面120T基本共面的上表面。在用密封材料165覆盖半导体芯片120和虚设芯片150之后，通过研磨封装件的上区域以暴露半导体芯片120的上表面120T，可以获得半导体封装件100A的平坦的上表面100T。
图5是示出根据虚设芯片的安装高度改善翘曲的效果的曲线图。
参照图5，可以在逐渐改变虚设芯片的安装高度T2与半导体芯片的安装高度T1的比的同时测量翘曲的变化，以确认改善虚设芯片的安装高度T2的变化的效果。
在不存在虚设芯片(0％)的封装件中，翘曲会以120μm或更大的量存在。通过采用虚设芯片，改善了半导体封装件翘曲。随着虚设芯片的安装高度T2(例如，半导体封装件的厚度)增大，可以确保刚性，并且可以逐渐减小半导体封装件的翘曲(例如，小于100μm)。另一方面，当虚设芯片的安装高度T2增大时，会再次增大翘曲。当封装件中的虚设芯片的安装高度T2与半导体芯片的安装高度T1相同(100％)时，翘曲被示出为增大至110μm。
当虚设芯片的安装高度T2在半导体芯片的安装高度T1的60％至90％的范围内时，改善翘曲的效果可被清楚的示出为处于100μm或更小的水平。
如前述实施例中所述，通过将虚设芯片的安装高度T2降低至半导体芯片的安装高度T1的90％，可以预期足够的翘曲改善效果。另一方面，当虚设芯片的安装高度T2小于半导体芯片的安装高度T1的60％时，通过虚设芯片本身来改善翘曲的效果会减小，因此可能无法预期整体上的足够的翘曲改善效果。因此，虚设芯片的相对于半导体芯片的安装高度T1的安装高度T2可以在60％至90％的范围内，通过控制底填件的延伸部分以获得足够的翘曲改善效果。
图6是示出采用图1中示出的半导体封装件的模块的剖面侧视图。
参照图6，根据本示例实施例的半导体封装模块200A包括图1中示出的半导体封装件100A以及其上安装有该半导体封装件的封装基底210。半导体封装模块200A可以是完整的封装件，并且图1中示出的半导体封装件100A可以被认为是半导体封装模块200A的中间产物。
封装基底210可以包括：基体基底211；上表面垫212，设置在基体基底211的上表面上并连接到中介件110的第二垫；下表面垫213，设置在基体基底211的下表面上并具有形成在下表面垫213上的外部连接端子215，所述外部连接端子215用于将半导体封装模块200A连接到在半导体封装模块200A外部的器件；以及重新分布层(RDL，未示出)，连接在上表面垫212与下表面垫213之间。未在图中示出的重新分布层可被理解为由多个过孔和导电图案构成的布线电路。
上表面垫212可以形成为与中介件110的第二垫113的尺寸和布置对应，下表面垫213可以形成为使垫的尺寸和空间扩展以适应诸如主板的电路的I/O端子，并且这样的重新分布电路可以通过封装基底210的重新分布层来实现。用于连接到外部电路的诸如焊料凸起的外部连接端子215可以设置在下表面垫213上。例如，外部连接端子215可以包括锡(Sn)、铅(Pb)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)和铋(Bi)中的至少一种金属，或者它们的合金。
根据本示例实施例的半导体封装模块200A可以至少包括设置在半导体封装件100A的上表面上的散热部170。在本示例实施例中采用的散热部170可以包括以盖结构的形式延伸到半导体封装件100A的侧表面的形状。散热部170可以使用接合构件180来接合到半导体封装件100A的上表面100T。在本示例实施例中，在半导体芯片120中发生的热可以发散到与其相邻设置的散热部170。
例如，散热部170可以包括具有良好导热性的材料，诸如，金属或陶瓷。此外，散热部170可以是包括热界面材料(TIM)的结构。例如，NCF、ACF、UV敏感膜、瞬时粘合剂、热固性粘合剂、激光可固化粘合剂、超声波固化粘合剂、NCP等可以用作接合构件180。
图7是根据示例实施例的半导体封装件的平面图。图8至图10是图7中示出的半导体封装件的分别沿线X1-X1'、X2-X2'和Y-Y'截取的剖面侧视图。
参照图7和图8，可以理解的是，根据本示例实施例的半导体封装件100B可以包括第一半导体芯片120和多个第二半导体芯片130A、130B、130C和130D，并且除了采用两个虚设芯片150A和150B之外，与图1中示出的半导体封装件100A类似。除非另有说明，否则本示例实施例的组件的描述可以与图1至图4中示出的半导体封装件100A的相同或相似组件的描述相同。
根据本示例实施例的半导体封装件100B可以包括第一半导体芯片120以及设置在第一半导体芯片周围的四个第二半导体芯片130A、130B、130C和130D。如图7中所示，四个第二半导体芯片130A、130B、130C和130D可以分别设置在第一半导体芯片120的四角处。
与第一半导体芯片120类似，第二半导体芯片130A、130B、130C和130D可以通过连接端子116将各自的连接垫132接合到中介件110的第一垫112。
根据本示例实施例的半导体封装件100B可以包括在第一半导体芯片120的两侧处的两个虚设芯片150A和150B。例如，如图7中所示，虚设芯片150A和150B中的每个可以设置在中介件110的第一表面110A上，以在两个第二半导体芯片130A和130D之间或者在两个第二半导体芯片130B和130C之间与第一半导体芯片120的侧表面彼此面对。
第一半导体芯片120可以包括逻辑芯片。例如，第一半导体芯片120可以包括控制器或包括逻辑器件的微处理器。
第二半导体芯片可以包括存储器芯片，诸如，DRAM、SRAM、闪存、PRAM、ReRAM、FeRAM或MRAM。例如，第二半导体芯片(130A、130B、130C和130D)可以是包括以TSV结构连接的存储器堆叠件的高带存储器(HBD)芯片。
参照图8，底填件161可以填充第一半导体芯片120、第二半导体芯片130A、130B、130C和130D以及中介件110的第一表面110A之间的空间，并且可以部分地从第一半导体芯片120延伸且沿着第一半导体芯片120和虚设芯片150A和150B的彼此面对的侧表面延伸。例如，底填件161可以具有沿着第一半导体芯片120与虚设芯片150A和150B之间的空间S1和S2形成的延伸部分161B。
在本示例实施例中，虚设芯片150A和150B具有比第一半导体芯片120的安装高度低的安装高度。虚设芯片150A和150B的比第一半导体芯片120相对低的上表面150T可以抑制底填件161在空间S1和S2中的不期望的抬升。结果，如图8中所示，可以保持底填件161的延伸部分161B使得延伸部分161B的上端部161T比第一半导体芯片120的上表面120T低。
由于延伸部分161B的上端部161T由虚设芯片150的相对低的上表面150T来控制，如上所述，在延伸部分161B的上端部161T处与虚设芯片150接触的点的水平可以比与第一半导体芯片120接触的点的水平低(见图3和图4)。此外，在与本示例实施例不同的可选实施例中，底填件161的延伸部分161B可以部分地延伸到虚设芯片150的上表面150T(见图4)。
在本示例实施例中，第二半导体芯片130A至130D可以具有与第一半导体芯片120的安装高度基本相等的安装高度。如图9中所示，在设置在第一半导体芯片120和第二半导体芯片130A至130D之间的空间S1'和S2'中，延伸部分161B的上端部161T可以形成在与封装件的上表面接近的相对较高的水平处。然而，如上所述，由于底填件161的延伸部分161B可以在一些区域(例如，由S1和S2表示的区域)中形成在较低水平处，如图8中所示，可以有效地减小由底填件161导致的在沿着第一半导体芯片120的两侧的区域中发生的翘曲。
图10是图7中示出的半导体封装件的沿线Y-Y'截取的剖视图。
参照图10，虚设芯片150A可以具有比两个相邻的第二半导体芯片130A和130D的安装高度低的安装高度。虚设芯片150A的比第二半导体芯片130A和130D相对低的上表面150T可以抑制底填件161在空间S1中的不期望的抬升。结果，如图10中所示，可以保持底填件161的延伸部分161B使得底填件161的上端部161T比第二半导体芯片130A和130D的上表面130T低。
由于延伸部分161B的上端部161T可以由虚设芯片150的相对低的上表面150T来控制，如上所述，在延伸部分161B的上端部161T处与虚设芯片150接触的点的水平可以比与第二半导体芯片130A和130D接触的点的水平低。类似地，在另一虚设芯片150B(见图7)与相邻于虚设芯片150B的第二半导体芯片130B和130C之间的空间S4中，底填件161的延伸部分161B可以由虚设芯片150B的相对较低的上表面150T(未示出)来控制以改善翘曲。
密封材料165可以设置在中介件110的第一表面110A上，以提供围绕第一半导体芯片120和第二半导体芯片130A至130D以及虚设芯片150A和150B的结构。如图8至图10中所示，密封材料165可以形成为覆盖虚设芯片150A和150B的上表面150T，但是可以形成为具有与第一半导体芯片的上表面120T和第二半导体芯片的上表面130T基本共面的上表面。通过这种结构，热可以有效地从作为热源的第一半导体芯片和第二半导体芯片发射。
由于在第一半导体芯片120、第二半导体芯片130A至130D以及虚设芯片150A和150B之间的区域S1、S2、S3和S4中将延伸部分161B的上端部161T保持为低，所以密封材料165可以覆盖底填件161的延伸部分161B。因此，通过具有比底填件161高的刚度的密封材料165，可以显著减小在第一半导体芯片120、第二半导体芯片130A至130D以及虚设芯片150A和150B之间的区域S1、S2、S3和S4中发生的翘曲问题。
以类似的方式，通过降低与第一半导体芯片和/或第二半导体芯片相邻的虚设芯片的安装高度，可以极大地减轻因底填件的沿着相对侧表面的抬升而导致的变形。
图11是示出采用图8中示出的半导体封装件的模块的剖面侧视图。
参照图11，可以理解的是，除了采用图8中示出的半导体封装件100B之外，根据本示例实施例的半导体封装模块200B与图6中示出的半导体封装模块200A类似。除非另有说明，否则本示例实施例的组件的描述可以参照图6中示出的半导体封装模块200A的相同或相似组件的描述。
根据本示例实施例的半导体封装模块200B可以包括图8中示出的半导体封装件100B以及其上安装有该半导体封装件的封装基底210。封装基底210可以包括：基体基底211；上表面垫212，通过外部端子115连接到中介件110的第二垫113；下表面垫213；以及重新分布层(未示出)，连接上表面垫212和下表面垫213。
根据本示例实施例的半导体封装模块200B可以包括设置在半导体封装件100B的上表面和侧表面上的散热部170。由于第一半导体芯片120和第二半导体芯片130A至130D的上表面可以暴露在半导体封装件100B的上表面上，所以由第一半导体芯片120以及第二半导体芯片130A至130D发生的热可以有效地发射到相邻的散热部170。
根据通过底填件来控制翘曲问题的方案，当采用多个半导体芯片时，通过改变一些半导体芯片而不是虚设芯片的安装高度(例如，厚度)可以预期类似的效果。
图12是根据示例实施例的半导体封装件的平面图，图13是图12中示出的半导体封装件的沿线X-X'截取的剖面侧视图。
参照图12和图13，根据本示例实施例的半导体封装件100C可以不使用虚设芯片，并且除了第一半导体芯片120的厚度和第二半导体芯片130A至130D的厚度不同之外，半导体封装件100C可以与图7和图8中示出的半导体封装件100B类似。除非另有说明，否则本示例实施例的组件的描述将参照图1和图2中示出的半导体封装件100A以及图7和图8中示出的半导体封装件100B的相同或相似组件的解释。
第二半导体芯片130A至130D可以设置在第一半导体芯片120的四个角处。底填件161可以填充第一半导体芯片120、第二半导体芯片130A、130B、130C和130D以及中介件110的第一表面110A之间的空间，并且可以部分地从第一半导体芯片120延伸且沿着第一半导体芯片120与第二半导体芯片130A至130D的彼此面对的侧表面延伸。例如，底填件161可以具有沿着第一半导体芯片120与第二半导体芯片130A至130D之间的空间Sa和Sb形成的延伸部分161B。
在本示例实施例中采用的第二半导体芯片130A至130D可以具有比第一半导体芯片120的安装高度低的安装高度。第二半导体芯片130A至130D的比第一半导体芯片120相对低的上表面130T可以抑制底填件161在空间Sa和Sb中的不期望的抬升。结果，如图13中所示，可以将底填件161的延伸部分161B保持为延伸部分161B的上端部161T比第一半导体芯片120的上表面120T低。
以类似的方式，由于延伸部分161B的上端部161T由第二半导体芯片130A至130D的相对较低的上表面130T来控制，因此在延伸部分161B的上端部161T中，在与第二半导体芯片130A至130D接触的点处的水平可以比与第一半导体芯片120接触的点处的水平低(见图3和图4)。另外，在与本示例实施例不同的可选实施例中，底填件161的延伸部分161B可以部分地延伸到第二半导体芯片130A至130D的上表面130T(见图4)。
密封材料165可以设置在中介件110的第一表面110A上，以提供围绕第一半导体芯片120以及第二半导体芯片130A至130D的结构。如图13中所示，密封材料165可以在形成为具有与第一半导体芯片120的上表面120T基本共面的上表面的同时，形成为覆盖第二半导体芯片130A至130D的上表面130T。
可以在第一半导体芯片120以及第二半导体芯片130A至130D之间的区域Sa和Sb中将延伸部分161B的上端部161T保持为低，使得密封材料165可以覆盖底填件161的延伸部分161B。
以类似的方式，通过降低与第一半导体芯片相邻的第二半导体芯片的安装高度，可以极大地缓解因底填件的沿着相对侧表面的抬升而导致的变形。
图14是示出根据本公开的示例性实施例的制造将在半导体封装件100A中使用的半导体器件的方法的流程图。
在步骤S1401中，设置基底。基底可以是如上根据示例性实施例描述的中介件110。基底/中介件110可以具有第一表面110A和与第一表面背对的第二表面110B。
在步骤S1403中，在基底/中介件110的第一表面110A上形成多个第一垫112，并在基底/中介件110的第二表面110B上形成多个第二垫113。可以将多个第二垫113电连接到多个第一垫112。
在步骤S1405中，将半导体芯片附着到基底/中介件110的第一表面110A并且连接到多个第一垫112。半导体芯片可以是根据上面公开的示例性实施例的半导体芯片120。
在步骤S1407中，在与基底/中介件110的第一表面110A平行的方向上将虚设芯片附着到基底/中介件110的与半导体芯片120分隔开的第一表面110A。虚设芯片可以是根据上面公开的示例性实施例的虚设芯片150。虚设芯片150具有与半导体芯片120的一个侧表面面对的侧表面并且具有在与基底/中介件110的第一表面110A垂直的方向上布置得比半导体芯片120的上表面120T低的上表面150T。
在步骤S1409中，在半导体芯片120与基底/中介件110的第一表面之间形成底填件。底填件可以是根据上面公开的示例性实施例的底填件161。底填件161具有在与基底/中介件110的第一表面110A垂直的方向上沿着半导体芯片120和虚设芯片150的面对的侧表面延伸的延伸部分161B。延伸部分161B的上端部161T被设置为比半导体芯片120的上表面120T低。
在步骤S1411中，在基底/中介件110的第一表面110A上形成密封材料。密封材料可以是根据上面公开的示例性实施例的密封材料165。密封材料165将半导体芯片120和虚设芯片150密封。
根据上面公开的工艺制造的半导体器件可以被用在根据上面公开的示例性实施例的示例性半导体封装件100A、100B、100C、200A和200B中。
如上所述，根据示例实施例，通过降低与半导体芯片相邻的(一个或多个)虚设芯片或其它(一个或多个)半导体芯片的安装高度，半导体封装件可以显著减轻由沿着半导体芯片的侧表面抬升的底填件导致的来自翘曲的屈折。
尽管可以使用诸如“一个实施例”或“某些实施例”或“示例实施例”的措辞来引用这里描述的附图，但是除非上下文如此指明，否则这些附图和它们的相应描述并不旨在与其它附图或描述互斥。因此，特定附图中的特定方面可以与其它附图中的特定特征相同，以及/或者特定附图可以是特定示例性实施例的不同表示或不同部分。
虽然在上面已经示出和描述了示例实施例，但是对于本领域技术人员而言，将明显的是，在不脱离由所附权利要求限定的本发明构思的范围的情况下，可以进行修改和变化。

Claims (23)

1.一种半导体封装件，所述半导体封装件包括：
基底，具有第一表面和与所述第一表面背对的第二表面；
多个第一垫和多个第二垫，所述多个第一垫设置在所述基底的所述第一表面上，所述多个第二垫设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；
半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫；
虚设芯片，具有与所述半导体芯片的一个侧表面面对的侧表面，设置在所述基底的所述第一表面上并且在与所述基底的所述第一表面平行的方向上与所述半导体芯片分隔开，所述虚设芯片在与所述基底的所述第一表面垂直的方向上具有比所述半导体芯片的上表面低的上表面；
底填件，设置在所述半导体芯片与所述基底的所述第一表面之间，并且具有在与所述基底的所述第一表面垂直的所述方向上沿着所述半导体芯片和所述虚设芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述半导体芯片的所述上表面低；以及
密封材料，设置在所述基底的所述第一表面上，并且密封所述半导体芯片和所述虚设芯片。
2.如权利要求1所述的半导体封装件，其中，所述底填件具有比所述密封材料的模量低的模量。
3.如权利要求2所述的半导体封装件，其中，所述密封材料覆盖所述底填件的所述延伸部分。
4.如权利要求1所述的半导体封装件，其中，所述底填件的所述延伸部分与所述虚设芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平比所述底填件的所述延伸部分与所述半导体芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平低。
5.如权利要求4所述的半导体封装件，其中，所述底填件的所述延伸部分与所述虚设芯片接触的在与所述基底的所述第一表面垂直的所述方向上的所述最上点的所述水平等于所述虚设芯片的所述上表面在与所述基底的所述第一表面垂直的所述方向上的水平。
6.如权利要求1所述的半导体封装件，其中，所述底填件的所述延伸部分的所述上端部进一步延伸以覆盖所述虚设芯片的所述上表面的至少一部分。
7.如权利要求1所述的半导体封装件，其中，所述密封材料覆盖所述虚设芯片的所述上表面，并且具有与所述半导体芯片的所述上表面共面的上表面。
8.如权利要求1所述的半导体封装件，其中，所述虚设芯片的在与所述基底的所述第一表面垂直的所述方向上的安装高度为所述半导体芯片的在与所述基底的所述第一表面垂直的所述方向上的安装高度的60％至90％。
9.一种半导体封装件，所述半导体封装件包括：
基底，具有第一表面和与所述第一表面背对的第二表面；
多个第一垫和多个第二垫，所述多个第一垫设置在所述基底的所述第一表面上，所述多个第二垫设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；
第一半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫的第一部分；
第二半导体芯片，设置在所述基底的所述第一表面上并且在与所述基底的所述第一表面平行的方向上与所述第一半导体芯片分隔开，并且连接到所述多个第一垫的第二部分，所述多个第一垫的所述第二部分与所述多个第一垫的所述第一部分不同；
虚设芯片，设置在所述基底的所述第一表面上以至少具有与所述第一半导体芯片的一个侧表面面对的侧表面，并且具有在与所述基底的所述第一表面垂直的方向上比所述第一半导体芯片的上表面低的上表面；
底填件，设置在所述第一半导体芯片、所述第二半导体芯片与所述基底的所述第一表面之间，并且具有在与所述基底的所述第一表面垂直的所述方向上沿着所述第一半导体芯片和所述虚设芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述第一半导体芯片的所述上表面低；以及
密封材料，设置在所述基底的所述第一表面上，并且密封所述第一半导体芯片、所述第二半导体芯片和所述虚设芯片。
10.如权利要求9所述的半导体封装件，其中，所述第二半导体芯片包括与所述第一半导体芯片的所述一个侧表面相邻设置的多个第二半导体芯片，并且所述虚设芯片设置在所述多个第二半导体芯片之间。
11.如权利要求9所述的半导体封装件，其中，所述底填件具有比所述密封材料的热膨胀系数高的热膨胀系数，并且所述密封材料覆盖所述底填件的所述延伸部分。
12.如权利要求9所述的半导体封装件，其中，所述底填件的所述延伸部分与所述虚设芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平比所述底填件的所述延伸部分与所述第一半导体芯片和所述第二半导体芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平低，所述底填件的所述延伸部分与所述虚设芯片接触的在与所述基底的所述第一表面垂直的所述方向上的所述最上点的所述水平等于所述虚设芯片的所述上表面的在与所述基底的所述第一表面垂直的所述方向上的水平。
13.如权利要求9所述的半导体封装件，其中，所述底填件的所述延伸部分的所述上端部覆盖所述虚设芯片的所述上表面的至少一部分。
14.如权利要求9所述的半导体封装件，其中，所述第一半导体芯片和所述第二半导体芯片在与所述基底的所述第一表面垂直的所述方向上具有相同的安装高度，所述虚设芯片在与所述基底的所述第一表面垂直的所述方向上的安装高度为所述第一半导体芯片和所述第二半导体芯片的所述安装高度的60％至90％。
15.如权利要求9所述的半导体封装件，其中，所述密封材料覆盖所述虚设芯片的所述上表面，并且具有与所述第一半导体芯片的所述上表面和所述第二半导体芯片的上表面共面的上表面。
16.如权利要求9所述的半导体封装件，所述半导体封装件还包括设置在所述半导体封装件的上表面上的散热部。
17.如权利要求9所述的半导体封装件，所述半导体封装件还包括：具有第一表面和第二表面的封装基底，所述封装基底的所述第一表面面对所述基底的所述第二表面，所述封装基底的所述第二表面与所述封装基底的所述第一表面背对并且背离所述基底的所述第二表面，所述封装基底包括：
上表面垫，设置在所述封装基底的所述第一表面上并且连接到所述基底的所述多个第二垫；
下表面垫，设置在所述封装基底的所述第二表面上；以及
重新分布层，连接所述上表面垫和所述下表面垫。
18.如权利要求9所述的半导体封装件，其中，所述第一半导体芯片包括逻辑芯片，所述第二半导体芯片包括存储器芯片。
19.一种半导体封装件，所述半导体封装件包括：
基底，具有第一表面和与所述第一表面背对的第二表面；
多个第一垫和多个第二垫，所述多个第一垫设置在所述基底的所述第一表面上，所述多个第二垫设置在所述基底的所述第二表面上并且电连接到所述多个第一垫；
第一半导体芯片，设置在所述基底的所述第一表面上并且连接到所述多个第一垫的第一部分；
第二半导体芯片，具有面对所述第一半导体芯片的一个侧表面的侧表面，设置在所述基底的所述第一表面上，并且在与所述基底的所述第一表面垂直的方向上具有安装高度，所述安装高度比所述第一半导体芯片的在与所述基底的所述第一表面垂直的所述方向上的安装高度低；
底填件，设置在所述第一半导体芯片、所述第二半导体芯片与所述基底的所述第一表面之间，并且具有在与所述基底的所述第一表面垂直的所述方向上沿着所述第一半导体芯片和所述第二半导体芯片的彼此面对的侧表面延伸的延伸部分，所述延伸部分的上端部设置为比所述第一半导体芯片的所述安装高度低；以及
密封材料，设置在所述基底的所述第一表面上，以在覆盖所述底填件的所述延伸部分的同时密封所述第一半导体芯片和所述第二半导体芯片，所述密封材料的热膨胀系数比所述底填件的热膨胀系数低。
20.如权利要求19所述的半导体封装件，其中，所述底填件的所述延伸部分与所述第二半导体芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平比所述底填件的所述延伸部分与所述第一半导体芯片接触的在与所述基底的所述第一表面垂直的所述方向上的最上点的水平低，所述底填件的所述延伸部分与所述第二半导体芯片接触的在与所述基底的所述第一表面垂直的所述方向上的所述最上点的所述水平等于所述第二半导体芯片的所述上表面的在与所述基底的所述第一表面垂直的所述方向上的水平。
21.如权利要求19所述的半导体封装件，其中，所述底填件的所述延伸部分的所述上端部覆盖所述第二半导体芯片的所述上表面的至少一部分。
22.如权利要求19所述的半导体封装件，其中，所述第二半导体芯片的在与所述基底的所述第一表面垂直的所述方向上的安装高度为所述第一半导体芯片的在与所述基底的所述第一表面垂直的所述方向上的所述安装高度的60％至90％。
23.如权利要求19所述的半导体封装件，其中，所述密封材料覆盖所述第二半导体芯片的上表面，并且具有与所述第一半导体芯片的上表面共面的上表面。
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