CN110096465A - The method and system of compatible DMX512 and scan protocols in intelligent illuminating system - Google Patents
The method and system of compatible DMX512 and scan protocols in intelligent illuminating system Download PDFInfo
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- CN110096465A CN110096465A CN201910209452.3A CN201910209452A CN110096465A CN 110096465 A CN110096465 A CN 110096465A CN 201910209452 A CN201910209452 A CN 201910209452A CN 110096465 A CN110096465 A CN 110096465A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses the intelligent illuminating systems of a kind of compatible DMX512 and scan protocols, including host computer, slave computer and LED to show dot matrix；Host computer is connect by communication interface with slave computer, controls the display that LED shows dot matrix by slave computer；Slave computer includes ARM microprocessor, FPGA, wherein ARM microprocessor exterior arrangement FLASH memory and jumper cap, the jumper cap two sides set-up mode is different, if wherein side is connected to jumper cap with ARM microprocessor, then ARM microprocessor selection is worked with the signal control protocol of daisy chain, if the jumper cap other side is connected to ARM microprocessor, the internal control protocol selection clock signal of ARM microprocessor carrys out recursion serial signal.The present invention can realize the compatibility of DMX512 and scan protocols in intelligent illuminating system.
Description
Technical field
The present invention relates to DMX512 compatible in intelligent illuminating system field more particularly to a kind of intelligent illuminating system and sweep
The method for retouching agreement.
Background technique
Two kinds of control protocols are mainly presented in current outdoor scene brightening, and one is assist derived from American Stage signal light control
The control program of 512 agreement of DMX derived from discussing, one is the scanning TTL agreements based on current display control agreement.DMX512
It is the derivative based on RS485, is a kind of lamp dimmer and lamp that American Stage light association (USITT) issues in nineteen ninety
The standard that tool equipment carries out data transmission.The scan protocols of display screen are a kind of high speeds, full duplex, synchronous communication bus,
And four lines, MOSI, MISO, SCLK, CS are only taken up on the pin of chip.In combination with the digit of scanning, also need to extend
1-6.
It cannot achieve the compatibility of two kinds of agreements in the prior art.
Summary of the invention
The technical problem to be solved in the present invention is that for the compatibility DMX512 of intelligent illuminating system in the prior art and sweeping
The defect that agreement can not be compatible with is retouched, a kind of method that two kinds of protocol-compliants may be implemented is provided.
The technical solution adopted by the present invention to solve the technical problems is:
The intelligent illuminating system of a kind of compatible DMX512 and scan protocols are provided, including host computer, slave computer and LED are shown
Show dot matrix；Host computer is connect by communication interface with slave computer, controls the display that LED shows dot matrix by slave computer；
Slave computer includes ARM microprocessor, FPGA, wherein ARM microprocessor exterior arrangement FLASH memory and wire jumper
Cap, the jumper cap two sides set-up mode is different, if wherein side is connected to jumper cap with ARM microprocessor, ARM microprocessor choosing
Select the signal control protocol work with daisy chain, if the jumper cap other side is connected to ARM microprocessor, ARM microprocessor
Internal control protocol selection clock signal carrys out recursion serial signal；
ARM microprocessor for obtaining external command from host computer by communication interface, and reads FLASH memory
Interior data；ARM microprocessor analysis peripheral data simultaneously determines which kind of control protocol taken, then will include prescribed control protocol
Instruction passes to FPGA；
FPGA, for generating screen display control letter according to specified control protocol after the instruction for receiving ARM transmission
Number, including decoding adaptation signal and pixel drive signal, and be sent to LED and show dot matrix；
LED shows dot matrix, receives the screen display control signal that FPGA is sent, and shown at the control.
Above-mentioned technical proposal is connect, ARM microprocessor reads the allocation plan in external FLASH memory by ARM bus,
It is carried out and goes here and there conversion operation, is stored in FLASH memory.
Above-mentioned technical proposal is connect, ARM microprocessor is also used to simulate the FPGA of TAP controller in reconfigurable controller, from
Configuration file is read in FLASH memory built in ARM, and the instruction for executing arm processor sending interprets the configuration file.
Above-mentioned technical proposal is connect, reconfigurable controller explains that binary file process is as follows:
Under the control of arm processor, a byte is read from the FLASH of load configurations file, which item judgement is
Then jtag instruction makees specific processing according to the format of instruction, generates TCK, TMS, TDI and TDO signal, can as target
The jtag interface of programming device motivates, and daisy chain is connected into the JTAG mouth of target FPGA programming device, in ARM microprocessor
Under control, in-system programming is carried out to target pro-grammable device.
Connect above-mentioned technical proposal, the memory of ARM microprocessor exterior arrangement large capacity.
Above-mentioned technical proposal is connect, the outside of FPGA is equipped with memory, and reading for timesharing includes gray scale, the data of brightness.
The present invention also provides a kind of compatibilities of intelligent illuminating system based on above-mentioned compatible DMX512 and scan protocols
Method, comprising the following steps:
ARM microprocessor by communication interface, simultaneously sentence according to the data obtained from jumper cap by the acquisition instruction collection from host computer
It is disconnected which kind of control protocol taken, then the instruction comprising prescribed control protocol is passed into FPGA；
FPGA generates screen display control signal after the instruction for receiving ARM transmission, according to specified control protocol, including
Adaptation signal and pixel drive signal are decoded, and is sent to LED and shows dot matrix；
LED shows that dot matrix is shown under the control of screen display control signal.
Above-mentioned technical proposal is connect, this method further comprises the steps of:
ARM microprocessor reads the allocation plan in external FLASH memory by ARM bus, carries out and go here and there to turn to it
Change operation, is stored in FLASH memory.
Above-mentioned technical proposal is connect, this method further comprises the steps of:
The FPGA that TAP controller is simulated in ARM microprocessor reconfigurable controller, from the FLASH memory built in ARM
Configuration file is read, and the instruction for executing arm processor sending interprets the configuration file.
Above-mentioned technical proposal is connect, reconfigurable controller explains that binary file process is as follows:
Under the control of arm processor, a byte is read from the FLASH of load configurations file, which item judgement is
Then jtag instruction makees specific processing according to the format of instruction, generates TCK, TMS, TDI and TDO signal, can as target
The jtag interface of programming device motivates, and daisy chain is connected into the JTAG mouth of target FPGA programming device, in ARM microprocessor
Under control, in-system programming is carried out to target pro-grammable device.
The beneficial effect comprise that: the present invention is by the external connection jumper cap in ARM microcontroller, according to wire jumper
The difference of cap connection type selects different control protocols, to realize the compatibility of DMX512 and scan protocols.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples, in attached drawing:
Fig. 1 is the structural schematic diagram of the intelligent illuminating system of the compatible DMX512 of the embodiment of the present invention and scan protocols；
Fig. 2 is the primary structure schematic diagram of slave computer of the embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
The present invention is by the external connection jumper cap in ARM microcontroller, not according to the different selections of jumper cap connection type
Same control protocol, to realize the compatibility of DMX512 and scan protocols.
The intelligent illuminating system of compatible DMX512 and scan protocols of the embodiment of the present invention, including host computer, slave computer and
LED shows dot matrix；Host computer is connect by communication interface with slave computer, controls the display that LED shows dot matrix by slave computer；
Slave computer includes ARM microprocessor, FPGA, wherein ARM microprocessor exterior arrangement FLASH memory and wire jumper
Cap, the jumper cap two sides set-up mode is different, if wherein side is connected to jumper cap with ARM microprocessor, ARM microprocessor choosing
Select the signal control protocol work with daisy chain, if the jumper cap other side is connected to ARM microprocessor, ARM microprocessor
Internal control protocol selection clock signal carrys out recursion serial signal；
ARM microprocessor for obtaining external command from host computer by communication interface, and reads FLASH memory
Interior data；ARM microprocessor analysis peripheral data simultaneously determines which kind of control protocol taken, then will include prescribed control protocol
Instruction passes to FPGA；
FPGA, for generating screen display control letter according to specified control protocol after the instruction for receiving ARM transmission
Number, including decoding adaptation signal and pixel drive signal, and be sent to LED and show dot matrix；
LED shows dot matrix, receives the screen display control signal that FPGA is sent, and shown at the control.
Further, ARM microprocessor reads the allocation plan in external FLASH memory by ARM bus, to its into
It goes and goes here and there conversion operation, be stored in FLASH memory.
Further, ARM microprocessor is also used to simulate the FPGA of TAP controller in reconfigurable controller, from built in ARM
FLASH memory in read configuration file, and execute arm processor sending instruction interpret the configuration file.
Wherein, reconfigurable controller explains that binary file process is as follows:
Under the control of arm processor, a byte is read from the FLASH of load configurations file, which item judgement is
Then jtag instruction makees specific processing according to the format of instruction, generates TCK, TMS, TDI and TDO signal, can as target
The jtag interface of programming device motivates, and daisy chain is connected into the JTAG mouth of target FPGA programming device, in ARM microprocessor
Under control, in-system programming is carried out to target pro-grammable device.
It can also be in the memory of ARM microprocessor exterior arrangement large capacity.The outside of FPGA is equipped with memory, reads for timesharing
It takes comprising gray scale, the data of brightness.
The present invention also provides a kind of compatibilities of intelligent illuminating system based on above-mentioned compatible DMX512 and scan protocols
Method, comprising the following steps:
ARM microprocessor by communication interface, simultaneously sentence according to the data obtained from jumper cap by the acquisition instruction collection from host computer
It is disconnected which kind of control protocol taken, then the instruction comprising prescribed control protocol is passed into FPGA；
FPGA generates screen display control signal after the instruction for receiving ARM transmission, according to specified control protocol, including
Adaptation signal and pixel drive signal are decoded, and is sent to LED and shows dot matrix；
LED shows that dot matrix is shown under the control of screen display control signal.
Above-mentioned technical proposal is connect, this method further comprises the steps of:
ARM microprocessor reads the allocation plan in external FLASH memory by ARM bus, carries out and go here and there to turn to it
Change operation, is stored in FLASH memory.
The FPGA that TAP controller is simulated in ARM microprocessor reconfigurable controller, from the FLASH memory built in ARM
Configuration file is read, and the instruction for executing arm processor sending interprets the configuration file.
In a specific embodiment of the invention, using ARM and FPGA reconfigurable processor, it is defeated to select that mouth is selected by wire jumper
Enter the protocol integrated test system of output.Two kinds of definition have been carried out to protocol interface on the coding inside the design of circuit and FPGA: 1, having been propped up
Hold the differential signal parallel interface of daisy chain structure；2, by clock signal come the serial signal of recursion.The inside of two kinds of signals
Selection, selection is provided with a 3 needle jumper cap and to select from outside in the embodiment of the present invention.Jumper cap is shorted two needle of the left side,
Processor selects work with the signaling protocol of daisy chain, and the internal agreement of jumper cap selection the right processor selects clock signal
Carry out the serial signal of recursion.The conversion of multi-protocols is realized by the selection of jumper cap.ARM has stronger transaction management function
Can, it can be used to run interface and application program etc., advantage is mainly reflected in control aspect.FPGA can with VHDL or
VerilogHDL is programmed, strong flexibility, due to be able to carry out programming, except it is wrong, reprogram and repetitive operation, can be abundant
Ground is designed exploitation and verifying.When circuit has a small amount of change, the advantage of FPGA can be more shown.In addition, due to FPGA sheet
Body is exactly a powerful gate array, and in the presence of having a large amount of logical operation in our design, the arithmetic speed of FPGA is excellent
Gesture is more obvious.
General whole system is mainly by host computer, and slave computer, communication system, controller, lattice module etc., system diagram is such as
Under:
Host computer is generally exactly traditional PC system or the embedded host based on liunx.It is mainly used for host computer tune
Examination, plays importing of source file etc..
Core controller and controller and the next machine controller that we are arranged, double agreements be mainly the ARM passed through and
The cooperative cooperating of FPGA, the calculating core of formation pass through the cooperation of program code and external jumper cap inside processor.It is logical
Communication interface is to read external command, and storage program data and protocol code inside memory, arm read sudden strain of a muscle after receiving external command
Interior data are deposited, analysis peripheral data is to need which kind of control protocol taken, and after being analyzed to identify, instruction is passed to FPGA, right
Its input and output are encoded, to export corresponding protocol instructions.Main system diagram is as shown in Figure 2.
In Fig. 2, the ARM bus that arm processor on the one hand passes through reads the protocol code of the storage in external FLASH: parallel
Daisy chain structure and serial TTL structure, it is carried out and goes here and there conversion operation, is stored in FLASH memory；It is another
The FPGA that TAP controller is simulated in aspect ARM controller, reads configuration file, and hold from the FLASH memory built in ARM
The instruction that row arm processor issues interprets this document, and reconfigurable controller explains that binary file method is as follows: in arm processor
Control under, a byte is read from the FLASH of load configurations file, judgement is the instruction of which item, then according to the association of instruction
It discusses format (serial signal of differential parallel daisy chain agreement or clock recursion) and makees specific processing, generate TCK, TMS, TDI
And TDO signal, the programming interface as target pro-grammable device are motivated, are connected into the programming interface of target FPGA programming device
Daisy chain carries out in-system programming to target pro-grammable device under the control of arm processor.
The pith of display control circuit system, mainly by input interface circuit, data conversion and signal control circuit,
Signal decoded output driving circuit composition.When display pixel dot matrix is more, the data for needing processing core to handle are more, data
Transmitting also will increase with the time of control, and the time for completing the time of a screen turntable driving or the data packet of transmission can be longer.
Therefore, we have selected the ARM and programmable logic array FPGA of high speed in this processor.
Instruction set is sent to ARM microprocessor, ARM micro process by communication interface (serial ports or RJ45) by host computer
Device is put into the instruction set received in external FLASH and saves, and content is not lost after power-off, while extension storage outside ARM
For storing the data of rapid computations, so that processor calls in time.FPGA completes to export hardware after receiving ARM instruction
Decoding adaptation, complete to pixel driver process, the Digital Logic of internal curing be responsible for generate screen display control signal,
The storage of exterior arrangement reads gray scale, the data such as brightness for timesharing.Meanwhile FPGA read grey from external storage it is believed that
Number, and be converted be decoded into screen data after on Serial output to the signal data bus of corresponding color.Expand outside FPGA
The storing data of exhibition constitutes data buffering, switch area, and using sequential logic, data are written to a piece of memory in a certain moment,
Another data conversion is read by fpga logic after be sent into display screen, the two switches in turn, ensure that in the high speed of data screen and
The continuity of display.The storage of ARM exterior arrangement large capacity and flash memory can support bigger display area, storage
More display contents obtain better display effect.
It should be understood that for those of ordinary skills, it can be modified or changed according to the above description,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (10)
1. a kind of intelligent illuminating system of compatible DMX512 and scan protocols, which is characterized in that including host computer, slave computer and
LED shows dot matrix；Host computer is connect by communication interface with slave computer, controls the display that LED shows dot matrix by slave computer；
Slave computer includes ARM microprocessor, FPGA, and wherein ARM microprocessor exterior arrangement FLASH memory and jumper cap, are somebody's turn to do
Jumper cap two sides set-up modes is different, if wherein side is connected to jumper cap with ARM microprocessor, ARM microprocessor select with
The signal control protocol of daisy chain works, if the jumper cap other side is connected to ARM microprocessor, the inside of ARM microprocessor
Control protocol selection clock signal carrys out recursion serial signal；
ARM microprocessor for obtaining external command from host computer by communication interface, and is read in FLASH memory
Data；ARM microprocessor analysis peripheral data simultaneously determines to take which kind of control protocol, then by the instruction comprising prescribed control protocol
Pass to FPGA；
FPGA, for generating screen display control signal, packet according to specified control protocol after the instruction for receiving ARM transmission
Decoding adaptation signal and pixel drive signal are included, and is sent to LED and shows dot matrix；
LED shows dot matrix, receives the screen display control signal that FPGA is sent, and shown at the control.
2. the intelligent illuminating system of compatible DMX512 and scan protocols according to claim 1, which is characterized in that ARM
Microprocessor reads the allocation plan in external FLASH memory by ARM bus, carries out to it and goes here and there conversion operation, by it
It stores in FLASH memory.
3. the intelligent illuminating system of compatible DMX512 and scan protocols according to claim 1, which is characterized in that ARM
Microprocessor is also used to simulate the FPGA of TAP controller in reconfigurable controller, reads and matches from the FLASH memory built in ARM
File is set, and the instruction for executing arm processor sending interprets the configuration file.
4. the intelligent illuminating system of compatible DMX512 and scan protocols according to claim 3, which is characterized in that reconstruct
Controller explains that binary file process is as follows:
Under the control of arm processor, a byte is read from the FLASH of load configurations file, judgement is which JTAG refers to
It enables, specific processing is then made according to the format of instruction, TCK, TMS, TDI and TDO signal are generated, as target pro-grammable device
Jtag interface excitation, be connected into daisy chain with the JTAG mouth of target FPGA programming device, under the control of ARM microprocessor,
In-system programming is carried out to target pro-grammable device.
5. the intelligent illuminating system of compatible DMX512 and scan protocols according to claim 1, which is characterized in that ARM
The memory of microprocessor exterior arrangement large capacity.
6. the intelligent illuminating system of compatible DMX512 and scan protocols according to claim 1, which is characterized in that FPGA
Outside be equipped with memory, for timesharing read include gray scale, the data of brightness.
7. a kind of compatibility method of the intelligent illuminating system of compatible DMX512 and scan protocols based on claim 1, special
Sign is, comprising the following steps:
ARM microprocessor is adopted by the communication interface data judgement that acquisition instruction collection and basis are obtained from jumper cap from host computer
Which kind of control protocol is taken, then the instruction comprising prescribed control protocol is passed into FPGA；
FPGA generates screen display control signal, including decoding after the instruction for receiving ARM transmission, according to specified control protocol
Adaptation signal and pixel drive signal, and be sent to LED and show dot matrix；
LED shows that dot matrix is shown under the control of screen display control signal.
8. the method according to the description of claim 7 is characterized in that this method further comprises the steps of:
ARM microprocessor reads the allocation plan in external FLASH memory by ARM bus, carries out and go here and there to convert behaviour to it
Make, is stored in FLASH memory.
9. the method according to the description of claim 7 is characterized in that this method further comprises the steps of:
The FPGA that TAP controller is simulated in ARM microprocessor reconfigurable controller, reads from the FLASH memory built in ARM and matches
File is set, and the instruction for executing arm processor sending interprets the configuration file.
10. according to the method described in claim 9, it is characterized in that, reconfigurable controller explains that binary file process is as follows:
Under the control of arm processor, a byte is read from the FLASH of load configurations file, judgement is which JTAG refers to
It enables, specific processing is then made according to the format of instruction, TCK, TMS, TDI and TDO signal are generated, as target pro-grammable device
Jtag interface excitation, be connected into daisy chain with the JTAG mouth of target FPGA programming device, under the control of ARM microprocessor,
In-system programming is carried out to target pro-grammable device.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060082331A1 (en) * | 2004-09-29 | 2006-04-20 | Tir Systems Ltd. | System and method for controlling luminaires |
| CN102892235A (en) * | 2012-10-09 | 2013-01-23 | 深圳市凯铭电气照明有限公司 | Illumination control system compatible with double protocols and control method adopting DMN (Default Mode Network) protocol |
| CN102905433A (en) * | 2012-10-16 | 2013-01-30 | 常州市城市照明工程有限公司 | Multi-compatible LED (Light Emitting Diode) lighting control system |
-
2019
- 2019-03-19 CN CN201910209452.3A patent/CN110096465B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060082331A1 (en) * | 2004-09-29 | 2006-04-20 | Tir Systems Ltd. | System and method for controlling luminaires |
| CN102892235A (en) * | 2012-10-09 | 2013-01-23 | 深圳市凯铭电气照明有限公司 | Illumination control system compatible with double protocols and control method adopting DMN (Default Mode Network) protocol |
| CN102905433A (en) * | 2012-10-16 | 2013-01-30 | 常州市城市照明工程有限公司 | Multi-compatible LED (Light Emitting Diode) lighting control system |
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