CN110096465B - Method and system for realizing compatibility of DMX512 and scanning protocol in intelligent lighting system - Google Patents
Method and system for realizing compatibility of DMX512 and scanning protocol in intelligent lighting system Download PDFInfo
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- CN110096465B CN110096465B CN201910209452.3A CN201910209452A CN110096465B CN 110096465 B CN110096465 B CN 110096465B CN 201910209452 A CN201910209452 A CN 201910209452A CN 110096465 B CN110096465 B CN 110096465B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses an intelligent lighting system compatible with DMX512 and a scanning protocol, which comprises an upper computer, a lower computer and an LED display dot matrix, wherein the upper computer is connected with the lower computer; the upper computer is connected with the lower computer through a communication interface, and the lower computer is used for controlling the display of the LED display dot matrix; the lower computer comprises an ARM microprocessor and an FPGA (field programmable gate array), wherein a FLASH memory and a jumper cap are configured outside the ARM microprocessor, the two sides of the jumper cap are arranged in different modes, if one side of the jumper cap is communicated with the ARM microprocessor, the ARM microprocessor selects a signal control protocol of a daisy chain to work, and if the other side of the jumper cap is communicated with the ARM microprocessor, a clock signal is selected by an internal control protocol of the ARM microprocessor to recur serial signals. The invention can realize the compatibility of the DMX512 and the scanning protocol in the intelligent lighting system.
Description
Technical Field
The invention relates to the field of intelligent lighting systems, in particular to a method for enabling a DMX512 and a scanning protocol to be compatible in an intelligent lighting system.
Background
At present, two control protocols are mainly presented for outdoor landscape brightening, one is a control scheme derived from a DMX512 protocol derived from a stage lighting control protocol in the United states, and the other is a scanning TTL protocol based on a current display control protocol. DMX512 is a derivative based on RS485, and is a standard for transmitting data between a light controller and a luminaire device, which is published by the united states stage light association (USITT) in 1990. The scanning protocol of the display screen is a high-speed, full-duplex and synchronous communication bus, and only four wires, MOSI, MISO, SCLK and CS, are occupied on the pins of the chip. Meanwhile, the number of scanned bits is combined, and 1-6 bits are required to be expanded.
In the prior art, the compatibility of two protocols cannot be realized.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for realizing compatibility of two protocols, aiming at the defect that the compatibility of the DMX512 and the scanning protocol of the intelligent lighting system in the prior art cannot be compatible.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the provided intelligent lighting system compatible with the DMX512 and the scanning protocol comprises an upper computer, a lower computer and an LED display dot matrix; the upper computer is connected with the lower computer through a communication interface, and the lower computer is used for controlling the display of the LED display dot matrix;
the lower computer comprises an ARM microprocessor and an FPGA (field programmable gate array), wherein a FLASH memory and a jumper cap are configured outside the ARM microprocessor, the two sides of the jumper cap are arranged in different modes, if one side of the jumper cap is communicated with the ARM microprocessor, the ARM microprocessor selects to work in a daisy chain signal control protocol, and if the other side of the jumper cap is communicated with the ARM microprocessor, the internal control protocol of the ARM microprocessor selects a clock signal to recur serial signals;
the ARM microprocessor is used for acquiring an external instruction from the upper computer through the communication interface and reading data in the FLASH memory; the ARM microprocessor analyzes the peripheral data, judges which control protocol is adopted, and transmits an instruction containing a specified control protocol to the FPGA;
the FPGA is used for generating a screen display control signal according to a specified control protocol after receiving an instruction sent by the ARM, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal and is sent to the LED display dot matrix;
and the LED display dot matrix receives the screen display control signal sent by the FPGA and displays the screen display control signal under the control of the FPGA.
And reading the configuration scheme in the external FLASH memory by the ARM microprocessor through the ARM bus, performing parallel-serial conversion operation on the configuration scheme, and storing the configuration scheme in the FLASH memory.
In connection with the above technical solution, the ARM microprocessor is further configured to reconstruct an FPGA of the simulated TAP controller in the controller, read the configuration file from a FLASH memory built in the ARM, and execute an instruction sent by the ARM processor to interpret the configuration file.
In connection with the above technical solution, the process of interpreting the binary file by the reconfiguration controller is as follows:
under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which JTAG instruction is, then carrying out specific processing according to the format of the instruction, generating TCK, TMS, TDI and TDO signals which are taken as JTAG interface excitation of a target programmable device and are connected in series with a JTAG port of the target FPGA programming device to form a daisy chain, and carrying out system programming on the target programmable device under the control of an ARM microprocessor.
According to the technical scheme, the ARM microprocessor is externally provided with a large-capacity memory.
According to the technical scheme, a memory is arranged outside the FPGA and used for time-sharing reading of data containing gray scales and brightness.
The invention also provides a compatible method of the intelligent lighting system based on the compatible DMX512 and scanning protocol, which comprises the following steps:
the ARM microprocessor acquires an instruction set from an upper computer through a communication interface, judges which control protocol is adopted according to data acquired from the jumper cap, and transmits an instruction containing a specified control protocol to the FPGA;
after receiving the instruction sent by the ARM, the FPGA generates a screen display control signal according to a specified control protocol, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal, and the screen display control signal is sent to the LED display dot matrix;
the LED display dot matrix is displayed under the control of the screen display control signal.
In connection with the above technical solution, the method further comprises the steps of:
and the ARM microprocessor reads the configuration scheme in the external FLASH memory through an ARM bus, performs parallel-serial conversion operation on the configuration scheme, and stores the configuration scheme into the FLASH memory.
In connection with the above technical solution, the method further comprises the steps of:
the ARM microprocessor reconstructs an FPGA simulating a TAP controller in the controller, reads a configuration file from a FLASH memory built in the ARM, and executes an instruction sent by the ARM processor to interpret the configuration file.
According to the technical scheme, the process of interpreting the binary file by the reconstruction controller is as follows:
under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which JTAG instruction is, then carrying out specific processing according to the format of the instruction, generating TCK, TMS, TDI and TDO signals which are taken as JTAG interface excitation of a target programmable device and are connected in series with a JTAG port of the target FPGA programming device to form a daisy chain, and carrying out system programming on the target programmable device under the control of an ARM microprocessor.
The invention has the following beneficial effects: according to the invention, the jumper cap is connected outside the ARM microcontroller, and different control protocols are selected according to different connection modes of the jumper cap, so that the compatibility of the DMX512 and the scanning protocol is realized.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
fig. 1 is a schematic structural diagram of an intelligent lighting system compatible with DMX512 and a scanning protocol according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a main structure of a lower computer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
According to the invention, the jumper cap is connected outside the ARM microcontroller, and different control protocols are selected according to different connection modes of the jumper cap, so that the compatibility of the DMX512 and the scanning protocol is realized.
The embodiment of the invention discloses an intelligent lighting system compatible with DMX512 and a scanning protocol, which comprises an upper computer, a lower computer and an LED display dot matrix; the upper computer is connected with the lower computer through a communication interface, and the lower computer is used for controlling the display of the LED display dot matrix;
the lower computer comprises an ARM microprocessor and an FPGA (field programmable gate array), wherein a FLASH memory and a jumper cap are configured outside the ARM microprocessor, the two sides of the jumper cap are arranged in different modes, if one side of the jumper cap is communicated with the ARM microprocessor, the ARM microprocessor selects to work in a daisy chain signal control protocol, and if the other side of the jumper cap is communicated with the ARM microprocessor, the internal control protocol of the ARM microprocessor selects a clock signal to recur serial signals;
the ARM microprocessor is used for acquiring an external instruction from the upper computer through the communication interface and reading data in the FLASH memory; the ARM microprocessor analyzes the peripheral data, judges which control protocol is adopted, and transmits an instruction containing a specified control protocol to the FPGA;
the FPGA is used for generating a screen display control signal according to a specified control protocol after receiving an instruction sent by the ARM, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal and is sent to the LED display dot matrix;
and the LED display dot matrix receives the screen display control signal sent by the FPGA and displays the screen display control signal under the control of the FPGA.
Furthermore, the ARM microprocessor reads the configuration scheme in the external FLASH memory through the ARM bus, performs parallel-serial conversion operation on the configuration scheme, and stores the configuration scheme into the FLASH memory.
Furthermore, the ARM microprocessor is also used for reconstructing an FPGA of the analog TAP controller in the controller, reading the configuration file from a FLASH memory built in the ARM, and executing an instruction sent by the ARM processor to interpret the configuration file.
The process of interpreting the binary file by the reconfiguration controller is as follows:
under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which JTAG instruction is, then carrying out specific processing according to the format of the instruction, generating TCK, TMS, TDI and TDO signals which are taken as JTAG interface excitation of a target programmable device and are connected in series with a JTAG port of the target FPGA programming device to form a daisy chain, and carrying out system programming on the target programmable device under the control of an ARM microprocessor.
And a large-capacity memory can be configured outside the ARM microprocessor. And a memory is arranged outside the FPGA and used for time-sharing reading of data containing gray scale and brightness.
The invention also provides a compatible method of the intelligent lighting system based on the compatible DMX512 and scanning protocol, which comprises the following steps:
the ARM microprocessor acquires an instruction set from an upper computer through a communication interface, judges which control protocol is adopted according to data acquired from the jumper cap, and transmits an instruction containing a specified control protocol to the FPGA;
after receiving the instruction sent by the ARM, the FPGA generates a screen display control signal according to a specified control protocol, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal, and the screen display control signal is sent to the LED display dot matrix;
the LED display dot matrix is displayed under the control of the screen display control signal.
In connection with the above technical solution, the method further comprises the steps of:
and the ARM microprocessor reads the configuration scheme in the external FLASH memory through an ARM bus, performs parallel-serial conversion operation on the configuration scheme, and stores the configuration scheme into the FLASH memory.
The ARM microprocessor reconstructs an FPGA simulating a TAP controller in the controller, reads a configuration file from a FLASH memory built in the ARM, and executes an instruction sent by the ARM processor to interpret the configuration file.
In a specific embodiment of the invention, an ARM and FPGA reconfiguration processor is adopted, and input and output protocol control is selected through a jumper wire selection port. Two definitions are made for the protocol interface in terms of circuit design and coding inside the FPGA: 1. a differential signal parallel interface supporting a daisy chain structure; 2. a serial signal recurred by a clock signal. Two kinds of signals are selected internally, and in the embodiment of the invention, a 3-pin jumper cap is selected and arranged to select from the outside. The jumper cap is in short circuit with the left two pins, the processor selects to work according to a daisy chain signal protocol, and the jumper cap selects the internal protocol of the right processor to select a clock signal to recur serial signals. The conversion of multiple protocols is realized through the selection of the jumper cap. The ARM has a relatively strong transaction management function, can be used for running interfaces, application programs and the like, and has the advantages mainly in the aspect of control. FPGAs can be programmed with VHDL or verilog hdl, are flexible, and are fully designed for development and verification due to the ability to program, debug, reprogram, and repeat operations. When the circuit is slightly changed, the advantages of the FPGA can be better displayed. In addition, because the FPGA is a powerful gate array, when a large number of logic operations exist in the design, the operation speed advantage of the FPGA is more obvious.
Generally, the whole system mainly comprises an upper computer, a lower computer, a communication system, a controller, a dot matrix module and the like, and a system diagram is as follows:
the host computer is generally a conventional PC system or an embedded host based on liunx. The method is mainly used for debugging the upper computer, importing a playing source file and the like.
The dual-protocol dual-core processor is a computing core formed by the cooperation of an ARM and an FPGA and the cooperation of a program code inside a processor and an external jumper cap. The communication interface reads an external instruction, the internal memory stores program data and protocol codes, the arm reads data in the flash memory after receiving the external instruction, analyzes which control protocol needs to be adopted by peripheral data, transmits the instruction to the FPGA after analysis and confirmation, and encodes the input and output of the FPGA, thereby outputting a corresponding protocol instruction. The main system diagram is shown in fig. 2.
In fig. 2, on one hand, the ARM processor reads the stored protocol code in the external FLASH through the ARM bus: the parallel daisy chain structure and the serial TTL structure carry out parallel-serial conversion operation on the serial TTL structure and store the serial TTL structure into a FLASH memory; on the other hand, the FPGA simulating the TAP controller in the ARM controller reads the configuration file from the built-in FLASH memory of the ARM, executes the instruction sent by the ARM processor to interpret the file, and the method for reconstructing the controller to interpret the binary file comprises the following steps: under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which instruction is, then carrying out specific processing according to the protocol format (differential parallel daisy chain protocol or clock recursion serial signals) of the instruction, generating TCK, TMS, TDI and TDO signals which are used as programming interface excitation of a target programmable device and are connected in series with a programming interface of a target FPGA programming device to form a daisy chain, and carrying out system programming on the target programmable device under the control of the ARM processor.
The important part of the display control circuit system mainly comprises an input interface circuit, a data conversion and signal control circuit and a signal decoding output driving circuit. When the number of the display pixel lattices is more, the more data needs to be processed by the processing core, the time for data transmission and control is also increased, and the time for completing one-screen scanning driving or the time for sending a data packet is longer. Therefore, we have chosen high speed ARM and programmable logic array FPGAs in this processor.
The upper computer sends the instruction set to the ARM microprocessor through a communication interface (a serial port or RJ 45), the ARM microprocessor puts the received instruction set into an external FLASH for storage, the content is not lost after power failure, and meanwhile, the ARM external expansion storage is used for storing data for fast operation, so that the processor can be called in time. After receiving the ARM instruction, the FPGA completes decoding adaptation of hardware output and completes a pixel driving process, the internal solidified digital logic is responsible for generating a screen display control signal, and the external storage is used for time-sharing reading of gray scale, brightness and other data. Meanwhile, the FPGA reads the gray data signals from the external storage, converts and decodes the gray data signals into screen data and then serially outputs the screen data to the signal data bus of the corresponding color. The storage data expanded outside the FPGA forms a data buffering and switching area, sequential logic is adopted, data are written into one memory at a certain moment, the other memory is converted by the FPGA logic read data and then sent to a display screen, and the two memories are switched alternately, so that the high-speed screen loading and the display continuity of the data are ensured. The ARM is externally provided with a large-capacity memory and a flash memory, so that a larger display area can be supported, more display contents can be stored, and a better display effect can be obtained.
It will be appreciated that modifications and variations are possible to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the scope of the appended claims.
Claims (10)
1. An intelligent lighting system compatible with DMX512 and a scanning protocol is characterized by comprising an upper computer, a lower computer and an LED display dot matrix; the upper computer is connected with the lower computer through a communication interface, and the lower computer is used for controlling the display of the LED display dot matrix;
the lower computer comprises an ARM microprocessor and an FPGA (field programmable gate array), wherein a FLASH memory and a jumper cap are configured outside the ARM microprocessor, the two sides of the jumper cap are arranged in different modes, if one side of the jumper cap is communicated with the ARM microprocessor, the ARM microprocessor selects to work in a daisy chain signal control protocol, and if the other side of the jumper cap is communicated with the ARM microprocessor, the internal control protocol of the ARM microprocessor selects a clock signal to recur serial signals;
the ARM microprocessor is used for acquiring an external instruction from the upper computer through the communication interface and reading data in the FLASH memory; the ARM microprocessor analyzes peripheral data, judges which control protocol is adopted, and transmits an instruction containing a specified control protocol to the FPGA;
the FPGA is used for generating a screen display control signal according to a specified control protocol after receiving an instruction sent by the ARM, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal and is sent to the LED display dot matrix;
and the LED display dot matrix receives the screen display control signal sent by the FPGA and displays the screen display control signal under the control of the FPGA.
2. The DMX512 and scanning protocol compatible intelligent lighting system of claim 1 wherein the ARM microprocessor reads the configuration scheme from the external FLASH memory via the ARM bus, performs parallel to serial conversion on the configuration scheme, and stores the configuration scheme into the FLASH memory.
3. The DMX512 and scanning protocol compatible smart lighting system of claim 1 wherein the ARM microprocessor is further configured to reconfigure an FPGA of the controller that emulates the TAP controller, read the configuration file from a FLASH memory built into the ARM, and execute instructions from the ARM processor to interpret the configuration file.
4. The DMX512 and scanning protocol compatible smart lighting system of claim 3 wherein the reconfiguration controller interprets the binary file process as follows:
under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which JTAG instruction is, then performing specific processing according to the format of the instruction, generating TCK, TMS, TDI and TDO signals which are taken as JTAG interface excitation of a target programmable device, connecting in series with a JTAG interface of a target FPGA programming device to form a daisy chain, and performing system programming on the target programmable device under the control of an ARM microprocessor.
5. The DMX512 and scanning protocol compatible smart lighting system of claim 1 wherein the ARM microprocessor is configured externally with a large memory.
6. The intelligent lighting system compatible with DMX512 and scanning protocol as claimed in claim 1, wherein the FPGA is externally provided with a memory for time-sharing reading of data containing gray scale and brightness.
7. A method for compatible DMX512 and scanning protocol compatible intelligent lighting system based on claim 1, characterized by the following steps:
the ARM microprocessor acquires an instruction set from an upper computer through a communication interface, judges which control protocol is adopted according to data acquired from the jumper cap, and transmits an instruction containing a specified control protocol to the FPGA;
after receiving the instruction sent by the ARM, the FPGA generates a screen display control signal according to a specified control protocol, wherein the screen display control signal comprises a decoding adaptation signal and a pixel driving signal, and the screen display control signal is sent to the LED display dot matrix;
the LED display dot matrix is displayed under the control of the screen display control signal.
8. The method of claim 7, further comprising the steps of:
and the ARM microprocessor reads the configuration scheme in the external FLASH memory through an ARM bus, performs parallel-serial conversion operation on the configuration scheme, and stores the configuration scheme into the FLASH memory.
9. The method of claim 7, further comprising the steps of:
the ARM microprocessor reconstructs an FPGA simulating a TAP controller in the controller, reads a configuration file from a FLASH memory built in the ARM, and executes an instruction sent by the ARM processor to interpret the configuration file.
10. The method of claim 9, wherein the reconstruction controller interprets the binary file as follows:
under the control of an ARM processor, reading a byte from a FLASH loaded with a configuration file, judging which JTAG instruction is, then performing specific processing according to the format of the instruction, generating TCK, TMS, TDI and TDO signals which are taken as JTAG interface excitation of a target programmable device, connecting in series with a JTAG interface of a target FPGA programming device to form a daisy chain, and performing system programming on the target programmable device under the control of an ARM microprocessor.
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| CN102892235A (en) * | 2012-10-09 | 2013-01-23 | 深圳市凯铭电气照明有限公司 | Illumination control system compatible with double protocols and control method adopting DMN (Default Mode Network) protocol |
| CN102905433A (en) * | 2012-10-16 | 2013-01-30 | 常州市城市照明工程有限公司 | Multi-compatible LED (Light Emitting Diode) lighting control system |
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| US7394210B2 (en) * | 2004-09-29 | 2008-07-01 | Tir Technology Lp | System and method for controlling luminaires |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102892235A (en) * | 2012-10-09 | 2013-01-23 | 深圳市凯铭电气照明有限公司 | Illumination control system compatible with double protocols and control method adopting DMN (Default Mode Network) protocol |
| CN102905433A (en) * | 2012-10-16 | 2013-01-30 | 常州市城市照明工程有限公司 | Multi-compatible LED (Light Emitting Diode) lighting control system |
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