CN106647519A

CN106647519A - Multifunctional USB-JTAG interface FPGA download line based on single-chip microcomputer

Info

Publication number: CN106647519A
Application number: CN201611253006.5A
Authority: CN
Inventors: 卢建良; 王悦
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2017-05-10

Abstract

The invention discloses a multifunctional USB-JTAG interface FPGA download line based on a single-chip microcomputer. The single-chip microcomputer is used to simulate a JTAG protocol, and the function of the corresponding download line is realized, and at the same time, an upper computer is used to convert a programmed file according to the model of the FPGA acquired by the single-chip microcomputer, and is used to transmit the file to the single-chip microcomputer by a USB interface, and then the single-chip microcomputer is used to transmit the file to an FPGA development board. The multifunctional USB-JTAG interface FPGA download line is advantageous in that versatility is provided, and one line and one program are adapted to various FPGA development boards, and therefore expenses incurred for repurchasing devices are prevented, the costs of the download line are reduced, and upgrade extension is conveniently carried out.

Description

SCM Based Multifunctional USB-jtag interface FPGA downloading wires

Technical field

The present invention relates to the technical field of field programmable gate array FPGA downloading wires, and in particular to one kind is based on single The Multifunctional USB of piece machine-jtag interface FPGA downloading wires.

Background technology

In the industry the Liang great FPGA production firms of main flow are xilinx and altera, and the FPGA of two supports jtag interface Downloading wire carries out programming, but the downloading wire of two is all only supported to configure oneself chip, and cannot use with, and this not only gives User is brought using upper inconvenience, and increased cost.

The content of the invention

The present invention proposes a kind of USB- based on single-chip microcomputer (single-chip microcomputer model CY7C68013A that the present invention is adopted) JTAG downloading wires, can support that the FPGA to Xilinx, Altera and the chip of other support jtag interface programmings are configured.

The technical solution used in the present invention is：A kind of SCM Based Multifunctional USB-jtag interface FPGA downloading wires, By chip microcontroller, host computer procedure first loads single-chip microcomputer firmware to its Core Feature by USB interface, and single-chip microcomputer is performed Firmware program, by jtag interface No. ID of fpga chip is read, and returns to host computer procedure, and host computer obtains IDCODE Afterwards, programming file is changed on demand, be sent to single-chip microcomputer, and programming is in FPGA.

The SCM Based Multifunctional USB-jtag interface FPGA downloading wires, is read first by single-chip microcomputer IDCODE, makes state machine return to TEST-LOGIC-RESET.Control TMS and clock, makes state machine through Run-Test/ Idle, Select-DR-Scan, Select-IR-Scan, Capture-IR jump to SHIFT-IR states.Send to state machine Read the instruction of IDCODE.

Then control TMS and clock, make state machine through Exit1-IR, Updata-IR, Select-DR-Scan, Capture-IR comes Shift-DR states, reads IDCODE, returns to host computer.Host computer is obtained after IDCODE, is turned on demand Programming file is changed, single-chip microcomputer (CY7C68013A) is sent to, single-chip microcomputer (CY7C68013A) controls JTAG TAG data programming In entering FPGA.

The present invention principle be：

Resolving ideas of the present invention are exactly to use single-chip simulation JTAG protocol, realize the function of respective downloaded line, while on Position machine needs the model according to the FPGA obtained by single-chip microcomputer, conversion programming file to be sent to single-chip microcomputer by USB, then by Single-chip microcomputer is sent to FPGA development boards.The firmware program of single-chip microcomputer, simulates JTAG TAP state machines, reads IDCODE, obtains The model of FPGA, returns to host computer, and host computer polling routine data obtain more information, and make a choice, conversion programming text Part, is sent to single-chip microcomputer, continues to simulate JTAG protocol programming file.

Advantage of the present invention and good effect are：

(1) advantage of the present invention is versatility, realizes one program of single line and adapts to many FPGA development boards.

(2) advantage of the present invention is low cost, and the present invention adopts single-chip microcomputer price to be adopted well below specific download line Chip price, the average price of downloading wire can be substantially reduced.

(3) advantage of the present invention is autgmentability, and firmware is stored in PC ends, and upper computer software is on startup by firmware loads to list Piece machine, therefore need to only update the firmware file at PC ends and just can realize the upgrading or extension of downloading wire function.

Description of the drawings

Fig. 1 is JTAG TAG state machines in prior art；

Fig. 2 uses scene for downloading wire of the present invention；

Fig. 3 is workflow of the present invention；

Fig. 4 is workflow schematic diagram of the present invention.

Specific embodiment

Below in conjunction with the accompanying drawings and specific embodiment further illustrates the present invention.

As shown in figure 1, the core of JTAG is TAG state machines, in SHIFT-IR state write instructions, then SHIFT-DR again State reads or writes data.By Single-chip Controlling jtag interface sequential in the present invention, according to state transition figure, enter first Enter SHIFT-IR states, write control instruction (such as reads ID instructions, write configuration data instruction), and then state of a control machine enters Enter SHIFT-DR states, read or write data (such as chip id, configuration data) corresponding with control instruction.

As shown in Fig. 2 downloading wire one end is connected to PC by USB interface, the other end is connected to by jtag interface The download mouth of FPGA, PC is by the downloading wire by configuration file programming to FPGA.

As shown in Figure 3 and Figure 4, first IDCODE is read by single-chip microcomputer, the tms signal in jtag interface puts one, keeps 5 Individual clock (practical operation maintains 10 clock in order to ensure resetting), makes state machine return to TEST-LOGIC-RESET.

Control TMS and clock, makes state machine through Run-Test/Idle, Select-DR-Scan, Select-IR- Scan, Capture-IR jump to SHIFT-IR states.

TMS is set as 0, TDI and clock is controlled, the instruction for reading IDCODE is sent to state machine, start to send from lowest order Data.

Last cycle of said process redirects state machine state while reading in last position 0 of instruction, then controls TMS processed and clock, makes state machine come through Exit1-IR, Updata-IR, Select-DR-Scan, Capture-IR Shift-DR states.

TMS is set as 0, clock is controlled, 32 data are read from TDO, return to host computer, obtain IDCODE.

Host computer is obtained after IDCODE, and programming file is changed on demand, is sent to Single-chip Controlling JTAG TAG and data are burnt In writing into FPGA.

Claims

1. a kind of SCM Based Multifunctional USB-jtag interface FPGA downloading wires, its Core Feature passes through single-chip microcomputer reality It is existing, it is characterised in that：First host computer procedure loads single-chip microcomputer firmware by USB interface, and single-chip microcomputer performs firmware program, passes through Jtag interface reads No. ID of fpga chip, and returns to host computer procedure, and host computer is obtained after IDCODE, and programming is changed on demand File, is sent to single-chip microcomputer, and programming is in FPGA.

2. SCM Based Multifunctional USB according to claim 1-jtag interface FPGA downloading wires, it is characterised in that： First IDCODE is read by single-chip microcomputer, make state machine return to TEST-LOGIC-RESET；Control TMS and clock, makes state Machine jumps to SHIFT-IR shapes through Run-Test/Idle, Select-DR-Scan, Select-IR-Scan, Capture-IR State；The instruction for reading IDCODE is sent to state machine；

Then TMS and clock is controlled, state machine is made through Exit1-IR, Updata-IR, Select-DR-Scan, Capture- IR comes Shift-DR states, reads IDCODE, returns to host computer；Host computer is obtained after IDCODE, and programming text is changed on demand Part, is sent to single-chip microcomputer, and Single-chip Controlling JTAG TAG enters data programming in FPGA.