CN201349208Y

CN201349208Y - FPGA multi-mode configuration circuit

Info

Publication number: CN201349208Y
Application number: CNU2008202355111U
Authority: CN
Inventors: 魏洵佳
Original assignee: Konka Group Co Ltd
Current assignee: Konka Group Co Ltd
Priority date: 2008-12-23
Filing date: 2008-12-23
Publication date: 2009-11-18
Anticipated expiration: 2018-12-23

Abstract

The utility model provides an FPGA configuration circuit with multi configuration modes for overcoming the shortcoming of single configuration mode of an existing F P G A configuration circuit, which comprises a memory and an on-site programmable gate array chip, wherein the memory is connected with the on-site programmable gate array chip, and does configuration control and data exchange for the on-site programmable gate array chip, the memory is an F L A S H chip with an S P I series bus, and the configuration circuit further comprises a remote communication chip, a buffer and a data selector, wherein the remote communication chip is connected with a buffer and the on-site programmable gate array chip, and the buffer is connected into the on-site programmable gate array chip and the data selector, and the on-site programmable gate array chip and the buffer are connected on the input end of the F L A S H chip after connecting with the data selector, and the output end of the F L A S H chip is connected with the on-site programmable gate array chip. The F P G A configuration circuit is simultaneously provided with three configuration modes, and has the advantages of flexibility, reliability and lower production cost.

Description

A kind of FPGA multi-mode configuration circuit

Technical field

The utility model relates to a kind of FPGA configuration circuit, relates to a kind of FPGA configuration circuit with various configurations pattern particularly.

Background technology

FPGA is based on the application technology of SRAM (static memory), and program can not be preserved, and needs when powering on FPGA to be configured.The configuration mode of FPGA has multiple, FPGA with ALTERA company is an example, three kinds of configuration downloading modes are generally arranged: the one, series arrangement Mode A S (Active Serial Configuration) initiatively, it sends control signal by embedded configuration module of FPGA and dedicated pin and goes the boot configuration operating process; The 2nd, passive serial configuration mode PS (Passive Serial Configuration) then sends control signal by outer computer or controller and goes the boot configuration process.Also have a kind of JTAG that is used to debug (JointTest Action Group) configuration mode, be mainly used in the online download and the border debugging of development program, also can be used for the curing of program.

Existing FPGA configuration circuit generally all is single configuration, as adopt initiatively series arrangement pattern, then do not support the remote online upgrading, adopt the passive serial configuration mode can utilize serial ports to be implemented in the sequence of threads upgrading, and can change special-purpose EEPROM into FLASH with SPI universal serial bus, except that when powering on, finishing to the configuration of FPGA the new procedures code being write the FLASH zone of appointment, simultaneously also can be in non-program code area memory access user's data, the parameter of FLASH, this mode has brought flexibility for the application of FPGA, and weak point is to have increased overhead.

The utility model content

The utility model is the deficiency that overcomes above-mentioned existing FPGA configuration circuit, and a kind of FPGA configuration circuit with various configurations pattern is provided.

The utility model realizes that the technical scheme that goal of the invention adopts is, a kind of FPGA multi-mode configuration circuit, comprise memory and field programmable gate array chip, described memory connects field programmable gate array chip and can be configured control and exchanges data to it, it is characterized in that: described memory is the FLASH chip with SPI universal serial bus, described configuration circuit also comprises the telecommunication chip, buffer and data selector, described telecommunication chip inserts buffer and field programmable gate array chip, described buffer inserts field programmable gate array chip and data selector, field programmable gate array chip with insert FLASH chip input after buffer is connected data selector, the FLASH chip output connects field programmable gate array chip.

Better, described field programmable gate array chip is connected with the programming signal socket.

Better, described buffer is eight bus buffers, and described data selector is four alternative data selectors, described configuration circuit also comprise one reset chip and four or two the input or the door, the output of the chip that resets with or the door 6a or the door 6d link to each other; Or door 6a input outputs to or door 6b from field programmable gate array chip, eight bus buffers and the chip that resets; Described or door 6b input from or door 6a and telecommunication chip, output to four alternative data selectors; Described or door 6c imports from field programmable gate array chip and telecommunication chip, outputs to or door 6d; Described or door 6d input from or the door 6c and the chip that resets, output to eight bus buffers.

Described FLASH is the non-volatile flash memory chip with ISP universal serial bus, and preference is the W25X family chip, and input links to each other with four alternative data selectors its control signal with data, and data output links to each other with FPGA;

Described four alternative data selector preferences are 74HC157, and its input meets the pin of initiatively programming, I/O control pin and eight bus buffers of FPGA, its gating signal input termination or door 6b respectively;

Described telecommunication chip preference is LVDS Deserializer LV1224, and the data/address bus pin links to each other with eight bus buffers with FPGA, its phase-locked loop state output signal/LOCK with or the door 6b or the door 6C link to each other with FPGA;

The JTAG programming signal socket that described programming signal socket is FPGA links to each other with the relevant tube leg of FPGA.

Described configuration circuit also comprises resistance [81-87], described resistance [81] connects field programmable gate array chip and eight bus buffers for pull down resistor, described resistance [82] for pull down resistor connect field programmable gate array chip and or the door 6c, described resistance [83-84] connects field programmable gate array chip for pull-up resistor, described resistance [85-86] connects field programmable gate array chip and eight bus buffers for pull-up resistor, described resistance [86] also connects or door 6a, and described resistance [87] connects field programmable gate array chip for pull-up resistor, the telecommunication chip, or door 6b and or door 6c.

The beneficial effects of the utility model are, need not additionally to add under the situation of microprocessor, change the monotype programmed circuit of FPGA into the multi-mode programmed circuit, configuration when making it both can finish FPGA and power on by active series arrangement pattern, can finish remote upgrade by the passive serial configuration mode again to program, possess JTAG configuration debugging and program Solidification function simultaneously, replace special-purpose EEPROM with FLASH in addition with ISP communication bus, opened up the storage of subscriber data district, thereby increased FPGA application flexibility and reliability, reduced design cost.This FPGA multi-mode programmed circuit needing to be particularly useful for remote upgrade and programming to require the high industry of reliability, for example automation control, LED display control, military project space flight industry etc.

Description of drawings

Fig. 1 is the utility model FPGA programmed circuit logical design schematic diagram.

Among the figure, 1 FPGA, 2 FLASH chips, 3 four alternative data selectors, 4 eight bus buffers, 5 reset chip, (6a, 6b, 6c, 6d) four or two inputs or door, 7 long-range communication chips, (81-87) resistance, 9 JTAG programming signal sockets.

Embodiment

Below in conjunction with accompanying drawing the utility model is further described.

Fig. 1 is the utility model FPGA programmed circuit logical design schematic diagram, comprises FPGA 1, FLASH 2, four alternative data selectors 3, eight bus buffers 4, chip 5,42 input or door 6, long-range communication chip 7, resistance 81-87 and JTAG programming signal socket 9 reset.

Described FPGA 1 is a field programmable gate array chip, preference is the FPGA of ALTERA company, it is programming control signal nCSO initiatively, ASDO, DCLK output respectively with the A1 of three alternative gates of four alternative data selectors 3, B1, the C1 input links to each other, the input of DATA0 data is exported SO with the data of FLASH 2, the D5 output of eight bus buffers 4 links to each other, configuration status signal nSTATE output connects draws resistance 83, configuration is finished signal CONF_DONE output and is connected and draw resistance 84, configuration enabling signal nCONFIG input connects the D7 output and the pull-up resistor 85 of eight bus buffers 4, programming mode selects signal MSEL0 to connect the D6 output and the pull down resistor 81 of eight bus buffers 4, MSEL1 ground connection, other has three I/O pin definitions is IO_/CS, IO_SO, IO_SCK output respectively with the A0 of three alternative gates of four alternative data selectors 3, B0, the C0 input links to each other, an I/O pin definitions is the data output pin SO of IO_SI data input with FLASH 2, the D5 output of eight bus buffers 4 links to each other, I/O pin definitions for the output of IO_/EN number with or a door C link to each other with pull down resistor 82, I/O pin definitions be IO_/FH output with or door a, the D0 of eight bus buffers 4 links to each other with pull-up resistor 86, I/O pin definitions be the IO_/LOCK input with long-range communication interface 7 /LOCK exports and links to each other with pull-up resistor 87, the JTAG cable of FPGA 1 is downloaded relevant pins and is linked to each other with socket 9, part I/O pin links to each other with the data/address bus of long-range communication interface 7, and all the other pin accompanying drawings of FPGA 1 omit.

Described FLASH chip 2 is the nonvolatile flash memory chips with ISP universal serial bus, preference is the W25X family chip, its CE input port/CS, serial input data port SI and input end of clock mouth SCK meet output signal Y0, Y1 and the Y2 of 3 three alternative gates of four alternative data selectors respectively, serial data delivery outlet SO receive simultaneously FPGA 1 initiatively programme pin data input pin DATA0 and be defined as an I/O pin of IO_SI input.

The input of described eight bus buffers 4 connects the data/address bus of telecommunication chip 7, its D0 output connects or door 6a and pull-up resistor 86, D1 output meets the C0 of four alternative data selectors 3, D2 output meets the B0 of four alternative data selectors 3, D3 output meets the A0 of four alternative data selectors 3, D4 output meets the DCLK of FPGA 1 and the C1 of four alternative data selectors 3, D5 output meets DATA0 and the IO_SI of FPGA 1, D6 output connects MSEL0 and the pull down resistor 81 of FPGA 1, D7 output connects nCONFIG and the pull-up resistor 85 of FPGA 1, and the output enable signal connects or door 6d.

The preference of described four alternative data selectors 3 is 74HC157, and above-mentioned FPGA of being connected respectively to 1 and eight bus buffers 4 are seen in its input, and the above-mentioned FLASH of being connected to 2 is seen in output, and the input of gating signal pin connects or door 6b output.

The described chip 5 that resets has positive polarity long delay (greater than powering on configuration cycle of FPGA 1) reset signal, its output with or the door 6a or the door 6d link to each other.

Described in described four or two inputs or the door 6 or door 6a input from the IO_/FH of FPGA1, the D0 of eight bus buffers 4 and the RST of the chip 5 that resets, output to or door 6b; Described or door 6b input from or door 6a and telecommunication chip 7 /LOCK, wherein/the LOCK signal is connected to pull-up resistor 87, output is as the gating signal of four alternative data selectors 3; Described or door 6c input from the IO_/EN of FPGA 1 and telecommunication chip 7 /LOCK, wherein the IO_/EN signal is connected to pull down resistor 81 ,/LOCK signal is connected to pull-up resistor 87, outputs to or door 6d; Described or door 6d input from or the RST of the door 6c and the chip 5 that resets, output to the output enable port of eight bus buffers.

Described telecommunication core 7 type preferences are LVDS Deserializer LV1224, its data/address bus links to each other with host computer, FPGA 1 and eight bus buffers 4 respectively, bear the communication and the remote upgrade of FPGA1 and host computer, its phase-locked loop state output/LOCK as or the input of door 6b or door 6c, and lead to the IO_/LOCK pin of FPGA 1.

The annexation of described seven resistance 81-87 one ends is seen above-mentioned, and the other end ground connection of two pull down resistor 81-82 is wherein arranged, another termination power VCC of five pull-up resistor 83-87.

The JTAG 10 core cables that described JTAG programming signal socket 9 is FPGA are downloaded socket, link to each other with the relevant tube leg of FPGA.

The operation principle of the utility model FPGA multi-mode programmed circuit is as follows:

The MSEL1 of described FPGA 1, MSEL0 are that programming mode is selected signal, as MSEL1, when MSEL0 is 0, setting FPGA 1 configuration mode is active series arrangement pattern, dedicated pin nCSO, ASDO, DCLK by FPGA 1 when promptly powering on send control signal, by the DATA0 mouth program among the FLASH 2 are write among the FPGA 1.When MSEL1 be 1, when MSEL0 is 0, setting FPGA 1 configuration mode is the passive serial configuration mode, the i.e. external control signal that sends by non-FPGA 1 dedicated pin nCSO, ASDO, DCLK, the program of solidifying among remote upgrade program or the FLASH 2 is write among the FPGA 1, narrate JTAG configuration mode, active series arrangement pattern and passive serial configuration mode below respectively.

JTAG configuration mode: the general download socket of JTAG 10 core cables that described socket 9 is FPGA 1, link to each other with the JTAG relevant tube leg (TDI, TMS, TCK, TDO) of FPGA 1, main effect is to be finished the configuration to FPGA 1, peripheral I/O test or program is write among the FLASH 2 by computer, the program Solidification that also can be used for product export, the state of it and MSEL0, MSEL1 programming mode signal is irrelevant.In addition, when telecommunication chip 7 breaks away from host computer, the phase-locked loop state output/LOCK of telecommunication chip 7 is owing to have pull-up resistor 87 for high, it passes through or door 6c arrives or door 6d, or door 6d output 1 makes the D0-D7 of eight bus buffers 4 be output as three-state, by or the gating input of door 6b output 1 to four alternative data selector 3, thereby choose the 1 end input of four alternative data selectors 3 so that FPGA 1 can be with the JTAG configuration mode to FLASH 2 program curings.

Active series arrangement pattern: initiatively the series arrangement pattern is used for the configuration that powers on of FPGA 1, in order to realize powering on by the dedicated pin configurator of FPGA 1, during the back FPGA1 that must guarantee to power on disposes, mode select signal MSEL1 when promptly configuration is finished signal CONF_DONE and also do not uprised, MSEL0 all remains 0, this is that positive polarity long delay (greater than the low period of CONF_DONE) the reset signal RST that sends when being powered on by the chip 5 that resets gives security, RST leads to or door 6d, or door 6d output 1 makes the D0-D7 of eight bus buffers 4 be output as three-state, MSEL1 is 0 because of being connected to pull down resistor 81, RST also passes through or door 6a arrives or door 6b, or door b output 1 goes to choose the 1 end input of four alternative data selectors 3, this moment, all I/O pins of FPGA 1 were ternary, when disposing starting impulse signal nCONFIG automatically by low uprising, active programming control signal nCSO, ASDO, DCLK is effective, by them the program among the FLASH 2 is read among the FPGA 1.

The passive serial configuration mode: the passive serial configuration mode is used for Remote configuration or the online upgrading of FPGA 1, and it is connected to host computer by telecommunication chip 7 and realizes, and communication interface 7 when working properly its phase-locked loop state output/LOCK be low.The passive serial configuration mode has two kinds of situations, one is not work of FPGA 1, no program among failure of active series arrangement or the FLASH 2 when for example powering on, this moment, FPGA 1 all I/O pins were three-state, but the IO_/EN of FPGA 1 output is owing to have pull down resistor 82 for low, if its two FPGA 1 is in work, FPGA 1 receives that Remote configuration or online upgrading instruction back military order IO_/EN are low, add that reset signal RST also is low, make or the door 6c and or the door 6d be output as 0, the D0-D7 output of opening eight bus buffers 4 is effective, this moment, host computer only need make that D6 is 1, just FPGA1 can be changed to the passive serial configuration mode, again by D0 be 0 make or the door 6a and or the door 6b be output as 0, choose the 0 end input of four alternative data selectors 3, by D3 is 1 not choose FLASH 2, make the SO of FLASH 2 be output as three-state, send Remote configuration starting impulse signal nCONFIG by D7 afterwards, nCONFIG sends configurable clock generator by D4 after postponing a period of time from low to high again, send configuration data by D5, can finish Remote configuration FPGA 1.Owing to can not preserve after the Remote configuration power down of above-mentioned FPGA 1, also need ROMPaq is write among the FLASH 2.The program updates of FLASH 2 has two kinds of methods, one is that host computer directly writes to the BOOT code area of FLASH 2, if not work of FPGA 1, FPGA 1 all I/O pins are three-state, if FPGA 1 is in work, FPGA 1 receives that FLASH 2 writes instruction back military order IO_/CS, IO_SO, IO_SCK, IO_/FH is changed to ternary invalid, make IO_/EN hang down the D0-D7 that makes eight bus buffers 4 to export effectively, this moment, host computer only need make D6 0 FPGA 1 is changed to initiatively series arrangement pattern, make D7 1 start invalid configuration, be 0 to choose the 0 end input of four alternative data selectors 3 by D0 again, by D3 is 0 to choose FLASH 2, send by D1 afterwards and write clock, send by D2 and write data, can finish program upgrade FLASH 2.It is two for to write ROMPaq to FLASH 2 indirectly by FPGA1, send 2 second kinds of programs of FLASH by host computer and write instruction this moment, after FPGA 1 receives, military order IO_/EN is high, make the D0-D7 of eight bus buffers 4 be output as three-state, make IO_/FH output 0, make or the door 6a or the door 6b also export 0, thereby choose the 0 end input of four alternative data selectors 3, start IO_/CS, IO_SO, IO_SCK control signal simultaneously, the ROMPaq that host computer can be sent is written among the FLASH 2.Adopt above-mentioned two kinds of methods, host computer also can write direct or read and write data indirectly by FPGA1 in long-range data field to FLASH 2, and FPGA 1 itself also can carry out the data read-write operation of FLASH2 data field separately.

The utility model FPGA multi-mode programmed circuit has improved the reliability of Remote configuration or upgrading, for example host computer is written to FLASH 2 sudden power midway with ROMPaq, the upgrading failure, FPGA 1 does not work after causing active series arrangement pattern to power on, after in case host computer detects, it can send FPGA 1 passive serial configuration-direct automatically, directly recent program is write among the FPGA1, makes FPGA 1 start working at once.

In addition, FLASH 2 capacity are enough big, except that the configurator that can write FPGA 1, also can utilize the data of its complementary space read-write design, for example required pixel correction data, gamma curve, Control Parameter etc. in the LED Display Technique.

The foregoing description is a better embodiment of the present utility model; those skilled in the art will be appreciated that; above-mentioned better embodiment only is used for illustrating the utility model; be not to be used for limiting protection range of the present utility model; any within spirit of the present utility model and principle scope; any modification of being done; equivalence is replaced; improve etc.; for example change four alternative data selectors into two bus buffers; conversion eight bus buffer D0-D7 signal locations; adopt the communication chip of other model; and for example with four alternative data selectors 3; eight bus buffers 4 and four or two inputs or door 6 functions that have all should be included within the rights protection scope of the present utility model by CPLD or microprocessor realization etc.

Claims

1, a kind of FPGA multi-mode configuration circuit, comprise memory and field programmable gate array chip (1), described memory connects field programmable gate array chip (1) and can be configured control and exchanges data to it, it is characterized in that: described memory is the FLASH chip (2) with SPI universal serial bus, described configuration circuit also comprises telecommunication chip (7), buffer (4) and data selector (3), described telecommunication chip (7) inserts buffer (4) and field programmable gate array chip (1), described buffer (4) inserts field programmable gate array chip (1) and data selector (3), field programmable gate array chip (1) is connected data selector (3) back and inserts FLASH chip (2) input with buffer (4), FLASH chip (2) output connects field programmable gate array chip (1).

2, a kind of FPGA multi-mode configuration circuit according to claim 1, it is characterized in that: described field programmable gate array chip (1) is connected with JTAG programming signal socket (9).

3, a kind of FPGA multi-mode configuration circuit according to claim 1, it is characterized in that: described buffer (4) is eight bus buffers, described data selector (3) is four alternative data selectors.

4, a kind of FPGA multi-mode configuration circuit according to claim 1 is characterized in that: described configuration circuit also comprises reset chip (5) and four or two inputs or a door (6a-6d), the output of the chip that resets (5) with or door (6a) or (6d) link to each other; Or door (6a) input outputs to or door (6b) from field programmable gate array chip (1), eight bus buffers (4) and the chip that resets (5); Described or the door (6b) input from or the door (6a) and telecommunication chip (7), output to four alternative data selectors (3); Described or door (6c) is imported from field programmable gate array chip (1) and telecommunication chip (7), outputs to or door (6d); Described or the door (6d) input from or the door (6c) and the chip that resets (5), output to eight bus buffers (4).

5, a kind of FPGA multi-mode configuration circuit according to claim 1, it is characterized in that: described configuration circuit also comprises resistance (81-87), described resistance (81) connects field programmable gate array chip (1) and eight bus buffers (4) for pull down resistor, described resistance (82) for pull down resistor connect field programmable gate array chip (1) and or the door (6c), described resistance (83-84) connects field programmable gate array chip (1) for pull-up resistor, described resistance (85-86) connects field programmable gate array chip (1) and eight bus buffers (4) for pull-up resistor, described resistance (86) also connects or door (6a), and described resistance (87) connects field programmable gate array chip (1) for pull-up resistor, telecommunication chip (7), or door (6b) and or door (6c).