CN201477429U - Controller for high-count stitching jacquard based on FPGA - Google Patents

Abstract

The utility model discloses a controller for a high-count stitching jacquard based on an FPGA (field programmable gate array). An SDRAM controller in an FPGA chip is connected to an SDRAM memory chip through an address, data and a control signal; a pin corresponding to the FPGA chip is connected with a serial configuration memorizer EPCS16; a weft selecting signal and an encoder signal are both directly connected with the FPGA chip through one general-purpose I/O pin; a pattern output module and an SD memory card are connected with the FPGA chip through another general-purpose I/O pin respectively; and an Nios II/f kernel embedded in the FPGA interacts with PIO peripheral equipment, an IO port control module, an EPCS controller, an SPI mode controller and an SDRAM controller through an AvaIon bus. An electronic jacquard control system adopts the FPGA, the serial configuration device, the SD memory card and the pattern output module embedded in an Nios II/f system as cores, has the advantages of flexible hardware design and short development cycle, and solves the problems in the jacquard control system of low data transmission speed and small pattern file memory space, thereby realizing the high-count stitching and the high-speed jacquard.

Description

Large needle based on FPGA is counted jacquard loom controller

Technical field

The utility model relates to electronic jacquard machine control system, specifically relates to a kind of large needle based on FPGA and counts jacquard loom controller.

Background technology

Electronic jacquard machine is to utilize electronic control mechanism to replace mechanical type jacquard weave tap, realizes jacquard weaving by the sink-float of control shades of colour warp thread and the action of shuttle.It is simple in structure, speed is high, at home and abroad is widely used.Current Britain Bonus (Bonas) company, Switzerland history pottery Bill (Staubli) company, German Ge Luosi (Gross) jacquard that company developed have been represented the production and the application level of electronic jacquard machine in the world.Up to now, though external electronic jacquard machine is in advanced level, its electronic jacquard machine control system also is that to be in the world top, and it is slow that the jacquard machine control system of above-mentioned producer all has data rate, the bottleneck problem of pattern data low memory.With regard to domestic, it seems that totally three phases has roughly been experienced in the development of electronic jacquard machine control system:

Phase one: the control box of chip microcontroller at first occurred, design is simple relatively, cost is also relatively more cheap, but is subjected to the limitation of single-chip microcomputer function, function is abundant inadequately, and does not have operating system, and the extendability of systemic-function is not strong, be not easy upgrading, be difficult to satisfy user's requirement.

Subordinate phase: PC104 realizes control system, but the cost height of PC104, and interface control is inconvenient.Along with evolution of embedded technology, powerful embedded microprocessor has appearred, after having accumulated development technique and development Experience, enter the embedded control system epoch comprehensively.

Phase III: embedded control system, along with Embedded development, 32 flush bonding processor is widely used.What utilization was maximum at present is exactly arm processor, though function is comparatively powerful, the construction cycle is long, and the hardware circuit complexity also is difficult to satisfy actual needs.

Summary of the invention

Deficiency at domestic and international electronic jacquard machine control system technology, the purpose of this utility model is to provide the large needle based on FPGA to count jacquard loom controller, solve bottleneck problems such as the slow and colored type file storage of the jacquard machine control system pattern data transmission speed amount of current existence is low, realize that the large needle of electronic jacquard machine is counted jacquard weave.

In order to achieve the above object, the technical solution adopted in the utility model is:

The utility model comprises fpga chip, SDRAM storage chip, series arrangement storer EPCS16, selects the latitude signal, code device signal, flower type output module and SD storage card; Sdram controller in the fpga chip is connected to the SDRAM storage chip by address, data and control signal, the pin of the correspondence of fpga chip connects with series arrangement storer EPCS16, select latitude signal and code device signal all directly to link by general purpose I/O pin and fpga chip, flower type output module and SD storage card link by other I/O pin and fpga chip respectively.

Described fpga chip comprises: NiosII/f processor, jtag controller, system identifier, Avalon bus module, PIO peripheral hardware, IO mouth control module, EPCS controller, SPI mode controller and sdram controller; Nios II/f kernel (8) connects with the Avalon bus module by instruction bus and data bus; Jtag controller is a JTAG debugging module that is integrated in the Nios II/f kernel, and jtag controller is connected to the JTAG device by jtag interface; System identifier links by Avalon bus module and Nios II/f kernel; PIO peripheral hardware, IO mouth control module, EPCS controller, SPI mode controller and sdram controller are connected on the Avalon bus module by the Avalon interface of definition respectively, and then mutual with Nios II/f kernel information.Sdram controller is connected to the SDRAM storage chip by address, data and control signal; The SPI mode controller connects with the SD storage card by 4 pin serial line interfaces; The EPCS controller directly directly is connected to series arrangement storer EPCS16 by the pin on the circuit board; IO mouth control module is exported four road signals by the flower type and is connected with flower type output module; The PIO peripheral hardware connects with selecting latitude signal and code device signal by universaling I/O port.

The beneficial effect that the utlity model has is:

The utility model adopts a kind of SOC (system on a chip) that embeds Nios II/f processor based on FPGA.FPGA is a kind of field programmable gate array electronics integrated device, and its integrated level height is used for electronic jacquard machine control system, and the volume of control system is greatly reduced, and the reliability of system is also improved greatly.The programmability of FPGA also can make design, debugging and the production of electronic jacquard machine control system more flexible.Adopting the FPGA, series arrangement device, SD storage card, the flower type output module that embed the NiosII/f system is the electronic jacquard machine control system of core, its hardware design is flexible, construction cycle is short, it is slow fundamentally to solve existing jacquard machine control system data rate, the low difficult problem of flower type file storage amount, can realize large needle number, high-speed electronic jacquard, have important engineering practical value and vast market promotion potential.

Description of drawings

The large needle that Fig. 1 is based on FPGA is counted the master control borad block diagram of jacquard machine control system.

Fig. 2 is the Nios II/f system chart that embeds FPGA.

The large needle that Fig. 3 is based on FPGA is counted the circuit structure diagram of jacquard machine control system.

Among the figure: 1, fpga chip, 2, SDRAM storage chip, 3, series arrangement storer EPCS16,4, select the latitude signal, 5, code device signal, 6, spend the type output module, 7, the SD storage card, 8, Nios II/f kernel, 9, jtag controller, 10, system identifier, 11, the Avalon bus module, 12, the PIO peripheral hardware, 13, IO mouth control module, 14, EPCS controller, 15, the SPI mode controller, 16, sdram controller, 17, Switching Power Supply, 18, the master control borad of control system, 19, the interface board of control system, 20, the electromagnetic needle selection drive plate.

Embodiment

The utility model will be further described below in conjunction with drawings and Examples.

As shown in Figure 1, the utility model comprise fpga chip 1, SDRAM storage chip 2, series arrangement storer EPCS163, select latitude signal 4, code device signal 5, flower type output module 6, SD storage card 7.Wherein, the sdram controller in the fpga chip 1 is connected to SDRAM storage chip 2 by address, data and control signal, and SDRAM storage chip 2 is used for storing program, variable, heap and the storehouse that fpga chip 1 processor is carried out; Series arrangement storer EPCS16 3 connects with fpga chip by the special pin of fpga chip 1, its internal configurations data of 4 pin serial interface access that fpga chip 1 provides by series arrangement storer EPCS16 3, and SDRAM storage chip 2 internal elements are configured; Select latitude signal 4 and code device signal 5 all directly to link by general purpose I/O pin and fpga chip 1, wherein, fpga chip 1 selects 4 outputs of latitude signal by light-coupled isolation and level shifting circuit handle, and scrambler is input to code device signal 5 in the fpga chip 1 by light-coupled isolation and level shifting circuit; Flower type output module 6, SD storage card 7 link with fpga chip 1 by I/O mouth control module 13, SPI controller 15 respectively, wherein, fpga chip 1 reads SD storage card 7 inner pattern datas, exports pattern data to colored type output module 6 by clock signal, enable signal, latch signal and data-signal then.

As shown in Figure 2, described fpga chip comprises: NiosII/f processor 8, jtag controller 9, system identifier 10, Avalon bus module 11, PIO peripheral hardware 12, IO mouth control module 13, EPCS controller 14, SPI mode controller 15 and sdram controller 16; Nios II/f kernel 8 connects with Avalon bus module 11 by instruction bus and data bus; Jtag controller 9 is JTAG debugging modules that are integrated in the Nios II/f kernel 8, and jtag controller 9 is connected to the JTAG device by jtag interface; System identifier 10 links by Avalon bus module 11 and Nios II/f kernel 8; PIO peripheral hardware 12, IO mouth control module 13, EPCS controller 14, SPI mode controller 15 and sdram controller 16 respectively by the definition the Avalon interface be connected on the Avalon bus module 11, and then with Nios II/f kernel 8 information interactions.Sdram controller 16 is connected to SDRAM storage chip 2 by address, data and control signal, finishes all logics of SDRAM storage chip 2, and the function of SDRAM storage chip 2 mainly is the used application program of storage system, variable, heap and storehouse. SPI mode controller 15 connects with SD storage card 7 by 4 pin serial line interfaces; EPCS controller 14 directly directly is connected to series arrangement storer EPCS16 3 by the pin on the circuit board; IO mouth control module 13 is exported four road signals by the flower type and is connected with flower type output module 6; PIO peripheral hardware 12 connects with selecting latitude signal 4 and code device signal 5 by universaling I/O port.

Transmitting a latitude pattern data with this control system below is example, specifically introduces principle of work of the present utility model: at first the card reader by computer general-purpose is in the SD storage card 7 of 1G with the pattern data capacity of being stored in, and then card is inserted on the socket of master control borad.With downloading in the fpga chip 1 that line downloads to master control borad with compiled hardware control system design document and application program by JTGA controller 9.Begin to re-power, to fpga chip 1 configuration, program run is in SDRAM storage chip 2 automatically for series arrangement storer EPCS16.Nios II/f kernel 8 reads in pattern data by the read-write of SPI mode controller 15 from SD storage card 7, be transferred to the register in the IO mouth control module 13, wait for the enable signal of Nios II/f kernel 8, utilize four road signals of IO mouth control module 13, be that clock signal, data-signal, data latch signal and output enable signal are transferred to colored type output module 6, for the reliability that guarantees to transmit, will send four road signals and all convert differential signal to and transmit.Flower type output module 6 stores the data in the buffer zone of drive plate superior displacement register, wait for that this latitude color signal of latitude signal 4 and the loom synchronizing information of code device signal 5 determine whether data are sent to jacquard, read next latitude data then and so circulate until last latitude.

As shown in Figure 3, form by the drive plate 20 of Switching Power Supply 17, control system systematic master control board 18, control system interface board 19 and the electromagnetic needle selection of+5V/+12V based on the electronic jacquard machine control system circuit structure of FPGA; Control system systematic master control board 18 by the crystal oscillator of 50MHZ, double ten core jtag interface plug-in units, fpga chip Cyclone III EP3C25Q240C8N, a slice sdram memory HY57V561620, the miniature SD card of a slice, a slice series arrangement device EPCS16, one 10.4 cun liquid crystal display, flower type output module, select latitude signal and code device signal; Flower type output module 6 mainly is made up of difference chip MC2387 and flower type signal output interface, four road flower type signals of exporting in the fpga chip are transferred in the interface board 19 by difference chip and flower type signal output interface, and level conversion is transferred in the drive plate 20 in interface board 19 then; Fpga chip output selects latitude signal 4 by optical coupling isolation circuit with select the latitude signal output interface to be transferred to interface board 19; The code device signal 5 of the scrambler transmission that interface board 19 receives is decoded by the optical coupling isolation circuit that scrambler input interface and 6N137 form, and decoded signal is transferred in the fpga chip; Reserve some IO mouth signals on the fpga chip, given over to signal extension.

Claims (2)

1. the large needle based on FPGA is counted jacquard loom controller, it is characterized in that: comprise fpga chip (1), SDRAM storage chip (2), series arrangement storer EPCS16 (3), select latitude signal (4), code device signal (5), flower type output module (6) and SD storage card (7); Sdram controller in the fpga chip (1) is connected to SDRAM storage chip (2) by address, data and control signal, the pin of the correspondence of fpga chip (1) connects with series arrangement storer EPCS16 (3), select latitude signal (4) and code device signal (5) all directly to link by general purpose I/O pin and fpga chip (1), flower type output module (6) and SD storage card (7) link by other I/O pin and fpga chip (1) respectively.

2. a kind of large needle based on FPGA according to claim 1 is counted jacquard loom controller, and it is characterized in that: described fpga chip comprises: NiosII/f processor (8), jtag controller (9), system identifier (10), Avalon bus module (11), PIO peripheral hardware (12), IO mouth control module (13), EPCS controller (14), SPI mode controller (15) and sdram controller (16); Nios II/f kernel (8) connects with Avalon bus module (11) by instruction bus and data bus; Jtag controller (9) is a JTAG debugging module that is integrated in the Nios II/f kernel (8), and jtag controller (9) is connected to the JTAG device by jtag interface; System identifier (10) links by Avalon bus module (11) and Nios II/f kernel (8); PIO peripheral hardware (12), IO mouth control module (13), EPCS controller (14), SPI mode controller (15) and sdram controller (16) respectively by the definition the Avalon interface be connected on the Avalon bus module (11), and then with Nios II/f kernel (8) information interaction.Sdram controller (16) is connected to SDRAM storage chip (2) by address, data and control signal; SPI mode controller (15) connects with SD storage card (7) by 4 pin serial line interfaces; EPCS controller (14) directly directly is connected to series arrangement storer EPCS16 (3) by the pin on the circuit board; IO mouth control module (13) is exported four road signals by the flower type and is connected with flower type output module (6); PIO peripheral hardware (12) connects with selecting latitude signal (4) and code device signal (5) by universaling I/O port.

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