CN209215538U - Test equipment and test macro - Google Patents
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- CN209215538U CN209215538U CN201821631055.2U CN201821631055U CN209215538U CN 209215538 U CN209215538 U CN 209215538U CN 201821631055 U CN201821631055 U CN 201821631055U CN 209215538 U CN209215538 U CN 209215538U
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Abstract
The disclosure provides a kind of tested target test equipment and test macro.Test equipment couples n tested targets by the first signal wire, n scan chain cell is coupled to by second signal line, n scan chain cell is respectively coupled to n tested targets by third signal wire, wherein, n scan chain cell series connection, first scan chain cell is coupled to the serial signal line of test equipment, the controller of test equipment is executed to give an order: sending the first preset signals of the position n and synchronizing clock signals by second signal line before sending test signal, each first preset signals is set to be transmitted to a scan chain cell by the series sequence correspondence of scan chain cell according to synchronizing clock signals, and tested target corresponding with each scan chain cell is transmitted to via third signal wire.The embodiment of the present disclosure can realize individually control to multiple tested targets with limited test equipment pin.
Description
Technical field
This disclosure relates to which technical field of semiconductors, can carry out multiple tested targets in particular to one kind independent
The test equipment and test macro of test.
Background technique
In the related art, when testing multiple tested targets, in order to realize the independent survey to each tested target
Examination, generally requires that chip select line is separately configured for each tested target.
Fig. 1 is a kind of schematic diagram of tested target test scenes more in the related technology.With reference to Fig. 1, in Fig. 1, five quilts
It surveys tested target and respectively occupies an I/O interface.In the available limited situation of I/O interface of test equipment, occupies I/O interface and match
The testing efficiency of test equipment can be reduced by setting chip select line, reduce the tested target quantity that test equipment can test.
Therefore, it is necessary to multiple tested targets test equipment and test macro improve, improving test equipment can be same
When the quantity of tested target that connects, and then promote tested target testing efficiency.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The disclosure is designed to provide a kind of test equipment and test macro, for overcoming at least to a certain extent
Due to the relevant technologies limitation and defect caused by the insufficient problem of tested target quantity that connects of test equipment.
According to one aspect of the disclosure, a kind of test macro is provided, comprising:
Test equipment has the first signal wire, second signal line and serial signal line；
N tested targets, are coupled to the test equipment by first signal wire；
N concatenated scan chain cells, are coupled to the test equipment by the second signal line, pass through third signal
Line is respectively coupled to the n tested targets, and first scan chain cell is coupled to the serial signal line.
In a kind of exemplary embodiment of the disclosure, the test equipment setting are as follows:
Scan enable signal and synchronizing clock signals are sent by the second signal line, while passing through the serial signal
Line sends the first preset signals of the position n, makes each described first preset signals according to the synchronizing clock signals by the scanning
The series sequence correspondence of chain element is transmitted to the scan chain cell；
Scan disable signal is sent by the second signal line and maintains the scan disable signal, to forbid described sweep
Chain element is retouched to continue to identify and receive first preset signals；
The second preset signals are sent by the second signal line and test signal is sent by first signal wire.
In a kind of exemplary embodiment of the disclosure, first signal wire include data signal line, address signal line,
Control signal wire, the second signal line include scan enable signal line, synchronizing clock signals line, chip selection signal line, and described
Three signal wires include that secondary pieces select signal wire.
In a kind of exemplary embodiment of the disclosure, the scan chain cell includes:
First gate, first input end are coupled to serial signal input terminal, and it is defeated that the second input terminal is coupled to serial signal
Outlet, control terminal are coupled to the scan enable signal line；
D type flip flop, input terminal are coupled to the output end of first gate, and it is defeated that output end is coupled to the serial signal
Outlet, control terminal are coupled to the synchronizing clock signals line；
Or door, first input end are coupled to the scan enable signal line, the second input terminal is coupled to the serial signal
Output end；
Second gate, first input end are coupled to the chip selection signal line, and the second input terminal is set to high-impedance state, control
End is coupled to described or door output end；
Driving element, input terminal are coupled to the output end of second gate, and output end is coupled to the secondary pieces choosing
Signal wire.
In a kind of exemplary embodiment of the disclosure, the test equipment setting are as follows:
Scan enable signal is sent by the scan enable signal line；
The synchronizing clock signals are sent by the synchronizing clock signals line, while being sent by the serial signal line
The first chip selection signal of the position n makes each described first chip selection signal according to the synchronizing clock signals by the scan chain cell
Series sequence correspondence be transmitted to the scan chain cell, and select signal wire to be transmitted to and each scanning via the secondary pieces
The corresponding tested target of chain element；
Scan disable signal is sent by the scan enable signal line and maintains the scan disable signal；
The second chip selection signal is sent by the chip selection signal line, and passes through the control signal wire, the address signal
Line, the data signal line send test signal.
It is described that second chip selection signal is sent by the chip selection signal line in a kind of exemplary embodiment of the disclosure,
And test signal is sent by the control signal wire, the address signal line, the data signal line and includes:
The second chip selection signal is sent by the chip selection signal line, is made and the enabled state position in first chip selection signal
Corresponding tested target is enabled；
It sent simultaneously by the control signal wire, the address signal line, the data signal line and writes control instruction, write
Address and write data.
It is enabled state when only having one in first chip selection signal in a kind of exemplary embodiment of the disclosure
When, it is described that second chip selection signal is sent by the chip selection signal line, and pass through the control signal wire, the address signal
Line, the data signal line send test signal
The second chip selection signal is sent by the chip selection signal line, is made and the enabled state position in first chip selection signal
Corresponding tested target is enabled；
It is sent simultaneously by the control signal wire, the address signal line and reads control instruction and read address, and pass through institute
Data signal line is stated to be read out the tested target being enabled.
According to one aspect of the disclosure, a kind of test equipment is provided, comprising:
First signal wire, second signal line and serial signal line, described n tested targets of first signal wire coupling, institute
It states second signal line and is coupled to n scan chain cell, the n scan chain cell is respectively coupled to the n by third signal wire
A tested target, wherein the n scan chain cell is connected, first scan chain cell is coupled to the serial signal line, often
A scan chain cell includes d type flip flop and multiple selector；
Memory；And
The processor of memory belonging to being coupled to, the processor is configured to the finger based on storage in the memory
It enables, executes following control action:
Scan enable signal and synchronizing clock signals are sent by the second signal line, while passing through the serial signal
Line sends the first preset signals of the position n, makes each described first preset signals according to the synchronizing clock signals by the scanning
The series sequence correspondence of chain element is transmitted to the scan chain cell；
Scan disable signal is sent by the second signal line and maintains the scan disable signal, to forbid described sweep
Chain element is retouched to continue to identify and receive first preset signals；
The second preset signals are sent by the second signal line and test signal is sent by first signal wire.
In a kind of exemplary embodiment of the disclosure, first signal wire include data signal line, address signal line,
Control signal wire, the second signal line include scan enable signal line, synchronizing clock signals line, chip selection signal line, and described
Three signal wires include that secondary pieces select signal wire, and first preset signals include the first chip selection signal, second preset signals
Including the second chip selection signal.
In a kind of exemplary embodiment of the disclosure, it is described by the second signal line send scan enable signal and
Synchronizing clock signals, while the first preset signals of the position n are sent by the serial signal line and include:
The scan enable signal is sent by the scan enable signal line；
The synchronizing clock signals are sent by the synchronizing clock signals line, while being sent by the serial signal line
The first chip selection signal of the position n makes each described first chip selection signal according to the synchronizing clock signals by the scan chain cell
Series sequence correspondence be transmitted to the scan chain cell, and select signal wire to be transmitted to and each scanning via the secondary pieces
The corresponding test target of chain element.
It is described that second preset signals are sent simultaneously by the second signal line in a kind of exemplary embodiment of the disclosure
Sending test signal by first signal wire includes:
The second chip selection signal is sent by the chip selection signal line, is made and the enabled state position in first chip selection signal
Corresponding tested target is enabled；
It sent simultaneously by the control signal wire, the address signal line, the data signal line and writes control instruction, write
Address and write data.
It is enabled state when only having one in first chip selection signal in a kind of exemplary embodiment of the disclosure
When, it is described that second preset signals are sent by the second signal line and test signal packet is sent by first signal wire
It includes:
The second chip selection signal is sent by the chip selection signal line, is made and the enabled state position in first chip selection signal
Corresponding tested target is enabled；
It is sent simultaneously by the control signal wire, the address signal line and reads control instruction and read address, and pass through institute
Data signal line is stated to be read out the tested target being enabled.
The test equipment and test macro that the embodiment of the present disclosure provides correspond to tested target quantity by using digit
Serial signal is output to scan chain cell corresponding with tested target, so that each scan chain cell is stored and is exported and corresponds to
One tested target signal, can be by a pin to multiple tested target output signals, and effectively save test equipment is drawn
Foot.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of schematic diagram of tested target test scenes multiple in the related technology.
Fig. 2A and Fig. 2 B is the connection figure of test macro in the embodiment of the present disclosure.
Fig. 3 is the circuit diagram of scan chain cell in the embodiment of the present disclosure.
Fig. 4 is the control sequential figure of scan chain cell circuit shown in Fig. 3.
Fig. 5 is a kind of block diagram of test equipment in one exemplary embodiment of the disclosure.
Fig. 6 is the control sequential figure of test equipment shown in Fig. 5.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in any suitable manner in one or more embodiments.In the following description, it provides perhaps
More details fully understand embodiment of the present disclosure to provide.It will be appreciated, however, by one skilled in the art that can
It is omitted with technical solution of the disclosure one or more in the specific detail, or others side can be used
Method, constituent element, device, step etc..In other cases, be not shown in detail or describe known solution to avoid a presumptuous guest usurps the role of the host and
So that all aspects of this disclosure thicken.
In addition, attached drawing is only the schematic illustrations of the disclosure, identical appended drawing reference indicates same or similar portion in figure
Point, thus repetition thereof will be omitted.Some block diagrams shown in the drawings are functional entitys, not necessarily necessary and object
The entity managed or be logically independent is corresponding.These functional entitys can be realized using software form, or in one or more
These functional entitys are realized in hardware module or integrated circuit, or in heterogeneous networks and/or processor device and/or microcontroller
These functional entitys are realized in device.
Disclosure example embodiment is described in detail with reference to the accompanying drawing.
Fig. 2A and Fig. 2 B is the connection figure of test macro in the embodiment of the present disclosure.
With reference to Fig. 2A, in the embodiments of the present disclosure, test macro 200 may include:
Test equipment 1 has the first signal wire S1 and second signal line S2 and serial signal line SL；
N tested targets 2, are coupled to test equipment 1 by the first signal wire S1；
N concatenated scan chain cells 3, are coupled to test equipment 1 by second signal line S2, pass through n third respectively
Signal wire S3 couples n tested targets.
Wherein, first scan chain cell is coupled to the serial signal line SL of test equipment 1.
In Fig. 2A illustrated embodiment, the first signal wire S1 and second signal line S2 may each comprise a plurality of multiple types
Signal wire, third signal wire are used to carry out signal transmitting between tested target and its corresponding scan chain cell.
Fig. 2 B is one embodiment of test macro in Fig. 2A.
In fig. 2b, the first signal wire includes data signal line DQ, address signal line ADD, controls and believe CMD line, and second
Signal wire includes scan enable signal line SHIFT, synchronizing clock signals line SCK, chip selection signal line CS, and third signal wire includes time
Grade chip selection signal line CS_n.
Test equipment 1 has control signal wire CMD, address signal line ADD, data signal line DQ, chip selection signal line CS, same
Step clock signal line SCK, scan enable signal line SHIFT and serial signal line SL；
N tested targets 2 are coupled to test and are set by control signal wire CMD, address signal line ADD, data signal line DQ
Standby 1；
N concatenated scan chain cells 3 pass through chip selection signal line CS_n, synchronizing clock signals line SCK, scan enable signal
Line SHIFT is coupled to test equipment 1, selects the chip selection signal of signal wire CS_n n tested targets of coupling by n secondary pieces respectively
Line CS, scan chain cell couple the serial signal output end SO of previous scan chain cell by serial signal line input terminal SI.
In the embodiment shown in Fig. 2 B, all tested 2 shared control signals line CMD of target, address signal line ADD, number
According to signal wire DQ, practical piece selects state to select the output signal control of signal wire CS_n by secondary pieces by its corresponding scan chain cell
System.
The synchronizing clock signals line that all 3 sharing chips of scan chain cell select signal wire CS, control serial signal shift LD
SCK and scan enable signal line SHIFT, the serial signal input terminal of first scan chain cell are coupled to the string of test equipment
Row signal line SL.When scan enable signal line SHIFT is in enabled state, each scan chain cell 3 can be believed with synchronised clock
Number variation receive and store a data on serial signal input terminal SI, and a data stored before is transmitted to string
Row signal output end SO provides signal for the serial signal input terminal of next scan chain cell, finally exports test equipment 1
Serial signal each according to scan chain cell series sequence correspondence be transmitted to a scan chain cell.
Each scan chain cell can determine that piece selects shape by serial signal input terminal received signal together with chip selection signal
State, then select the output signal of signal wire CS_n to control practical of corresponding tested target by secondary pieces and select state.
By the above structure it is found that the tested target test macro that the embodiment of the present disclosure provides can be each by serial signal
The state of position controls the output signal of each scan chain cell, and then tests multiple tested targets, and energy using limited I/O pin
It realizes and one or more tested targets in multiple tested targets is individually tested.
Fig. 3 is a kind of circuit diagram of scan chain cell in Fig. 2 B illustrated embodiment.
With reference to Fig. 3, in some embodiments, each scan chain cell may include:
First gate 31, first input end are coupled to serial signal input terminal SI, and the second input terminal is coupled to serial letter
Number output end SO, control terminal are coupled to scan enable signal line SHIFT；
D type flip flop 32, input terminal D are coupled to the output end of the first gate 31, and output end is coupled to serial signal output
SO is held, control terminal is coupled to synchronizing clock signals line SCK；
Or door 33, first input end are coupled to scan enable signal line SHIFT, it is defeated that the second input terminal is coupled to serial signal
Outlet SO；
Second gate 34, first input end are coupled to chip selection signal line CS, and the second input terminal is set to high-impedance state, control
End is coupled to or the output end of door 33；
Driving element 35, input terminal are coupled to the output end of the second gate 34, and output end is coupled to secondary chip selection signal
Line CS_n, for increasing the power of output signal.
Fig. 4 is the control sequential figure of scan chain cell circuit shown in Fig. 3.
With reference to Fig. 3 and Fig. 4, in the embodiment shown in fig. 3, when scan enable signal line SHIFT input signal is 1
When or gate output terminal be 1, the second gate 34 export its first input end signal, secondary chip selection signal CS_n is equal at this time
The chip selection signal CS that test equipment is sent can be right if the chip selection signal CS that test equipment 1 is sent at this time is enabled state
All tested targets carry out write operation simultaneously.
At this point, 31 control output end signal of the first gate is equal to the signal of first input end, 32 input terminal of d type flip flop
Signal is equal to the signal of serial signal input terminal SI, i.e. the n-th of serial signal.When the control terminal of d type flip flop 32 receives together
When the rising edge signal of the synchronizing clock signals on step clock signal line SCK, the signal of input terminal is transmitted to output end and is gone here and there
Row signal line SL is simultaneously latched.Since serial signal line SL is coupled to the serial signal input terminal of next scan chain cell
N-th Bits Serial signal has been transferred to next scan chain cell so being equivalent to, made in next synchronizing clock signals by SI
When rising edge signal arrives, d type flip flop the n-th Bits Serial signal of latch of next scan chain cell, and the D of this scan chain cell
Flip/flops latch the (n+1)th Bits Serial signal.
When the digit of serial signal is identical as tested target quantity, export whole serial signals and it is corresponding synchronous when
After clock signal, the d type flip flop of concatenated scan chain cell can latch a bit serial signal.
When scan enable signal line SHIFT input signal is 0, it is defeated equal to second that the first gate 31 controls output signal
The signal i.e. signal of 32 output end of d type flip flop for entering end, when synchronizing clock signals arrive, d type flip flop 32 is constantly by output end
Signal latch is simultaneously output to output end, therefore or door state it is constant.
If 32 latch mode of d type flip flop of the scan chain cell is 1 at this time, or 33 output state of door is 1, the second choosing
Logical 34 output end signal of device is equal to chip selection signal, and secondary chip selection signal CS_n is equal to chip selection signal CS；If the scan chain cell
32 latch mode of d type flip flop be 0, then or 33 output state of door be 0,34 output end signal of the second gate be equal to high resistant shape
State does not export, then secondary chip selection signal CS_n is without (or being defaulted as 0).
Therefore, when test equipment 1 sends enable signal, the scan chain cell for being only latched with serial signal 1 is corresponding
Tested target is enabled (CS_n=1), that is, passes through the state of each of setting serial signal and the position pair of scan chain cell
It should be related to the independent piece choosing that may be implemented to be tested one or more target.
Fig. 5 schematically shows a kind of block diagram of test equipment in one exemplary embodiment of the disclosure.
With reference to Fig. 5, test equipment 1 may include:
First signal wire S1, second signal line S2 and serial signal line SL, the first signal wire S1 couple n tested targets
2, second signal line S2 is coupled to n scan chain cell 3, and n scan chain cell is respectively coupled to n quilt by third signal wire S3
Mark, wherein n scan chain cell 3 is connected, and first scan chain cell is coupled to serial signal line SL, each scan chain list
Member 3 includes d type flip flop and multiple selector；
Memory 11；And
The processor 12 of memory belonging to being coupled to, processor 12 are configured as based on instruction stored in memory,
Execute following control action:
Scan enable signal and synchronizing clock signals are sent by second signal line, while defeated by the serial signal line
The first preset signals of the position n out make series sequence of each first preset signals according to synchronizing clock signals by scan chain cell
Correspondence is transmitted to a scan chain cell；
Scan disable signal is sent by second signal line and maintains scan disable signal, to forbid scan chain cell to continue
The first preset signals of identification and reception；
The second preset signals are sent by second signal line and test signal is sent by the first signal wire.
Wherein, third signal wire both can be used for from scan chain cell to tested target transmit signal, can be used for by
Tested target transmits signal to scan chain cell.
When test equipment is as shown in Figure 2 B, processor be can also be performed as given an order:
Scan enable signal is sent by scan enable signal line；
Synchronizing clock signals are sent by synchronizing clock signals line, while the choosing of the position n first is sent by serial signal line
Signal makes each first chip selection signal be transmitted to one by the series sequence correspondence of scan chain cell according to synchronizing clock signals
Scan chain cell, and select signal wire to be transmitted to test target corresponding with each scan chain cell via secondary pieces；
Scan disable signal is sent by scan enable signal line and maintains scan disable signal, to forbid scan chain cell
Continue to identify and receive the first preset signals；
The second chip selection signal is sent by chip selection signal line, and passes through control signal wire, address signal line, data signal line
Send test signal.
Fig. 6 is the control sequential figure of test equipment shown in Fig. 5.
With reference to Fig. 6, T1 stage, scan enable signal is equal to 1, exports serial signal SI, each corresponds to a scan chain
Unit and a tested target.Each scan chain cell carries out shift LD to serial signal SI, in the control of synchronizing clock signals
Under each scan chain cell latch a Bits Serial signal respectively to control the piece of corresponding tested target and select state.In the process, by
It is equal to 1 in scan enable signal, the chip selection signal line CS of data and test equipment on the chip selection signal line CS of each tested target
Data are identical, are not influenced by serial signal latch in scan chain cell, tested target can be normally written at this time.
T2 stage, scan enable signal are equal to 0, and the piece that corresponding scan chain cell latches the tested target of 1 signal selects letter
Data on number line CS are identical as the chip selection signal line CS data of test equipment, and corresponding scan chain cell latches the quilt of 0 signal
No chip selection signal on the chip selection signal line CS of mark.When test equipment exports chip selection signal, only corresponding scan chain
The tested target of 1 signal of unit latches enters piece and selects state.In the above manner, test equipment can to multiple tested targets into
Row individually control.
In some embodiments, write-in while to multiple tested targets can be accomplished by the following way:
The second chip selection signal is sent by chip selection signal line CS, is made corresponding with the enabled state position in the first chip selection signal
Tested target is enabled；
It is sent simultaneously by control signal wire CMD, address signal line ADD, data signal line DQ and writes control instruction, write address
With write data.
Due to each tested target shared data signal wire DQ, each tested target can not be read simultaneously, therefore to read quilt
Mark, can only have the serial signal of an enabled state by setting to control one in multiple tested targets by mark
Select state into piece, and target is tested to this and is read out.
Being read to a tested target for example can be with are as follows:
The second chip selection signal is sent by chip selection signal line CS, is made corresponding with the enabled state position in the first chip selection signal
Tested target is enabled；
It is sent simultaneously by control signal wire CMD, address signal line ADD and reads control instruction and read address, and pass through data
Signal wire DQ tested target corresponding to the chip selection signal of enabled state is read out.
If you need to read each tested target, only the first different chip selection signal of enabled state position need to be exported every time and is carried out
Read operation.
The test equipment that the embodiment of the present disclosure provides can be by being written one of serial signal to each scan chain cell, can
Whether enter piece to control the corresponding tested target of scan chain cell when test equipment sends chip selection signal and select state, Jin Ertong
Crossing a serial signal line I/O interface can be thus achieved independent control to multiple tested targets, effectively save interface, be promoted
Testing efficiency.
It should be noted that although being referred to several modules or list for acting the equipment executed in the above detailed description
Member, but this division is not enforceable.In fact, according to embodiment of the present disclosure, it is above-described two or more
Module or the feature and function of unit can embody in a module or unit.Conversely, an above-described mould
The feature and function of block or unit can be to be embodied by multiple modules or unit with further division.
Person of ordinary skill in the field is it is understood that the various aspects of the utility model can be implemented as system, side
Method or program product.Therefore, the various aspects of the utility model can be with specific implementation is as follows, it may be assumed that complete hardware is real
The embodiment combined in terms of applying mode or hardware and software, may be collectively referred to as circuit, " module " or " system " here.
Through the above description of the embodiments, those skilled in the art is it can be readily appreciated that example described herein is implemented
Mode can also be realized by software realization in such a way that software is in conjunction with necessary hardware.
In addition, above-mentioned attached drawing is only schematically illustrating according to the utility model exemplary embodiment, rather than limit mesh
's.It can be readily appreciated that above-mentioned processing shown in the drawings does not indicate or limits the time sequencing of these processing.In addition, being also easy to manage
Solution, these processing, which can be, for example either synchronously or asynchronously to be executed in multiple modules.
Those skilled in the art will readily occur to the disclosure after considering specification and practicing utility model disclosed herein
Other embodiments.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications are used
Way or adaptive change follow the general principles of this disclosure and including the disclosure it is undocumented in the art known in
Common sense or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope of the disclosure and design are by weighing
Benefit requires to point out.
Claims (12)
1. a kind of test macro characterized by comprising
Test equipment has the first signal wire, second signal line and serial signal line；
N tested targets, are coupled to the test equipment by first signal wire；
N concatenated scan chain cells, are coupled to the test equipment by the second signal line, pass through third signal wire point
The n tested targets are not coupled, and first scan chain cell is coupled to the serial signal line.
2. test macro as described in claim 1, which is characterized in that the test equipment setting are as follows:
Scan enable signal and synchronizing clock signals are sent by the second signal line, while being sent out by the serial signal line
It send the position n the first preset signals, makes each described first preset signals according to the synchronizing clock signals by the scan chain list
The series sequence correspondence of member is transmitted to the scan chain cell；
Scan disable signal is sent by the second signal line and maintains the scan disable signal, to forbid the scan chain
Unit continues to identify and receive first preset signals；
The second preset signals are sent by the second signal line and test signal is sent by first signal wire.
3. such as the described in any item test macros of claims 1 or 2, which is characterized in that first signal wire includes data letter
Number line, address signal line, control signal wire, the second signal line includes scan enable signal line, synchronizing clock signals line, piece
Signal wire is selected, the third signal wire includes that secondary pieces select signal wire.
4. test macro as claimed in claim 3, which is characterized in that the scan chain cell includes:
First gate, first input end are coupled to serial signal input terminal, and the second input terminal is coupled to serial signal output end,
Control terminal is coupled to the scan enable signal line；
D type flip flop, input terminal are coupled to the output end of first gate, and output end is coupled to the serial signal output
End, control terminal are coupled to the synchronizing clock signals line；
Or door, first input end are coupled to the scan enable signal line, the second input terminal is coupled to the serial signal output
End；
Second gate, first input end are coupled to the chip selection signal line, and the second input terminal is set to high-impedance state, control terminal coupling
It is connected to described or door output end；
Driving element, input terminal are coupled to the output end of second gate, and output end is coupled to the secondary chip selection signal
Line.
5. test macro as claimed in claim 3, which is characterized in that the test equipment setting are as follows:
Scan enable signal is sent by the scan enable signal line；
The synchronizing clock signals are sent by the synchronizing clock signals line, while sending n by the serial signal line
First chip selection signal makes each string of first chip selection signal according to the synchronizing clock signals by the scan chain cell
Connection sequence correspondence is transmitted to the scan chain cell, and selects signal wire to be transmitted to and each scan chain list via the secondary pieces
The corresponding tested target of member；
Scan disable signal is sent by the scan enable signal line and maintains the scan disable signal；
The second chip selection signal is sent by the chip selection signal line, and passes through the control signal wire, the address signal line, institute
It states data signal line and sends test signal.
6. test macro as claimed in claim 5, which is characterized in that described to send second choosing by the chip selection signal line
Signal, and test signal is sent by the control signal wire, the address signal line, the data signal line and includes:
The second chip selection signal is sent by the chip selection signal line, is made corresponding with the enabled state position in first chip selection signal
Tested target be enabled；
It is sent simultaneously by the control signal wire, the address signal line, the data signal line and writes control instruction, write address
With write data.
7. test macro as claimed in claim 5, which is characterized in that when only one is enabled in first chip selection signal
It is described that second chip selection signal is sent by the chip selection signal line when state, and believed by the control signal wire, the address
Number line, the data signal line send test signal
The second chip selection signal is sent by the chip selection signal line, is made corresponding with the enabled state position in first chip selection signal
Tested target be enabled；
It is sent simultaneously by the control signal wire, the address signal line and reads control instruction and read address, and pass through the number
The tested target being enabled is read out according to signal wire.
8. a kind of test equipment characterized by comprising
First signal wire, second signal line and serial signal line, n tested targets of first signal wire coupling, described the
Binary signal line is coupled to n scan chain cell, and the n scan chain cell is respectively coupled to the n quilt by third signal wire
Mark, wherein the n scan chain cell is connected, first scan chain cell is coupled to the serial signal line, Mei Gesuo
Stating scan chain cell includes d type flip flop and multiple selector；
Memory；And
The processor of memory belonging to being coupled to, the processor is configured to the instruction based on storage in the memory,
Execute following control action:
Scan enable signal and synchronizing clock signals are sent by the second signal line, while being sent out by the serial signal line
It send the position n the first preset signals, makes each described first preset signals according to the synchronizing clock signals by the scan chain list
The series sequence correspondence of member is transmitted to the scan chain cell；
Scan disable signal is sent by the second signal line and maintains the scan disable signal, to forbid the scan chain
Unit continues to identify and receive first preset signals；
The second preset signals are sent by the second signal line and test signal is sent by first signal wire.
9. test equipment as claimed in claim 8, which is characterized in that first signal wire includes data signal line, address
Signal wire, control signal wire, the second signal line include scan enable signal line, synchronizing clock signals line, chip selection signal line,
The third signal wire includes that secondary pieces select signal wire, and first preset signals include the first chip selection signal, and described second is pre-
If signal includes the second chip selection signal.
10. test equipment as claimed in claim 9, which is characterized in that described to be made by second signal line transmission scanning
Energy signal and synchronizing clock signals, while the first preset signals of the position n are sent by the serial signal line and include:
The scan enable signal is sent by the scan enable signal line；
The synchronizing clock signals are sent by the synchronizing clock signals line, while sending n by the serial signal line
First chip selection signal makes each string of first chip selection signal according to the synchronizing clock signals by the scan chain cell
Connection sequence correspondence is transmitted to the scan chain cell, and selects signal wire to be transmitted to and each scan chain list via the secondary pieces
The corresponding test target of member.
11. the test equipment as described in claim 9 or 10, which is characterized in that described to send the by the second signal line
Two preset signals and by first signal wire send test signal include:
The second chip selection signal is sent by the chip selection signal line, is made corresponding with the enabled state position in first chip selection signal
Tested target be enabled；
It is sent simultaneously by the control signal wire, the address signal line, the data signal line and writes control instruction, write address
With write data.
12. the test equipment as described in claim 9 or 10, which is characterized in that when only one in first chip selection signal
It is described that second preset signals are sent by the second signal line and survey is sent by first signal wire when being enabled state
Trial signal includes:
The second chip selection signal is sent by the chip selection signal line, is made corresponding with the enabled state position in first chip selection signal
Tested target be enabled；
It is sent simultaneously by the control signal wire, the address signal line and reads control instruction and read address, and pass through the number
The tested target being enabled is read out according to signal wire.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821631055.2U CN209215538U (en) | 2018-09-28 | 2018-09-28 | Test equipment and test macro |
| PCT/CN2019/106359 WO2020063414A1 (en) | 2018-09-28 | 2019-09-18 | Test method and test system |
| US17/167,382 US11320484B2 (en) | 2018-09-28 | 2021-02-04 | Test method and test system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821631055.2U CN209215538U (en) | 2018-09-28 | 2018-09-28 | Test equipment and test macro |
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| CN209215538U true CN209215538U (en) | 2019-08-06 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270432A (en) * | 2018-09-28 | 2019-01-25 | 长鑫存储技术有限公司 | Test method and test macro |
| WO2020063414A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Test method and test system |
| WO2020063483A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip test method, apparatus, device, and system |
-
2018
- 2018-09-28 CN CN201821631055.2U patent/CN209215538U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109270432A (en) * | 2018-09-28 | 2019-01-25 | 长鑫存储技术有限公司 | Test method and test macro |
| WO2020063414A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Test method and test system |
| WO2020063483A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip test method, apparatus, device, and system |
| US11320484B2 (en) | 2018-09-28 | 2022-05-03 | Changxin Memory Technologies, Inc. | Test method and test system |
| US11536770B2 (en) | 2018-09-28 | 2022-12-27 | Changxin Memory Technologies, Inc. | Chip test method, apparatus, device, and system |
| CN109270432B (en) * | 2018-09-28 | 2024-03-26 | 长鑫存储技术有限公司 | Test method and test system |
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