CN108431788A - A kind of method of veneer, electronic equipment and gating - Google Patents

A kind of method of veneer, electronic equipment and gating Download PDF

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Publication number
CN108431788A
CN108431788A CN201680076002.6A CN201680076002A CN108431788A CN 108431788 A CN108431788 A CN 108431788A CN 201680076002 A CN201680076002 A CN 201680076002A CN 108431788 A CN108431788 A CN 108431788A
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pin
jtag
module
channel
veneer
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CN108431788B (en
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刘翔
师军令
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention provides a kind of method of veneer, electronic equipment and gating, the veneer includes：JTAG's JTAG modules (11), memory module (14), channel selecting module (12) and memory interface (13)；The channel selecting module (12) is electrically connected with the JTAG modules (11), the channel selecting module (12) is electrically connected with the memory interface (13), the memory module (14), the channel selecting module (12) are electrically connected with the memory module (14)；The channel selecting module (12), for when jtag test equipment is electrically connected with the memory interface (13), being connected to the memory interface (13) and the JTAG modules (11)；And when storage device is electrically connected with the memory interface (13), it is connected to the memory interface (13) and the memory module (14).The efficiency of later stage jtag test, the integrated level of electronic equipment and aesthetics can be improved.

Description

A kind of method of veneer, electronic equipment and gating Technical field
The present invention relates to a kind of methods of electronic technology field more particularly to veneer, electronic equipment and gating.
Background technique
At present, electronic equipment is increasingly intelligent, miniaturization and high integration direction are developed, each functional interface of electronic equipment internal is also more and more, for convenience of the later period to the fault diagnosis of electronic equipment and debugging etc., the functional interface of corresponding inner function circuit is drawn generally outside electronic equipment, as Figure 1-1, joint test working group (JTAG in main control chip, Joint Test Action Group) circuit and safety digital storage card (SD, Secure Digital Memory Card) internal circuit independence, respectively jtag circuit and SD internal circuit draw independent jtag interface and SD interface, the jtag interface and SD interface that tester is drawn by the two, external jtag test can be connected Equipment and SD equipment, and tested accordingly, the operation such as read/write.Since the circuit board of current electronic equipment is typically small, and external interface is compact to design, therefore to improve portable degree and aesthetics, electronic equipment internal will not be generally used to test, debug etc. and drawn outside functional interfaces, so that making troubles in the fault diagnosis of later period electronic equipment and debugging, need to dismantle the shell of electronic equipment in fault diagnosis or debugging, the fly line on electronic equipment internal circuit board, diagnosis efficiency or debugging efficiency are lower, and are easy to damage shell and circuit board etc..
It is general that other function is realized using the existing interface drawn outside multiplexing electronic equipment in current mechanism, it realizes under the premise of not adding additional interface, also can increase the function of electronic equipment, and improve the integrated level of electronic equipment.As shown in Figs. 1-2, input/output (the I/O of main control chip is multiplexed inside main control chip, Input/Output) interface, the function of jtag interface is realized by multiplexing SD interface, when carrying out jtag test, it needs to connect SD interface and jtag test equipment using dedicated pinboard, tester passes through the debugging software in jtag test equipment, specific instruction is sent to main control chip by dedicated pinboard, master control chip is set to identify jtag test equipment, to realize the switching between JTAG function and SD function.SD function and JTAG function are realized by then passing through the I/O interface of multiplexing main control chip, therefore function switch only could be completed when main control chip works normally, and it also requires dedicated pinboard and Special debugging software, are just able to achieve the switching of SD function and JTAG function.And when main control chip can not work normally, Wu Fajin Row jtag test can not carry out jtag test for the chip monomer of jtag circuit.
Summary of the invention
This application provides a kind of method of veneer, electronic equipment and jtag test, it is able to solve the problem that jtag test efficiency is lower in the prior art.
The application first aspect provides a kind of veneer, and the veneer includes:
JTAG's JTAG module, memory module, channel selecting module and memory interface；
The channel selecting module is electrically connected with the JTAG module, and the channel selecting module is electrically connected with the memory interface, and the channel selecting module is electrically connected with the memory module；
The channel selecting module, for being connected to the memory interface and the JTAG module when jtag test equipment is electrically connected with the memory interface；
And when storage equipment is electrically connected with the memory interface, it is connected to the memory interface and the memory module.It is multiplexed memory interface by the channel selecting module, realization switches between JTAG mode and memory module.The memory interface is SD interface.
In some possible designs, the channel selecting module, it is also used to be connected to the memory interface and the JTAG module, i.e., when the described jtag test equipment and the JTAG module form access, the JTAG module will be inputted from the jtag test signal of the jtag test equipment；
The first test data that test obtains for executing the corresponding test item of the jtag test signal according to the jtag test signal received from the channel selecting module, and is transmitted to the channel selecting module by the JTAG module；
The channel selecting module is also used to first test data from the JTAG module being transmitted to the jtag test equipment by the memory interface.After being communicated to the JTAG module on veneer by channel selecting module multiplexing memory interface, the output of jtag test function and test data is realized.
In some possible designs, the channel selecting module, it is also used to be connected to the memory interface and the memory module, i.e., when the described storage equipment and the memory module form access, the storage test signal from the storage equipment is exported to the memory module；
The memory module executes the corresponding test item of the storage test signal, and the second test data that test obtains is exported to the channel selecting module for testing signal according to the storage received from the channel selecting module；
The channel selecting module is also used to second test data from the memory module being transmitted to the storage equipment by the memory interface.After the memory module being communicated on veneer by channel selecting module selection, the functions such as storage, reading data, input and output are realized.
In some possible designs, the channel selecting module includes the first gated end, second gated end, common end and gating control pin, first gated end is electrically connected with the interface end of the JTAG module, second gated end is electrically connected with the interface end of the memory module, and the common end is electrically connected with the memory interface.Optionally, the channel selecting module includes multidiameter option switch, wherein, multidiameter option switch is the analog switch for realizing gating function, may include multiplexer, multiple selector, multiway analog switch, data selector, multi-channel analog converter, multiplexer switch, multi-channel switch, variable connector etc..
In some possible designs, the channel selecting module further includes gating control pin, and the gating control pin is connect for controlling the common end with first gated end, and the control common end and second gated end communicate to connect.
In some possible designs, the interface end of the JTAG module includes: that test pattern selection pin, test clock pin, test data input pin and test data output pin can also include optionally test reset pin；
First gated end includes: and the test pattern selection corresponding first passage pin of the pin and corresponding second channel pin of the test clock pin and corresponding third channel pin of the test data input pin and fourth lane pin corresponding with the test data output pin, correspondingly, can also include Five-channel pin corresponding with the test reset pin；
When the signal for inputting the gating control pin is the first level, the first passage pin, the second channel pin, the third channel pin and fourth lane pin gating in the channel selecting module, optionally, when gating control pin includes Five-channel pin, the Five-channel pin is also gated.The pin being electrically connected with JTAG module is gated by the way that gating control pin is arranged in channel selecting module, realizes signal transmission.
In some possible designs, the interface end of the memory module includes: command pin, clock pins, the first test data pins, the second test data pins, third test data pins and the 4th test data pins；
Second gated end includes: the 6th channel pin corresponding with described instruction pin and the clock The corresponding 7th channel pin of pin and the corresponding 8th channel pin of first test data pins and the corresponding 9th channel pin of the second test data pins and corresponding tenth channel pin of the third test data pins and the 11st channel pin corresponding with the 4th test data pins；
The 6th channel pin, the 7th channel pin, the 8th channel pin, the 9th channel pin, the tenth channel pin and the 11st channel pin gating when signal for inputting the gating control pin is second electrical level, in the channel selecting module.
In some possible designs, the memory interface includes that storage equipment detects pin, and the storage equipment detection pin is electrically connected with gating control pin；
The storage equipment detects pin, for when jtag test equipment is electrically connected with the memory interface, the signal of the triggering input gating control pin to be first level；When storage equipment is electrically connected with the memory interface, the signal of the triggering input gating control pin is the second electrical level.Pin, which is detected, by the storage equipment in memory module triggers corresponding level signal to gating control pin, so that gating control pin gates the corresponding pin of equipment of corresponding insertion memory interface according to the level height of signal.
Second aspect of the present invention provides a kind of electronic equipment, and the electronic equipment includes any veneer in each possible design of above-mentioned first aspect and first aspect.
Third aspect present invention provides a kind of method of gating, and the method is applied to veneer, which comprises
When JTAG's jtag test equipment is electrically connected with the memory interface in the veneer, the channel selecting module in the veneer is connected to the JTAG module in the memory interface and the veneer；
When storage equipment is electrically connected with the memory interface in the veneer, the channel selecting module is connected to the memory module in the memory interface and the veneer.
In a kind of possible design, channel selecting module includes the first gated end, second gated end, common end and gating control pin, first gated end is electrically connected with the interface end of JTAG module, second gated end is electrically connected with the interface end of the memory module, and the common end is electrically connected with the memory interface in the veneer；The memory interface includes that storage equipment detects pin, and the storage equipment detection pin is electrically connected with gating control pin；
It is described to be electrically connected in JTAG's jtag test equipment with the memory interface in the veneer When, the channel selecting module in the veneer is connected to the memory interface with the JTAG module in the veneer and includes:
It is described when the jtag test equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is the first level, the gating control pin gates first gated end, so that the jtag test equipment and the JTAG module communicate to connect；
It is described when storing equipment and being electrically connected with the memory interface in the veneer, the channel selecting module is connected to the memory module in the memory interface and the veneer, comprising:
It is described when the storage equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is second electrical level, the gating control pin gates second gated end, so that the storage equipment and the memory module communicate to connect；The second electrical level is different from first level.
In the embodiment of the present invention, JTAG module and memory interface are electrically connected by using channel selecting module, so that when jtag test equipment is electrically connected with the memory interface, access is formed with the JTAG module, to realize that being multiplexed the memory interface carries out jtag test, it realizes under the premise of being not necessarily to external pinboard, Special debugging software, not tearing machine open and do not reduce the integrated level of veneer, it is multiplexed memory interface and carries out jtag test, jtag test operation and testing appliance are effectively reduced, the efficiency of later period jtag test, the integrated level of electronic equipment and aesthetics can be also improved.
Detailed description of the invention
Fig. 1-1 is a kind of structural schematic diagram of jtag test system in current mechanism；
Fig. 1-2 is another structural schematic diagram of jtag test system in current mechanism；
Fig. 2 is the structural schematic diagram of veneer in the embodiment of the present invention；
Fig. 2-1 is the structural schematic diagram of jtag test system in the embodiment of the present invention；
Fig. 3 is the logic circuit schematic diagram of veneer in the embodiment of the present invention；
Fig. 4 is the circuit theory schematic diagram of veneer in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram figure of electronic equipment in the embodiment of the present invention；
Fig. 6 is the flow diagram of the method for jtag test in the embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear Chu is fully described by; obviously; described embodiments are only a part of the embodiments of the present invention; instead of all the embodiments; based on the embodiments of the present invention; those skilled in the art's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Description and claims of this specification and term " first " in above-mentioned attached drawing, " second " etc. are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that the data used in this way are interchangeable under appropriate circumstances, so that the embodiments described herein can be implemented with the sequence other than the content for illustrating or describing herein.Furthermore, term " includes " and " having " and their any deformation, it is intended to cover and non-exclusive includes, such as, contain the process of series of steps or module, method, system, product or equipment those of are not necessarily limited to be clearly listed step or module, but may include be not clearly listed or for these processes, method, the other steps or module of product or equipment inherently, the division of module appeared in this paper, a kind of only division in logic, there may be another division manner when realizing in practical application, such as multiple modules can be combined into or be integrated in another system, or some features can be ignored, or it does not execute, in addition, shown or discussion mutual coupling, direct-coupling or communication connection can be through some interfaces, INDIRECT COUPLING or communication link between module It connects and can be electrical or other similar form, be not construed as limiting herein.And, module or submodule can be the separation that may not be physically as illustrated by the separation member, it can be and may not be physical module, or can divide less than in multiple circuit modules, some or all of modules can be selected to realize the purpose of the embodiment of the present invention according to the actual needs.
The embodiment of the invention provides a kind of methods of veneer, electronic equipment and jtag test, are used for electronic technology field, can be improved jtag test efficiency.Term herein is described in detail below.
JTAG module herein is properly termed as jtag circuit, memory module is properly termed as SD module or SD circuit or memory chip etc..As shown in Figure 3, JTAG module is equipped with the jtag interface being electrically connected with channel selecting module, the general jtag interface includes 4 pins: test pattern selects (TMS, Test Module Select), test clock (TCK, Test Clock), test data input (TDI, Test Data Input), test data output (TDO, Test Data Output), can also include test reset (TRST, Test Reset).SD module is equipped with the SD interface being electrically connected with channel selecting module, which includes 6 pins: instruction (CMD, Command), clock (CLK, Clock), data (DATA0, DATA1, DATA2 and DATA3).Correspondingly, channel selecting module is equipped with 5 with jtag interface A corresponding 5 channel pins of pin, and equipped with the corresponding 6 channel pins of 6 pins with SD interface.
Chip with jtag interface includes microprocessor (MPU, Microprocessor Unit), microcontroller (MCU, Microprogrammed Control Unit), central processing unit (CPU, Central Processing Unit), digital signal processor (DSP, Digital Signal Processor), Complex Programmable Logic Devices (CPLD, Complex Programmable Logic Device), field programmable gate array (FPGA, Field Programmable Gate Array) or other meet electrically With the chip of Electronic Engineering Association (IEEE, Institute of Electrical and Electronics Engineers) 1149.1 standards.
Jtag test herein includes JTAG debugging, jtag boundary scanning and JTAG vector emulation testing.Jtag test is mainly used for testing the electrical characteristic and debugging of chip, such as electronic equipment is in the fault detection of production process and the fault detection for the electronic equipment reprocessed, for a user, electronic equipment only needs to draw memory interface, so that user carries out the functions such as reading data, data edition, data input and data output to the memory module built in electronic equipment by the memory interface.
Wherein, JTAG debugging, which refers to, carries out online programming (ISP, In-System Programmable) to fixed device on circuit boards, such as is programmed to devices such as camera (Camera), flash memories (FLASH).
Jtag boundary scanning refers to that the attachment process for the component on circuit board, welded condition etc. carry out hardware failure detection.
JTAG vector emulation testing refers to the observation control of the working condition of the test and each functional module for each functional module in main control chip, for example, the input/output signal by chip tests chip monomer.
Electronic equipment herein mainly has the characteristics that at least one: small-sized, jtag interface, not easy-to-dismount electronic equipment, SD interface and jtag interface multiplexing for not drawing individually etc..
In current mechanism, under the premise of pursuing electronics miniaturization, special external pinboard or Special debugging software etc. is needed to be multiplexed existing SD interface when carrying out jtag test to electronic equipment, and in main control chip failure, it can not carry out jtag test, to solve this technical problem, the present invention provides following scheme:
1, using the main control chip and memory interface inside channel selecting module connecting single board.
Wherein, main control chip includes JTAG module and memory module, and channel selecting module is electrically connected with JTAG module and memory module respectively.
2, when jtag test equipment is connect with memory interface, channel selecting module is connected to the JTAG module in master chip, so that JTAG module, channel selecting module, memory interface and jtag test equipment form access, it is implemented without under the premise of jtag interface is set for JTAG module and does not tear machine open, it is multiplexed existing memory interface, the function of jtag test can be realized.In addition, also not needing the existing memory interface of external pinboard or Special debugging software etc. i.e. reusable, operating procedure and testing appliance are reduced, the integrated level of electronic equipment is improved.
Referring to figure 2. with Fig. 2-1, a kind of veneer 1 is provided for the present invention, the veneer 1 includes:
JTAG's JTAG module 11, channel selecting module 12 and memory interface 13；
The channel selecting module 12 is electrically connected with the JTAG module 11, and the channel selecting module 12 is electrically connected with the memory interface 13；
The channel selecting module 12 makes jtag test equipment and the JTAG module 11 form access for being connected to the memory interface and the JTAG module when jtag test equipment is electrically connected with the memory interface 13.Optionally, due to all built-in storage circuit of current electronic equipment mostly, then a memory interface 13 is drawn outside the shell of opposing electronic device, so that user carries out the operation such as read/write by storage equipment of the built-in storage circuit to access memory interface 13, in the case where above-mentioned Fig. 2 realizes that being multiplexed existing memory interface realizes jtag test, when without jtag test, user still can be used normally above-mentioned memory interface 13 and carry out operation related with memory by the storage circuit built in electronic equipment.The i.e. described veneer 1 further includes memory module 14, and the channel selecting module 12 is for being electrically connected storage equipment with the memory module 14；
The channel selecting module 12 is also used to make to store equipment and the memory module 14 forms access when storage equipment is electrically connected with the memory interface 13.It is multiplexed memory interface 13 by the channel selecting module 12, realization switches between jtag test mode and memory module.The storage equipment can be the equipment for testing the memory module, be also possible to the memory with single store function, specifically not affected fixed.
It is understood that above-mentioned memory interface 13 is communicated for the JTAG module 11 with the jtag test equipment for accessing the memory interface 13 and the memory module 14 is communicated with the storage equipment for accessing the memory interface 13.For example, user described in 11 pairs of JTAG module accesses by depositing The jtag test equipment for storing up interface 13 carries out the functions such as jtag test, and carries out the operation such as read/write by the storage equipment of 14 pairs of the memory module access memory interfaces 13.Above-mentioned memory interface is the existing memory interface for carrying out the functions such as read/write by the storage equipment of 14 pairs of the memory module access memory interfaces 13 for realizing user, such as SD interface.
In the embodiment of the present invention, JTAG module 11 and memory interface 13 are connected by using channel selecting module 12, so that when jtag test equipment is electrically connected with the memory interface 13, access is formed with the JTAG module 11, to realize that being multiplexed the memory interface 13 carries out jtag test, it realizes and is being not necessarily to external pinboard, Special debugging software, under the premise of not tearing machine open and not reducing the integrated level of veneer 1, it is multiplexed memory interface 13 and carries out jtag test, effectively reduce jtag test operation and testing appliance, also the efficiency of later period jtag test can be improved, the integrated level and aesthetics of electronic equipment.
Optionally, in some inventive embodiments, when later period tester needs to carry out jtag test to electronic equipment, tester only needs jtag test equipment being inserted into memory interface 13, it can realize the multiplexing memory interface 13, the JTAG module 11 in jtag test equipment and veneer is set to form access by channel selecting module 12, to start jtag test mode, tester can carry out jtag test by jtag test equipment.After specific starting jtag test mode, the signal flow of each module of electronic equipment is as follows:
The channel selecting module 12 is also used to be connected to the memory interface 13 and the JTAG module 11, i.e., when jtag test equipment and the JTAG module 11 form access, will input the JTAG module 11 from the jtag test signal of the jtag test equipment；
The first test data that test obtains for executing the corresponding test item of the jtag test signal according to the jtag test signal received from the channel selecting module 12, and is transmitted to the channel selecting module 12 by the JTAG module 11；
The channel selecting module 12 is also used to first test data from the JTAG module being transmitted to the jtag test equipment by the memory interface 13.After being communicated to the JTAG module 11 on veneer by the channel selecting module 12 multiplexing memory interface, realize jtag test function, by carrying out jtag boundary sweep test to the important electronic device on veneer 1, it can quickly confirm failure relevant to electronic device, improve the efficiency of maintenance analysis；Alternatively, can determine the chip of failure according to the working condition of chip by carrying out the emulation testing of JTAG vector to the important electronic device on veneer 1, event is improved Hinder the efficiency of analysis；Alternatively, corresponding program can also be written, effectively improve the processing progress of veneer 1 by carrying out online programming simultaneously to multiple function elements on assembled veneer 1.
Optionally, in some inventive embodiments, after tester carries out jtag test to electronic equipment, storage equipment can also be inserted into memory interface 13 by tester；Or storage equipment is directly inserted into memory interface 13 by tester, access can be formed by the memory module 13 in channel selecting module 12 and veneer, to start memory module or storage test pattern, tester can carry out the operation such as read/write, test to the storage equipment of connection.
1, after starting storage test pattern, each module by signal flow direction of electronic equipment is as follows:
The channel selecting module 12 is also used to be connected to the memory interface 13 and the memory module 14, i.e., when storage equipment and the memory module 14 form access, the storage test signal from the storage equipment is exported to the memory module 14；
The memory module 14 executes the corresponding test item of the storage test signal, and the second test data that test obtains is exported to the channel selecting module 12 for testing signal according to the storage received from the channel selecting module 12；
The channel selecting module 12 is also used to second test data from the memory module 14 being transmitted to the storage equipment by the memory interface 13.After the memory module 14 being communicated on veneer by the channel selecting module 12 selection, storage test is realized.
2, after starting memory module, each module by signal flow direction of electronic equipment is as follows:
The channel selecting module 12 is also used to be connected to the memory interface 13 and the memory module 14, i.e., when storage equipment and the memory module 14 form access, the binary signal sent from the storage equipment is exported to the memory module 14；
The memory module 14, for executing the operation of input/output data, the process of specific input/output data is similar with current mechanism, does not repeat herein according to the binary signal received from the channel selecting module 12.In input data, the memory module 14 stores the data from the storage equipment；In output data, 14 output data of memory module will input the channel selecting module 12；
The channel selecting module 12 is also used to the output data from the memory module 14 being transmitted to the storage equipment by the memory interface 13.After the memory module 14 being communicated on veneer by the channel selecting module 12 selection, the functions such as reading data, input, output are realized.
Optionally, such as Fig. 2-1, the channel selecting module 12 herein includes the first gated end 121, second gated end 122 and common end 123, first gated end 121 is electrically connected with the interface end of the JTAG module 11, second gated end 122 is electrically connected with the interface end of the memory module 14, and the common end 123 is electrically connected with the memory interface 13.The channel selecting module 12 can be multidiameter option switch, multidiameter option switch includes gated end, common end etc., as shown in Tu3 &4, first gated end includes NO1-NO6, second gated end includes NC1-NC6, common end includes COM1-COM6, first gated end of the multidiameter option switch is electrically connected with the interface end of the JTAG module 11, and the second gated end of the multidiameter option switch is electrically connected with the interface end of the memory module 14.Optionally, multidiameter option switch is the analog switch for realizing gating function, it may include multiplexer, multiple selector, multiway analog switch, data selector, multi-channel analog converter, multiplexer switch, multi-channel switch, variable connector etc., the multiway analog switch of model TS3A27518E can be used for example.
For example, JTAG module 11 and memory interface 13 are connected about by multidiameter option switch, or it is as shown in Figure 3 by the internal logic circuit that multidiameter option switch connects memory module 14 and memory interface 13, for the gating function for realizing multidiameter option switch, the embodiment of the present invention further includes gating control pin in multidiameter option switch, the gating control pin is used to control the communication connection of common end Yu first gated end, it is connected to the memory interface 13 and the JTAG module 11, with the communication connection for controlling the common end and second gated end, it is connected to the memory interface 13 and the memory module 14.When practical application, such as, the switching of multidiameter option switch control communication connection can be used, the setting gating control pin IN i.e. in the multidiameter option switch, the gating control pin IN is connected to for controlling the common end with first gated end, that is the communication connection of memory interface 13 and the JTAG module 11, and the control common end are connected to the second gated end, i.e. the communication connection of memory interface 13 and the memory module 14.I.e. by the way that gating control pin IN is arranged in multidiameter option switch, it can be realized when jtag test equipment is electrically connected with memory interface 13, gate the pin being electrically connected with JTAG module 11, to realize that signal transmits.
Optionally, the gating control pin IN is for realizing the function of controlling the multidiameter option switch gating control pin, therefore gating control pin IN can also be with forbidding the replacement such as end, enable end, control signal end, as long as can be realized the low and high level by inputting the gating control pin IN to control the gating of pin, concrete type is not construed as limiting.
Optionally, the number of above-mentioned gating control pin IN can be one or more, specifically can basis The model of chip and the design alternative of veneer, such as, the same gating control pin IN can be used to switch between jtag test mode and memory module, also wherein several pins that JTAG module or memory module are corresponded on a gating control pin IN1 control multidiameter option switch can be used, simultaneously using the gating for other pins for corresponding to JTAG module or memory module on gating control pin IN2 control multidiameter option switch, the quantity of specific gating control pin is not construed as limiting herein, as shown in Figure 3 and Figure 4 controls the logical circuitry that gating controls pin for using IN1 and IN2, i.e. above-mentioned gating control pin IN includes the first gating gating control of control pin IN1 and second pin IN2, wherein, first gating control pin IN1, for controlling CO M1 pin is connected to the NC1 pin, or connection NO1 pin, and control COM2 pin is connected to the NC2 pin, or connection NO2 pin, and COM3 pin is connected to the NC3 pin, or connection NO3 pin；Second gating control pin IN2 is connected to the NC4 pin, or connection NO4 pin for controlling COM4 pin, and control COM5 pin is connected to the NC5 pin, or connection NO5 pin, COM6 pin are connected to the NC6 pin.
Connection relationship in Fig. 3 between each device is described as follows:
One, for JTAG module:
The interface end of the JTAG module 11 includes: test pattern selection TMS pin, test clock TCK pin, test data inputs TDI pin, test data output TDO pin can also include optionally test reset TRST pin；
First gated end of the multidiameter option switch includes: and the test pattern selection corresponding first passage NO1 pin of TMS pin and the corresponding second channel NO2 pin of the test clock TCK pin and the test data input the corresponding third channel NO3 pin of TDI pin, TDO pin is exported with the test data corresponding fourth lane NO4 pin, optionally, Five-channel NO5 pin corresponding with the test reset TRST pin can also be set.
Wherein, TMS pin is electrically connected with first passage NO1 pin, TCK pin is electrically connected with second channel NO2 pin, TDI pin is electrically connected with third channel NO3 pin, TDO pin is electrically connected with fourth lane NO4 pin and TRST pin is electrically connected with Five-channel NO5 pin.
Two, for memory module:
The interface end of the memory module 14 includes: instruction CMD pin, clock CLK pin, the first test data DATA0 pin, the second test data DATA1 pin, third test data DATA2 pin and the 4th test data DATA3 pin；
Second gated end of the multidiameter option switch includes: the 6th channel NC1 pin corresponding with the CMD pin, the 7th channel NC2 pin corresponding with the clock pins, the 8th channel NC3 pin corresponding with the first test data DATA0 pin, the 9th channel NC4 pin corresponding with the second test data DATA1 pin, the tenth channel NC5 pin corresponding with the third test data DATA2 pin, and the 11st channel NC6 pin corresponding with the 4th test data DATA3 pin.
Wherein, CMD pin is electrically connected with the 6th channel NC1 pin, CLK pin is electrically connected with the 7th channel NC2 pin, the first test data DATA0 pin is electrically connected with the 8th channel NC3 pin, the second test data DATA1 pin is electrically connected with the 9th channel NC4 pin, third test data DATA2 pin is electrically connected with the tenth channel NC5 pin and the 4th test data DATA3 pin is electrically connected with the tenth channel NC5 pin.
For example, for realizing that the gating control pin IN controls the gating of pin in the multidiameter option switch, the signal for inputting the gating control pin IN can be defined to realize control, specifically:
The memory interface 13 includes that storage equipment detects pin (SD-DET, Storage Card-Detector) 131, and the storage equipment detection pin 131 is electrically connected with gating control pin IN, as shown in Fig. 2-1 and Fig. 4；
The storage equipment detects pin 131, for when jtag test equipment is electrically connected with the memory interface 13, the signal of the triggering input gating control pin IN to be the first level；When storage equipment is electrically connected with the memory interface 13, the signal of the triggering input gating control pin IN is second electrical level.Pin 131 is detected by the storage equipment on memory interface 13, corresponding low and high level signal is triggered to gating control pin IN, so that gating control pin IN gates the corresponding pin of equipment of corresponding insertion memory interface 13 according to the level height of signal according to the device type of access memory interface 13.Wherein, the second electrical level is different from first level, such as it is high level (H, High Level) that the first level, which can be set, and the second electrical level is low level (L, Low Level), and specific value is not construed as limiting herein.
For example, when the signal of the storage equipment detection triggering input of the pin 131 gating control pin IN is high level H/ low level L, as shown in Figure 3 and Table 1, there are mainly two types of for the case where gating control pin IN gates the multidiameter option switch:
A, the first passage pin NO1, the second channel pin NO2, the third when signal for inputting gating control pin IN (including IN1 and IN2) is H, in the multidiameter option switch Channel pin NO3, the fourth lane pin NO4 and Five-channel pin NO5 gating；
B, the 6th channel pin NC1, the 7th channel pin NC2, the 8th channel pin NC3, the 9th channel pin NC4, the tenth channel pin NC5 and the 11st channel pin NC6 gating when signal for inputting gating control pin IN (including IN1 and IN2) is L, in the multidiameter option switch.
Table 1
Refering to Fig. 5, the present invention also provides a kind of electronic equipment 2, the electronic equipment 2 includes any veneer 1 in above-mentioned Fig. 2-4.
The structure of a kind of veneer 1 and a kind of electronic equipment 2 is described in detail above, is illustrated below with the gating that jtag test equipment carries out access to above-mentioned veneer 1 or above-mentioned electronic equipment 2, refering to Fig. 6, the embodiment of the present invention includes:
101, when JTAG's jtag test equipment is electrically connected with the memory interface in the veneer, the channel selecting module in the veneer is connected to the JTAG module in the memory interface and the veneer；
102, when storage equipment is electrically connected with the memory interface in the veneer, the channel selecting module is connected to the memory module in the memory interface and the veneer.
Since the channel selecting module includes the first gated end, the second gated end, common end and gating control Pin, first gated end are electrically connected with the interface end of JTAG module, and second gated end is electrically connected with the interface end of the memory module, and the common end is electrically connected with the memory interface in the veneer；The memory interface includes that storage equipment detects pin, and the storage equipment detection pin is electrically connected with gating control pin.Then it is specific as follows to gate the case where JTAG module or memory module for the channel gating module:
1, when jtag test equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is the first level, the gating control pin gates first gated end, so that the jtag test equipment and the JTAG module communicate to connect.
2, when the storage equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is second electrical level, the gating control pin gates second gated end, so that the storage equipment and the memory module communicate to connect.
Wherein, the second electrical level is different from first level, when the signal for realizing input gating control pin is different particular level, gates corresponding gated end, realizes multiplexing memory interface.
In the embodiment of the present invention, it is electrically connected by jtag test equipment with the memory interface, the channel selecting module is connected to the memory interface and the JTAG module, so that jtag test equipment is communicated by both memory interface and channel selecting module with JTAG module；When storage equipment is electrically connected with the memory interface, the channel selecting module is connected to the memory interface and the memory module, it realizes under the premise of being not necessarily to external pinboard, Special debugging software, not tearing machine open and do not reduce the integrated level of veneer, it is multiplexed existing memory interface and carries out jtag test and function switch, jtag test operation and testing appliance are effectively reduced, the efficiency of later period jtag test, the integrated level of electronic equipment and aesthetics can be also improved.
The present invention also provides a kind of computer storage medium, which has program, which includes some or all of step in the method for above-mentioned gating when executing.
The present invention also provides a kind of computer storage medium, which has program, which includes above-mentioned veneer when executing or electronic equipment executes some or all of step in a kind of method of gating.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the part being described in detail in some embodiment, reference can be made to the related descriptions of other embodiments.
It is apparent to those skilled in the art that for convenience and simplicity of description, the specific work process of the system, apparatus, and unit of foregoing description can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method may be implemented in other ways.Such as, the apparatus embodiments described above are merely exemplary, such as, the division of the unit, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed mutual coupling, direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of device or unit, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, and component shown as a unit may or may not be physical unit, it can and it is in one place, or may be distributed over multiple network units.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
In addition, the functional units in various embodiments of the present invention may be integrated into one processing unit, it is also possible to each unit and physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated unit both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product, can store in a computer readable storage medium.Based on this understanding, substantially all or part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products technical solution of the present invention in other words, the computer software product is stored in a storage medium, it uses including some instructions so that a computer equipment (can be personal computer, server or the network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), the various media that can store program code such as magnetic or disk.
The method of a kind of veneer provided by the present invention, electronic equipment and gating is described in detail above, used herein a specific example illustrates the principle and implementation of the invention, and the above description of the embodiment is only used to help understand the method for the present invention and its core ideas；At the same time, for those skilled in the art has change according to the thought of the present invention in specific embodiments and applications Place, in conclusion the contents of this specification are not to be construed as limiting the invention.

Claims (9)

  1. A kind of veneer, which is characterized in that the veneer includes:
    JTAG's JTAG module, memory module, channel selecting module and memory interface；
    The channel selecting module is electrically connected with the JTAG module, and the channel selecting module is electrically connected with the memory interface, and the channel selecting module is electrically connected with the memory module；
    The channel selecting module, for being connected to the memory interface and the JTAG module when jtag test equipment is electrically connected with the memory interface；
    And when storage equipment is electrically connected with the memory interface, it is connected to the memory interface and the memory module.
  2. Veneer according to claim 1, it is characterized in that, the channel selecting module includes the first gated end, second gated end, common end and gating control pin, first gated end is electrically connected with the interface end of the JTAG module, and second gated end is electrically connected with the interface end of the memory module, and the common end is electrically connected with the memory interface.
    The gating control pin is connect for controlling the common end with first gated end, and the control common end and second gated end communicate to connect.
  3. Veneer according to claim 2, which is characterized in that
    The interface end of the JTAG module includes: test pattern selection pin, test clock pin, test data input pin and test data output pin；
    First gated end includes: and the test pattern selection corresponding first passage pin of the pin and corresponding second channel pin of the test clock pin and corresponding third channel pin of the test data input pin and fourth lane pin corresponding with the test data output pin；
    The first passage pin, the second channel pin, the third channel pin and the fourth lane pin gating when signal for inputting the gating control pin is the first level, in the channel selecting module.
  4. Veneer according to claim 2 or 3, which is characterized in that
    The interface end of the memory module includes: command pin, clock pins, the first test data pins, the second test data pins, third test data pins and the 4th test data pins；
    Second gated end include: and the corresponding 6th channel pin of the described instruction pin and corresponding 7th channel pin of the clock pins, the 8th channel pin corresponding with first test data pins, with The corresponding 9th channel pin of the second test data pins and corresponding tenth channel pin of the third test data pins and the 11st channel pin corresponding with the 4th test data pins；
    The 6th channel pin, the 7th channel pin, the 8th channel pin, the 9th channel pin, the tenth channel pin and the 11st channel pin gating when signal for inputting the gating control pin is second electrical level, in the channel selecting module；
    The second electrical level is different from first level.
  5. The veneer according to any one of claim 2-4, which is characterized in that the memory interface includes that storage equipment detects pin, and the storage equipment detection pin is electrically connected with gating control pin；
    The storage equipment detects pin, for when jtag test equipment is electrically connected with the memory interface, the signal of the triggering input gating control pin to be first level；When storage equipment is electrically connected with the memory interface, the signal of the triggering input gating control pin is the second electrical level.
  6. Veneer according to claim 1, which is characterized in that
    The channel selecting module is also used to when forming access with the JTAG module, will input the JTAG module from the jtag test signal of the jtag test equipment；
    The first test data that test obtains for executing the corresponding test item of the jtag test signal according to the jtag test signal received from the channel selecting module, and is transmitted to the channel selecting module by the JTAG module；
    The channel selecting module is also used to first test data from the JTAG module being transmitted to the jtag test equipment by the memory interface.
  7. A kind of electronic equipment, which is characterized in that the electronic equipment includes:
    The veneer as described in any one of claim 1 to 6.
  8. A kind of method of gating, the method are applied to veneer, which is characterized in that the described method includes:
    When JTAG's jtag test equipment is electrically connected with the memory interface in the veneer, the channel selecting module in the veneer is connected to the JTAG module in the memory interface and the veneer；
    When storage equipment is electrically connected with the memory interface in the veneer, the channel selecting module is connected to the memory module in the memory interface and the veneer.
  9. According to the method described in claim 8, it is characterized in that, the channel selecting module includes the first gated end, the second gated end, common end and gating control pin, first gated end and JTAG mould The interface end of block is electrically connected, and second gated end is electrically connected with the interface end of the memory module, and the common end is electrically connected with the memory interface in the veneer；The memory interface includes that storage equipment detects pin, and the storage equipment detection pin is electrically connected with gating control pin；
    It is described when JTAG's jtag test equipment is electrically connected with the memory interface in the veneer, the channel selecting module in the veneer is connected to the JTAG module in the memory interface and the veneer, comprising:
    When the jtag test equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is the first level, the gating control pin gates first gated end, so that the jtag test equipment and the JTAG module communicate to connect；
    It is described when storing equipment and being electrically connected with the memory interface in the veneer, the channel selecting module is connected to the memory module in the memory interface and the veneer, comprising:
    When the storage equipment is electrically connected with the memory interface in the veneer, the signal for the gating control pin that the storage equipment detection pin inputs in the channel selecting module is second electrical level, the gating control pin gates second gated end, so that the storage equipment and the memory module communicate to connect；The second electrical level is different from first level.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111046444A (en) * 2019-12-06 2020-04-21 合肥市卓怡恒通信息安全有限公司 Storage encryption system based on domestic chip platform, mode switching method thereof and computer
CN117728899A (en) * 2024-02-06 2024-03-19 北京东远润兴科技有限公司 Equipment joint debugging method and device, terminal equipment and storage medium
CN117728899B (en) * 2024-02-06 2024-06-04 北京东远润兴科技有限公司 Equipment joint debugging method and device, terminal equipment and storage medium

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793987A (en) * 1996-04-18 1998-08-11 Cisco Systems, Inc. Hot plug port adapter with separate PCI local bus and auxiliary bus
DE60221010D1 (en) * 2001-05-16 2007-08-16 Ibm METHOD AND SYSTEM FOR EFFICIENT ACCESS TO REMOVED INPUT / OUTPUT FUNCTIONS IN EMBEDDED CONTROL ENVIRONMENTS
US20080078669A1 (en) * 2006-09-15 2008-04-03 Nokia Corporation Providing maintenance access via an external connector
CN102142911A (en) * 2010-08-31 2011-08-03 华为技术有限公司 Communication equipment and communication test method
CN102289419A (en) * 2010-06-17 2011-12-21 珠海全志科技有限公司 Multiplex SOC(system on a chip) integrated circuit for functional interface and debugging interface
CN102750243A (en) * 2012-07-05 2012-10-24 中颖电子股份有限公司 Easily-debugged embedded system of complex SD (secure digital) interface
CN102998614A (en) * 2012-12-14 2013-03-27 中船重工（武汉）凌久电子有限责任公司 System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method
CN103136138A (en) * 2011-11-24 2013-06-05 炬力集成电路设计有限公司 Chip, chip debugging method and communication method for chip and external devices
CN103415777A (en) * 2011-03-09 2013-11-27 英特尔公司 A functional fabric-based test controller for functional and structural test and debug

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM298123U (en) * 2006-01-27 2006-09-21 Askey Computer Corp Peripherals connecting devices with boundary scanning and testing functions

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793987A (en) * 1996-04-18 1998-08-11 Cisco Systems, Inc. Hot plug port adapter with separate PCI local bus and auxiliary bus
DE60221010D1 (en) * 2001-05-16 2007-08-16 Ibm METHOD AND SYSTEM FOR EFFICIENT ACCESS TO REMOVED INPUT / OUTPUT FUNCTIONS IN EMBEDDED CONTROL ENVIRONMENTS
US20080078669A1 (en) * 2006-09-15 2008-04-03 Nokia Corporation Providing maintenance access via an external connector
CN102289419A (en) * 2010-06-17 2011-12-21 珠海全志科技有限公司 Multiplex SOC(system on a chip) integrated circuit for functional interface and debugging interface
CN102142911A (en) * 2010-08-31 2011-08-03 华为技术有限公司 Communication equipment and communication test method
CN103415777A (en) * 2011-03-09 2013-11-27 英特尔公司 A functional fabric-based test controller for functional and structural test and debug
CN103136138A (en) * 2011-11-24 2013-06-05 炬力集成电路设计有限公司 Chip, chip debugging method and communication method for chip and external devices
CN102750243A (en) * 2012-07-05 2012-10-24 中颖电子股份有限公司 Easily-debugged embedded system of complex SD (secure digital) interface
CN102998614A (en) * 2012-12-14 2013-03-27 中船重工（武汉）凌久电子有限责任公司 System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111046444A (en) * 2019-12-06 2020-04-21 合肥市卓怡恒通信息安全有限公司 Storage encryption system based on domestic chip platform, mode switching method thereof and computer
CN117728899A (en) * 2024-02-06 2024-03-19 北京东远润兴科技有限公司 Equipment joint debugging method and device, terminal equipment and storage medium
CN117728899B (en) * 2024-02-06 2024-06-04 北京东远润兴科技有限公司 Equipment joint debugging method and device, terminal equipment and storage medium

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